STMicroelectronics ST62T52C, ST62T62C Technical data

8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,

SAFE RESET, AUTO-RELOAD TIMER AND EEPROM

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHz Maximum Clock Frequency

■ -40 to +125°C Operating Temperature Range

■ Run, Wait and Stop Modes

■ 5 Interrupt Vectors

■ Look-up Table capability in Program Memory

■ Data Storage in Program Memory:

User selectable size

■ Data RAM: 128 bytes

■ Data EEPROM: 64 bytes (none on ST 62T 5 2 C )

■ User Programmable Options

■ 9 I/O pins, fully programmable as:

– Input with pull-up resistor – Input without pull-up resistor – Input with interrupt generation – Open-drain or push-pull output – Analog Input

■ 5 I/O lines can sink up to 30mA to drive LEDs or

TRIACs directly

■ 8-bit Timer/Counter with 7-bit programmable

prescaler

■ 8-bit Auto-reload Timer with 7-bit programmable

prescaler (AR Timer)

■ Digital Watchdog

■ Oscillator Safe Guard

■ Low Voltage Detector for Safe Reset

■ 8-bit A/D Converter with 4 analog inputs

■ On-chip Clock oscillator can be driven by Quartz

Crystal Ceramic resonator or RC network

■ User configurable Power-on Reset

■ One external Non-Maskable Interrupt

■ ST626x-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a parallel port)

ST62T52C

ST62T62C/E62C

PDIP16

PSO16

SSOP16

CDIP16W

(See end of Datasheet for Ordering Information)

DEVICE SUMMARY

DEVICE

ST62T52C 1836 ST62T62C 1836 64 ST62E62C 1836 64

EPROM

(Bytes)

OTP

(Bytes)

EEPROM

Rev. 3.0

February 2002 1/78

Table of Contents

Document

Page

ST62T52C

ST62T62C/E62C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3.6 Data RAM/EEPROM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.4.3 . EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.2 Low Frequenc y Au xiliar y Os c illa tor ( LFA O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2.4 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2.5 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2.6 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.4.4 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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Table of Contents

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1.3 ARTimer alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.2.1 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.3.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.4.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Document

Page

ST62P52C

ST62P62C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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Table of Contents

Document

Page

ST6252C

ST6262 B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

2 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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1 GENERAL DESCRIPTIO N

1.1 INTRODUCTION

ST62T52C ST62T62C/E62C

The ST62T52C and ST62T62C devices is low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at lo w t o med ium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip peripherals.

The ST62E62C is the erasable EPROM version of the ST62T62C device, whi ch may be used to em ulate the ST62T52C and ST62T62C devices as well as the ST6252C and ST6262B ROM devices.

OTP and EPROM devices are functional ly identical. The ROM based versions offer the same functionality selecting as ROM options the options de-

Figure 1. Block Diagram

8-BIT

TEST/V

NMI INTER RUPT

TEST

PROGRAM

MEMORY

1836 bytes OTP

(ST62T52C, T62C)

1836 bytes EPROM

(ST62E62C)

A/D CONVERTER

DATA ROM

USER

SELECTABLE

DATA RAM

128 Bytes

DATA EEPROM

64 Bytes

(ST62T62C/E62C)

fined in the programmable option byte of the OTP/EPROM versions.

OTP devices offer all the advant ages of user programmability at low cost, which make them the ideal choice in a wide range of applications where frequent code chang es, mu ltiple code vers ions or last minute programmability are required.

These compact low -cost devices feature a Timer comprising an 8-bit counter and a 7-bit programmable prescaler, an 8-bit Auto-Reload Timer, EEPRO M data capa bility (exce pt ST62T52C ), an 8-bit A/D Converter with 4 analog inputs and a Digital Watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications.

PORT A

PORT B

PORT C PC2..PC3 / Ain

AUTORELOAD

TIMER

PA4..PA5 / Ain

PB0, PB2..PB3 / 30 mA Sink PB6 / ARTimin / 20 mA Sink PB7 / ARTimout / 20 mA Sink

STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6

POWER SUPPLY

DDVSS

OSCILLATOR

OSCin OSCout RESET

8 BIT CORE

RESET

DIGITAL

WATCHDOG

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ST62T52C ST62T62C/E62C

1.2 PIN DESCRI PTIONS V

and VSS. Power is suppl ied to the MCU vi a

these two pins. V V

is the ground connection.

is the power conn ection and

OSCin and OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. The OSCin pin is the input pin, the OSCout pin is the output pin.

RESET. The active-low RESET

pin is used to re-

start the microcontroller.

TEST/V

PP. The TEST must be held at V

for nor-

mal operation. If TEST pin is connected to a +12.5V level during the reset phase, the EPROM/OTP programming Mode is entered.

NMI. The NMI pin provides the capability for asynchronous interruption, by applying an external non maskable interrupt to the MCU. The NM I input is falling edge sensitive. It is provided with an on-chip pullup resistor (if option has been e nabled), and Schmitt trigger characteristics.

PA4-PA5. Th es e 2 lines are orga nized as one I /O port (A). Each line may be configu red under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pull outputs, analog inputs for the A/D converter.

PB0, PB2-PB3, PB6-PB7. These 5 lines are organized as one I/O port (B). Each line may be configured under software control as inputs with or without internal pull-up resistors, interrupt generating inputs with pull-up resistors, open-drain or push-pull outputs. PB6/ARTIMin and PB7/ARTI-

Mout are either Port B I/O bits or the Input and Output pins of the ARTimer. Reset state of PB2-PB3 pins can be defined by option either with pull-up or high impedance.

PB0, PB2-PB3, PB6 -PB7 sca n also sink 30mA for direct LED driving.

PC2-PC3. These 2 lines are organized as one I/O port (C). Each line may be configured under software control as input with or without internal pullup resistor, interrupt generating in put with pull-up resistor, analog input for the A/D converter, opendrain or push-pull output.

Figure 2. ST62T52C, E62C and T62C Pin Configuration

PB0

/TEST

PB2

PB3

ARTIMin/PB6

ARTIMout/PB7

1 2 3 4 5 6 7 8

PC2/Ain

PC3/Ain

NMI

RESET

OSCout

OSCin PA5/Ain PA4/Ain

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1.3 MEMORY MA P

ST62T52C ST62T62C/E62C

1.3.1 Introd uct i on

The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs.

Figure 3. Mem ory Addressing D ia gram

PROGRAM SPACE

0000h

0-63

PROGRAM

MEMORY

Briefly, Program space contains user program code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack space accommodat es six levels of stack for subroutine and interrupt service routine nesting.

DATA SPACE

000h

RAM / EEPROM BANKING AREA

03Fh 040h

DATA READ-ONLY

WINDOW

RAM

07Fh 080h 081h 082h 083h 084h

MEMORY

X REGISTER Y REGISTER V REGISTER

W REGISTER

0FF0h

0FFFh

INTERRUPT &

RESET VECTORS

0C0h

0FFh

DATA READ-ONLY

MEMORY

WINDOW SELECT

DATA RAM

BANK SELECT ACCUMULATOR

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ST62T52C ST62T62C/E62C

MEMORY MAP (Cont’d)

1.3.2 Program Space

Program Space comprises the instructions to b e executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user v ectors. Program Space is addressed via the 12-bit Program Counter register (PC register).

1.3.2.1 Program Memory Protection

The Program Mem ory i n O TP or E P ROM devices can be protected against external readout of memory by selecting the READOUT PROTECTION option in the option byte.

In the EPROM parts, READOUT PROTECTION option can be disactivated only by U.V. erasure that also results into the whole EPROM context erasure.

Note: Once the Readout Protection is activated, it is no longer possible, even for STMicroelectronics, to gain access to the OTP contents. Returned parts with a protection set can therefore not be accepted.

Figure 4. ST62T52C/T62C Program

Memory M a p

0000h

RESERVED

087Fh 0880h

USER

PROGRAM MEMORY

1836 BYTES

(OTP/EPROM)

0F9Fh 0FA0h 0FEFh 0FF0h 0FF7h 0FF8h

0FFBh 0FFCh 0FFDh

0FFEh

0FFFh

RESERVED

INTERRUPT VECTORS

RESERVED

NMI VECTOR

USER RESET VECTOR

(*) Reserved areas should be filled with 0FFh

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MEMORY MAP (Cont’d)

1.3.3 Data Space

Data Space accommodates all the data necessary for processing the user program. This space comprises the RAM resource, the proc essor core an d peripheral registers, as well as read-only data such as constants and look-up tables in OTP/EPROM.

1.3.3.1 Data ROM

All read-only data is physically stored in program memory, which also accommodates the Program Space. The program mem ory consequently contains the program code to be executed, as well as the constants and look-up tables required by th e application.

The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to acc ess the read-only data stored in OTP/EPROM.

1.3.3.2 Data RAM/EEPROM

In ST62T52C, T62C and ST62E62C devices, the data space includes 60 bytes of RAM, the accumulator (A), the i ndirect registers (X), (Y), t he short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the interrupt option register and the Data ROM Window register (DRW register).

Additional RAM and EEPROM pages can also be addressed using banks of 64 bytes located between addresses 00h and 3Fh.

1.3.4 Stack Space

Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents.

Table 1. Additional RAM / EEPROM Banks

Device RAM EEPROM

ST62T52C 1 x 64 bytes ST62T62C 1 x 64 bytes 1 x 64 bytes

ST62T52C ST62T62C/E62C

Table 2. ST62T52C, T62C and ST62E62C Data

Memory Space

RAM / EEPROM banks

DATA ROM WINDOW AREA

X REGISTER 080h Y REGISTER 081h V REGISTER 082h

W REGISTER 083h

DATA RAM 60 BYT ES

PORT A DATA REGISTER 0C0h PORT B DATA REGISTER 0C1h PORT C DAT A REGISTER 0C2h

RESERVED 0C3h PORT A DIRECTION REGISTER 0C4h PORT B DIRECTION REGISTER 0C5h

PORT C DIRECTION REGISTER 0C6h

RESERVED 0C7h

INTERRUPT OPTION REGISTER 0C8h*

DATA RO M WINDOW RE GIS T ER 0C9h*

RESERVED

PORT A OPTION REGISTER 0CCh PORT B OPTION REGISTER 0CDh

PORT C OPTION REGISTER 0CEh

RESERVED 0CFh

A/D DATA REGISTER 0D0h

A/D CONTROL REGISTER 0D1h

TIMER PRESCALER REGISTE R 0D2h

TIMER COUNTER REGISTER 0D3h

TIMER S T A T US CONTRO L REGISTER 0D4h

AR TIMER MODE CONTROL REGI STER 0D5h AR TIMER STATUS/CONTROL REGISTER1 0D6h AR TIMER STATUS/CONTROL REGISTER2 0D7h

WATCHDOG REGISTER 0D8h

AR TIMER RELOAD/CAPTURE REGISTER 0D9h

AR TIMER COMPARE REGISTER 0DAh

AR TIMER LOAD REGISTER 0 DBh

RESERVED

DATA RAM/EEPROM REGISTER 0E8h*

RESERVED 0E9h

EEPROM CONTROL REGISTER 0EAh

RESERVED

ACCUMULATOR 0FFh

* WRITE ONLY REGISTE R

000h

03Fh

040h

07Fh

084h

0BFh

0CAh 0CBh

0DCh 0DDh 0DEh

0E7h

0EBh 0FEh

9/78

ST62T52C ST62T62C/E62C

MEMORY MAP (Cont’d)

1.3.5 Data Window Register (DWR)

Data Wind ow R eg ist er (DWR)

The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes located anywhere in program memory, between address 0000h and 0FFFh (top memory address depends on the specific device). All the program memory can therefore be used to store ei ther instructions or read-only data. Indeed, the window can be moved i n steps of 64 byt es along the program memory by writing the appropriate code in the Data Window Register (DWR).

The DWR can be addressed like any RAM location in the Data Space, it is however a write-only register and therefore cannot be accessed using singlebit operations. This register is used to position the 64-byte read-only data window (from address 40 h to address 7Fh of the Data space) in program memory in 64-byte steps. The effective address of the byte to be rea d as data in program me mory is obtained by concatenating the 6 least significant bits of the register address given in the instruction (as least significant bits) and the content of the DWR register (as most significant bits), as illustrated in Figure 5 below. For instance, when address- ing location 0040h of the Data Space, with 0 loaded in the DWR register, the physical location addressed in program memory is 00h. The DWR register is not cleared on reset, therefore it must be written to prior to the first access to the Data readonly memory window area.

Address: 0C9h — Write Only

- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

Bits 6, 7 = Not used. Bit 5-0 = DWR5-DWR0:

Window Register Bits.

Data read-only memory

These are the Da ta readonly memory Window bits that correspond to the upper bits of the data read-only memory space.

Caution:

This register is undefined on reset. Neither read nor single bit instructions may be used to address this register.

Note: Care is required when handling the DWR register as it is write only. For this reason, the DWR contents should no t be changed while executing an interrupt service routine, as the service routine cannot save and then restore the register’s previous contents. If it is impossible to avoid writing to the DWR during the interrupt service routine, an image of the register m ust be saved in a RAM location, and each time the program writes to the DWR, it must also write to the image register. The image register must be written first so that, if an interrupt occurs between the two instructions, the DWR is not affected.

Figure 5. Data read-only memory Window Memo ry Add ressi ng

543210

DATA ROM

WINDOW REGISTER

CONTENTS

(DWR)

Example:

DWR=28h

ROM

ADDRESS:A19h

765432 0

1100000001

67891011

000

543210

PROGRAM SPACE ADDRESS

READ

DATA SPACE ADDRESS

40h-7Fh

IN INSTRUCTION

DATA SPACE ADDRESS

59h

VR01573C

10/78

ST62T52C ST62T62C/E62C

MEMORY MAP (Cont’d)

1.3.6 Data RAM/EEPROM Bank Register (DRBR)

Address: E8h — Write only

---

DRBR

---

DRBR

Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM

Page 2. Bit 3-1. Not used Bit 0. DRBR0. This bit, when set, selects EEP-

ROM page 0. The selection of the bank is made by programming

the Data RAM Bank Switch register (DRBR register) located at address E8h of the Data Sp ace according to Table 1. No more than one bank should be set at a time.

The DRBR register can be addressed l ike a RAM Data Space at the address E8h; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register is used to select the desired 64-byte RAM bank of the Data Space. The bank number has to be loaded in the DRB R register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3Fh address).

This register is not cleared during the MCU initialization, therefore it must be written bef ore the first access to the Data Space bank region. Refer to the Data Space description f or a dditional inform a-

tion. The DRBR register is not modified whe n an interrupt or a subroutine occurs.

Notes : Care is required when handling the DRBR register

as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the w riting of th is register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between t he two instructions the DRBR is not affected.

In DRBR Register, only 1 bit must be set. Otherwise two or more pages are enabled in parallel, producing errors.

Care must also be taken not to change the E²PROM page (when available) when the parallel writing mode is set for the E²PROM, as defined in EECTL register.

Table 3. Data RAM Bank Register Set-up

DRBR ST62T52C ST62T62C

00 None None 01 Not available EEPROM page 0 02 Not Available Not Available 08 Not available Not available

10h RAM Page 2 RAM Page 2

other Reserved Reserved

11/78

ST62T52C ST62T62C/E62C

MEMORY MAP (Cont’d)

1.3.7 EEPROM Description

EEPROM memory is located in 64-byte pages i n data space. This memory may be used by the user program for non-volatile data storage.

Data space from 00h to 3Fh is paged as described in T able 4 . EEPROM locations are accessed directly by addressing these paged sections of data space.

The EEPROM does not require dedicated instructions for read or write access. Once selected via t he Data RAM Bank Register, the active EEPROM page is controlled by the EEPROM Control Register (EECTL), which is described below.

Bit E20FF of the EECTL register must be reset prior to any write or read access to the EEPROM. If no bank has been selected, or if E2OFF is set, any access is meaningless.

Programming must be enabled by setting the E2ENA bit of the EECTL register.

The E2BUSY bit of the EECTL register is set when the EEPROM is performing a programming cycle. Any access to the EEPROM when E2B US Y is set is meaningless.

Provided E2OFF and E2BUSY are reset, an EEPROM location is read just like any other data location, also in terms of access time.

Writing to the EEPROM ma y be carried o ut in tw o modes: B yte Mode (BM ODE) and Pa rallel Mode

(PMODE). In BMODE, one byte is accessed at a time, while in PMODE up to 8 bytes in the same row are programmed simultaneously (with consequent speed and power consumption advantages, the latter being particularly important in battery powered circuits).

General Notes: Data should be written directly to the intended ad-

dress in EEPROM space. There is no buffer memory between data RAM and the EEPROM space.

When the EEPROM is busy (E2BUSY = “1”) EECTL cannot be accessed in write mode, it is only possible to read t he status of E2BUSY . This implies that as long as the EEPROM is busy, it is not possible to change the status of the EEP ROM Control Register. EECTL bits 4 and 5 are reserved and must never be set.

Care is required when dealing with the EECTL register, as some bits are w rite on ly. F or this reason, the EECTL contents must not be altered while executing an interrupt service routine.

If it is impossible to avoid writing to this register within an interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to EECTL it must also write to the image register. The image register must be written to first so that, if an interrupt occurs between the two in structions, the E E CT L wi ll not be affected.

Table 4. Row Arr a ng e men t f or Para llel Writin g of EEPRO M Lo c ations

Dataspace addresses. Banks 0 and 1.

Byte01234567 ROW7 38h-3Fh ROW6 30h-37h ROW5 28h-2Fh ROW4 20h-27h ROW3 18h-1Fh ROW2 10h-17h ROW1 08h-0Fh ROW0 00h-07h

Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.

The number of available 64-byte banks (1 or 2) is device dependent.

Note: The EEPROM is di s abled as soon as STO P inst ruction i s exec uted in order to a chieve the lowest power-consumption.

12/78

MEMORY MAP (Cont’d) Addi t i onal No t es on Parallel Mo de:

If the user wishes to perform parallel programming, the first step should be t o set the E2PAR2 bit. From this time on, the EEPROM will be addressed in write mode, the ROW address and the data will be latched and it will be possible to change them only at the end of the programmin g cycle or by resetting E2PAR2 without programming the EEPROM. After the ROW address is latched, the MCU can only “see” the selected EEPROM row and any attempt to write or read other rows will produce errors.

The EEPROM should not be read while E2PAR2 is set.

As soon as the E2PAR2 bit is set, the 8 volatile ROW latches are cleared. From this moment on, the user can load data in all or in part of the ROW. Setting E2PAR1 will modify the EEPROM registers corresponding to the ROW latches accessed after E2PAR2. For example, if the software sets E2PAR2 and accesses the EEPROM by writing to addresses 18h, 1Ah and 1Bh, and then sets E2PAR1, t he s e t h r ee re g is ters will be modified s imultaneously; the remaining bytes in the row will be unaffected.

Note that E2PAR2 is internally reset at the end of the programming cycle. This implies that the user must set the E2PAR2 bit between two parallel programming cycles. Note that if the user tries to set E2PAR1 while E2PAR2 is not set, there will be no programming cycle and the E2PAR1 bit will be unaffected. Consequently, the E2PAR1 bit cannot be set if E2ENA is low. The E2PAR1 bit can be set by the user, only if the E2ENA and E2PAR2 bits are also set.

Notes: The EEPROM page shall not be changed through the DRBR register when the E2PAR2 bit is set.

ST62T52C ST62T62C/E62C

EEPROM Control Register (EECTL)

Address: EAh — Read/Write Reset status: 00h

E2O

D5 D4

Unused.

Stand-by Enable Bit.

Bit 7 = D7: Bit 6 = E2OFF:

If this bit is set the EEPROM is disabled (any access will be meaningless) and the power consumption of the EEPROM is reduced to it s lowe st va lue .

Bit 5-4 = D5-D4:

Reserved.

Bit 3 = E2PAR1: Once in Parallel Mode, as soon as the user software sets the E2PAR1 bit, parallel writing of the 8 adjacent registers will start. This bit is internally reset at the end of the programming procedure. Note that less than 8 bytes can be written if required, the undefined bytes being unaffected by the parallel programming cycle; thi s is explained in greater d etail in the Additional Notes on Parallel Mode overleaf.

Bit 2 = E2PAR2: ONLY. This bit must be set by the user program in order to perform parallel programming. If E2PAR2 is set and the parallel start bit (E2PAR1) is reset, up to 8 adjacent bytes c an be written simultaneously. These 8 adjacent bytes are considered as a row, whose address lines A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 are the changing bits, as illustrated in Table 4. E2PAR2 is automatically reset at the end of any parallel programming procedure. It can be reset by the user s oftware before starting the programming procedure, thus leaving the EEPROM registers unchanged.

Bit 1 = E2BUSY: LY. This bit is aut omatically set by the EEP ROM control logic when the EEPROM is in programming mode. The user program should test it before any EEPROM rea d or wri te oper at ion; any att emp t to access the EEPROM while the busy bit is set will be aborted and the writing procedure in progress w ill be c ompleted.

Bit 0 = E2ENA:

EEPROM Enable Bi t.

LY. This bit enables programming of the EEPROM cells. It must be set before any write to the EEPROM register. Any attempt to write to the EEPROM when E2ENA is low is meaningless and will not trigger a write cycle.

E2PAR1E2PAR2E2BUSYE2E

WRIT E ONL Y.

MUST be kept reset.

Parallel Start Bit.

WRITE ONLY.

Parallel Mode En. Bit.

EEPROM Busy Bit.

WRITE ON-

WRITE

READ ON-

13/78

ST62T52C ST62T62C/E62C

1.4 PROGRAMMING MODES

1.4.1 Option Bytes

The two Option Bytes allow configuration capability to the MCUs. Option byte’s content is automatically read, and the selected options enabled, when the chip reset is activated.

It can only be accessed during the programmin g mode. This access is made either automatically (copy from a master device) or by selecting the OPTION BYTE PROGRAMMING mode of the programmer.

The option bytes are located in a non-user m ap. No address has to be specified.

EXTCNTL is low, STOP mode is not available with the watchdog active.

PB2-3 PULL. When set this bit removes pull-up at reset on PB2-PB3 pins. When cleared PB2-PB3 pins have an internal pull-up resistor at reset.

D4. Reserved. Must be cleared to 0. WDACT. This bit controls the watchdog activation.

When it is high, hardware activation is selected. The software activation is selected when WDACT is low.

DELAY.

This bit enables the selection of the delay internally generated after the internal reset (external pin, LVD, or watchdog activated) is released.

EPROM Code Option Byte (LSB)

PRO-

EXTC-

TECT

NTL

PB2-3

PULL

- WDACT

DELAY

OSCIL OSGEN

When DELAY is low, the delay is 2048 cycles of the oscillat or, it is of 32768 cycles when DELAY i s high.

OSCIL.

Oscillat or selection

. When this bit is low, the oscillator must b e controlled by a quartz crystal, a ceramic resonator or an ex ternal frequenc y. When it is high, the oscillator must be controlled by

EPROM Code Option Byte (MSB)

15 8

--SYNCHRO

ADC

NMI

PULL

LVD

an RC network, with only the resistor having to be externally provided.

OSGEN.

Oscillator Safe Guard

set high to enable the Oscillator Safe Guard. When this bit is low, the OSG is disabled.

The Option byte is writt en during programming ei-

D15-D13. Reserved . Must be cleared. ADC SYNCHRO

When set, an A/D c onvers ion is

started upon WAIT instruction execution, in order

ther by using the PC menu (PC driven M ode) or automatically (stand-alone mode).

1.4.2 Program Memory

to reduce supply noise. When this bit is low, an A/D conversion is started as soon as the STA bit of the A/D Converter Control Register is set.

D11. Reserved, must be cleared. D10. Reserved, must be set to one. NMI PULL.

NMI Pull-Up

. This bit must be set high to configure the NMI pin with a pull-up resistor. When it is low, no pull-up is provided.

LVD.

LVD RESET enable.

When this bit is set, safe RESET is performed by MCU when the supply voltage is too low. When this bit is cleared, only power-on reset or external RESET are active.

PROTECT.

Readout Protection.

This bit allows the protection of the software contents against piracy. When the bit PROTECT is set high, readout of the OTP contents is prevented by hardware.. When this bit is low, the user program can be read.

EXTCNTL.

External STOP MODE control.

. Whe n

EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/V programming flow of the ST62T62C is described in the User Manual of the EPROM Programming Board.

The MCUs can be programmed with the ST62E6xB EPRO M programming tools available from STMicroelectronics.

Table 5. ST62T52C/T62C Program Memory Map

Device Address Description

0000h-087Fh 0880h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

NMI Interrupt Vector

EXTCNTL is high, ST OP mode is available with watchdog active by setting NMI pin to one. When

Note: OTP/EPROM devices c an be programmed with the development tools a vailable from STMicroelectro n ics (ST62E6X-EPB or ST62 6X - KIT ) .

. This bit must be

pin. The

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

Reset Vector

14/78

PROGRAMMING MODES (Cont’d)

1.4.3 . EEPROM Data Memory

EEPROM data pages are supplied in the virgin state FFh. Partial or total programming of EEPROM data memory can be performed either through the application software or through an ex-

ST62T52C ST62T62C/E62C

ternal programmer. Any STMicroelectronics tool used for the program memory (O TP/EPROM ) c an also be used to pr o g ra m th e EEPROM data memory.

15/78

ST62T52C ST62T62C/E62C

2 CENTRAL PRO CESSING UNIT

2.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the I/O or Memory conf iguration. As such, it may b e thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 6; the controller being externally linked to both the Reset and Oscillator circuits, while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirec tly, for interrupt purposes, through the control registers.

2.2 CPU REGISTERS

The ST6 Family CPU core features six registers and three pairs of flags available to the programmer. These are described in the following paragraphs.

Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be a ddressed in Dat a space as a RAM location at address FFh. Thus the ST6 can manipulate the accumu lator just like any other register in Data space.

Figure 6ST6 Core Block Diagram

0,01 TO 8MHz

RESET

OSCin

Indirect Registers (X, Y). These t wo indi rect registers are used as pointers to memory locations in Data space. They are used in the register-indirect addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST6 i nstruction set can use the indirect registers as any other register of the data space.

Short Direct Registers (V, W). The se two registers are used to save a byte in short direct addressing mode. They can be addressed in Data space as RAM locations at addresses 82h (V) and 83h (W). They can also be acc ess ed usin g th e direct and bit direct addressing modes. Thus, the ST6 instruction set can use the short direct registers as any other register of the data space.

Program Counter (PC). The program counter is a 12-bit register which cont ains the address of the next ROM location to be processed by the core. This ROM location may b e an opcode, an operand, or the address of an operand. The 12-bit length allows the direct addressing of 4096 bytes in Program space.

OSCout

16/78

PROGRAM

ROM/EPROM

OPCODE

Program Count e r

and

6 LAYER STACK

CONTROLLER

FLAG

VALUES

FLAGS

CONTROL

SIGNALS

A-DATA

ADDRESS/READ LINE

ADDRESS

DECODER

B-DATA

ALU

RESULTS TO DATA SPACE (WRITE LINE)

INTERRUPTS

256

DATA SPACE

DATA

RAM/EEPROM

DATA

ROM/EPROM

DEDICATIONS

ACCUMULATOR

VR01811

CPU REGISTERS (Cont’d)

ST62T52C ST62T62C/E62C

However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register.

The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways:

- JP (Jump) instructionPC=Jump address

- CALL instructionPC= Call address

- Relative Branch Instruction.PC= PC +/- offset

- Interrupt PC=Interrupt vector

- ResetPC= Reset vector

- RET & RETI instructionsPC= Pop (stack)

- Normal instructionPC= PC + 1 Flags (C, Z). The ST6 CPU includes three pairs of

flags (Carry and Zero), each pair being associated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskabl e Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is u sed during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt m ode (CNMI, ZNMI).

The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable I nterrupt) is generated, the ST 6 CPU uses the Interrupt flags (resp. the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context switching and thus retain their status.

The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the val ue of the bit tested in a bit test instruction; it also participates in the rotate left instruction.

The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared.

Switching between the three sets of flags is performed automatically when an NMI, an interrupt or

a RETI instructions occurs. As the NMI mode is automatically selected aft er the reset of the MCU, the ST6 core uses at first the NMI flags.

Stack. The ST6 CP U includes a true LIFO hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the PC is shifted into the first level (the original contents of the sixth stac k level are lost). Whe n a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of ea ch level is popped back into the previous level. Since the acc umulator, in common with all other data space registers, is not stored in this sta ck, management of these registers should be performed within the subroutine. The stack will rem ain in it s “deep est” pos it ion if more than 6 nested calls or interrupts are executed, and consequent ly the last return address wi ll be lost. It will als o remain in its highe st pos ition if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed.

Figure 7S T6 C P U Pro gramming Mo de

X R EG. POINTER

INDEX

INTERRUPTFLAGS

NMI FLAGS

b7 b7 b7

b7 b7

PROGRAM COUNTER

SIX LEVELS

STACK REGISTER

YREG.POINTER

VREGISTER

WREGISTER

ACCUMULATOR

b0 b0 b0

b0 b0

b0b11

CZNORMAL FLAGS

SHORT

DIRECT

ADDRESSING

MODE

VA000423

17/78

ST62T52C ST62T62C/E62C

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 CLOCK SYSTEM

The MCU f ea tu r es a Main Oscilla tor wh ic h c an be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a s uitable ceramic resonator, or with an external resistor

). In addition, a Low Frequency Auxiliary Os-

NET

cillator (LFAO) can be switched in for security reasons, to reduce power consumption, or to offer the benefits of a back-up clock system.

The Oscillator Safeguard (OSG) option filters spikes from the oscillator lines, provides access to the LFAO to provide a backup oscillator in the event of main osc illator failure and al so automat ically limits the internal clock frequency (f function of V

, in order to guarantee correct oper-

INT

) as a

ation. These functions are il lustrated in Figure 9.,

Figure 10., Figure 11. and Figure 12.. Figure 8. illustrates various possible oscillator con-

figurations using an external crystal or ceramic resonator, an external clock input, an external resistor (R

), or the lowest cost solution using only the

NET

LFAO. C

an CL2 should have a capacitance in the

range 12 tST6_CLK1o 22 pF for an oscillator frequency in the 4-8 MHz range.

The internal MCU clock frequency (f

) is divided

INT

by 12 to drive the Timer, the A/D converter and the Watchdog timer, and by 13 to drive the CPU core, as may be seen in Figure 11..

With an 8MHz oscillator frequency, the fastest machine cycle is therefore 1.625µs.

A machine cycle is the smallest unit of ti me needed to execute any operation (for instance, to increment the Program Counter). An instruction may requi re two, four, or five machine cycles for execution.

3.1.1 Main Oscillator

The oscillator configuration may be specified by selecting the appropriate option. When the CRYSTAL/RESONATOR option is selected, it must be used with a quartz crystal, a ceramic resonator or an external signal provided on the OSCin pin. When the RC NETWORK option is selected, the system clock is generated by an external resistor.

The main oscillator can be turned off (when the OSG ENABLED option is se lected ) by set ting th e OSCOFF bit of the ADC Control Register. The Low Frequency Auxiliary Oscillator is automatically started.

Figure 8. Os cill a tor C on f ig urations

CRYSTAL/RESONATOR CLOCK

CRYSTAL/RESONATOR option

ST6xxx

OSC

out

NET

OSC

L1n

EXTERNAL CLOCK

CRYSTAL/RESONATOR option

OSC

RC NETWORK

RC NETW O RK option

OSC

INTEGRATED CL OCK

CRYSTAL/RESONATOR option

OSG ENABLED option

OSC

18/78

ST62T52C ST62T62C/E62C

CLOCK SYSTEM (Cont’d)

Turning on the main oscillator is achieved by resetting the OSCOFF bit of the A/D Converter Control Register or by resetting the MCU. Restarting the main oscillator implies a delay comprising the oscillator start up delay period plus the duration of the software instruction at f

clock frequency.

LFAO

3.1.2 Low Frequency Auxiliary Oscillator

(LFAO)

The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines. Secondly, it offers a fully integrated system clock, without any external components. Lastly, it acts as a safety oscillator in case of main oscillator failure.

This oscillator is available when the OSG ENABLED option is selected. In this case, it automatically starts one of its periods after the first missing edge from the main oscillator, whatever the reason (main oscillator defective, no clock circuitry provided, main osc illator swit ched off...).

User code, normal interrupts, WAIT and STOP instructions, are processed as normal, at the reduced f

frequency. The A/D converter accura-

LFAO

cy is decreased, since the internal frequency is below 1MHz.

At power on, the Low Frequency Aux ilia ry Osc ill ator starts faster than the Main Oscillator. It therefore feeds the on-chip counter generating the POR delay until the Main Oscillator runs.

The Low Frequency Auxiliary Oscillator is automatically switched off as soon as the main oscillator sta r ts.

ADCR

Address: 0D1h — Read/Write

ADCR7ADCR6ADCR5ADCR4ADCR3OSC

OFF

ADCR1ADCR

Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:

ADC Control Register

. These bits are not used.

Bit 2 = OSCOFF. When low, this bit enables m ai n oscillator to run. The main oscillator is switched off when OSCOFF is high.

3.1.3 Oscillator Safe Guard

The Oscillator Safe Guard (OSG) affords drastically increased operational integrity in ST62x x dev ices. The OSG circuit provides three basic func-

tions: it filters spikes from the oscillator lines which would result in over frequency to the ST62 CPU; it gives access to the Low Frequency Auxiliary Oscillator (LFAO), used to ensure minimum processing in case of main oscillator failure, to offer reduced power consumption or to provide a fixed frequency low cost oscillator; finally, it automatically limits the internal clock frequen cy as a function of supply voltage, in order to ensure correct operation even if the power supply should drop.

The OSG is enabled or disab led by choosin g the relevant OSG option. It may b e viewed as a filter whose cross-over frequency is device dependent.

Spikes on the oscillator lines result in an effectively increased internal clock frequency. In the absence of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The OSG filters out such spikes (as illustr ated in Figure

9.). In all cases, when the OSG is active, the max-

imum internal clock frequency, f f

, which is supply voltage dependent. T his re-

OSG

lationship is illustrated in Figure 12.. When the OSG is enabled, the Low Frequency

Auxiliary Oscillator may be accessed. This oscillator starts operating after the first missing edge of the main oscillator (see Figu re 10.).

Over-frequency, at a given power supp ly level, is seen by the OSG as spikes; it therefore filte rs out some cycles in order that the internal clock frequency of the device is kept within the range t he particular device can stand (depending o n V and below f

: the maximum authorised frequen-

OSG

cy with OSG enabled. Note. The OSG should be used wherever possible

as it provides maximum safet y. Care must be taken, however, as it ca n increase power consumption and reduce the maximum operating frequency to f

OSG

Warning: Care has to be taken when using the OSG, as the internal frequency is defined between a minimum and a maximum value and is not accurate.

For precise timing measu remen ts, it is no t re commended to use the OSG and it should not be enabled in applications that use the SPI or the UART.

It should also be noted that power consum ption in Stop mode is higher when the OSG is enabled (around 50µA at nominal conditions and room temperature).

, is limited to

INT

19/78

ST62T52C ST62T62C/E62C

CLOCK SYSTEM (Cont’d) Figure 9. OSG Fi l terin g P rin c i pl e

(1)

(2)

(3)

(4)

(1)

Maximum Frequency for the device to work correctly

(2)

Actual Quartz Crystal Frequency at OSCin pin

(3)

Noise from OSCin

(4)

Resulting Internal Frequency

Figure 10. OSG Emergency Oscillator Principle

Main

Oscillator

Emergency

Oscillator

Internal

Frequency

VR001932

20/78

VR001933

CLOCK SYSTEM (Cont’d) Figure 11. Clock Circuit Block Diagram

ST62T52C ST62T62C/E62C

POR

OSG

MAIN

OSCILLATOR

LFAO

Main Oscillator off

Figure 12. Maximum Operating Frequency (f

Maximum FREQUENCY (MHz)

2.5

GUARANTEED

FUNCTIONALITY IS NOT

IN THIS AREA

3.644.555.56

M U X

) versus Supply Voltage (VDD)

MAX

INT

OSG

Min (at 85 °C)

OSG

Min (at 125°C)

OSG

Core

TIMER 1

Watchdog

SUPPLY VOLTAGE (V

Notes:

1. In this area, operation is guaranteed at the quartz crystal frequency.

2. When the OSG is disabled, operation in this area is guaranteed at the crystal frequency. When the OSG is enabled, operation in this area is guaranteed at a frequency of at least f

OSG Min.

3. When the OSG is disabled, operation in this

)

VR01807J

area is guaranteed at the quartz crystal frequency. When the OSG is enab led, access to this area is prevented. The internal frequency is kept a f

OSG.

4. When the OSG is disabled, operation in this area is not guaranteed When the OSG is enab led, access to this area is prevented. The internal frequency is kept at f

OSG.

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ST62T52C ST62T62C/E62C

3.2 RESETS

The MCU can be reset in four ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. – by Low Voltage Detection (LVD)

3.2.1 RESET Input

The RESET

pin may be connected to a device of the application board in order to reset the MCU if required. The RESET

pin may be pulled low in RUN, WAIT or STOP mode. This input can be used to reset the MCU internal state and ensure a correct start-up procedure. The pin i s active low and features a Schmitt trigger input. The internal Reset signal is generated by adding a delay to the external signal. Therefore even short pulses on the RESET

pin are acceptable, provide d VDD has completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the RESET

If RESET

pin is held low.

activation occurs in the RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the Inputs and Outputs are configured as inputs with pull-up resistors and the main Osc illat o r is res t ar ted. When the le v el o n the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

If RESET

pin activation occurs in the STOP mode, the oscillator starts u p and a ll Inputs and Out puts are configured as inputs with pull-up resistors. When the level of the RESET

pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

3.2.2 Power-on Reset

The function of the POR circuit cons ists in waking up the MCU by detecting around 2V a dynamic (rising edge) variation of the VDD Supply. At the beginning of this sequence, the MCU is configured in the Reset state: al l I/O ports are c onfigured as inputs with pull-up resistors a nd no instruction is executed. When the power supply voltage rises to a sufficient level, the o scillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize befo re ex ecut ing the first instruction. The initialization sequence

is executed immediately following the internal delay.

To ensure correct s tart-up, the user shoul d take care that the VDD Supply is stabilized at a sufficient level for the chosen frequency (see recommended operation) before the reset sign al is released. In addition, supply rising must start from 0V.

As a consequence, the POR does not allow to supervise static, slowly rising, or falling, or noisy (present in g o s c illation) VDD supplies.

An external RC network connected to the RESET pin, or the LVD reset can b e used instead to get the best performances.

Figure 13. Reset and Interrupt Processing

RESET

NMI M ASK SET

INT LATCH CLEARED

( IF PRESENT )

SELECT

NMI MODE FLAGS

PUT FFEH

ON ADDRESS BUS

YES

IS RESET STILL

PRESENT?

LOAD PC

FROM RESET LOCATIONS

FFE/FFF

FETCH INSTRUCTION

VA000427

22/78

RESETS (Cont’d)

3.2.3 Watchdog Reset

The MCU provides a Wat chdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog regi ster is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongs t ot her things, resets the watchdog counter.

ues, allowing hysteresis effect. Reference value in case of voltage drop has been set lower than the reference value for power-on in order to avoid any parasitic Reset when MCU start's running and sinking current on the supply.

As long as the s upply voltage is below the reference value, there is a internal and static RESET command. The MCU can start only when the sup-

The MCU restarts just as though the Reset had been generated by the RESET

pin, including the

built-in stabilisation de l a y peri o d.

3.2.4 LVD Reset

The on-chip Low Voltage Detector, selectable as user option, features static Reset when supply voltage is below a reference value. Thanks to this feature, external reset circuit can be removed while keeping the application safety. This SAFE RESET is effective as well in Power-on phase as

ply voltage rises over the reference value. Therefore, only two operating mode exist for the MCU: RESET active below the voltage reference, and running mode over the voltage reference as shown on the Figure 14., that represents a powerup, power-down sequence.

Note: When the RESET state is controlled by one of the internal RESET sourc es (Low Voltage Detector, Watchdog, Power on Reset), the RESET pin is tied to low logic level.

in power supply drop with different reference val-

Figure 14. LVD Reset on Power-on and Power-down (Brown-out)

ST62T52C ST62T62C/E62C

RESET

3.2.5 Application Notes

No external resistor is requ ired bet ween V

and

the Reset pin, thanks to the built-in pull-up device.

RESET

time

VR02106 A

Direct external connection of the pin RESET to V

must be avoided in order to ensure safe be-

haviour of the internal reset sources (AND.Wired structure).

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ST62T52C ST62T62C/E62C

RESETS (Cont’d)

3.2.6 MCU Initialization Sequence

When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (located in program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a Reset , the Interrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode; this prevents the initialisation routine from being interrupted. The initialisation routine should therefore be t erminated by a RETI instruction, in order to revert to normal mode and enable interrupts. If no pending interrupt is present at the end of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETI instruction. If, however, a pending interrupt is present, it will be serviced.

Figure 16. Reset Block Diagram

Figure 15. Reset and Interrupt Processing

RESET

VECTOR

INITIALIZATION ROUTINE

RETI

JP:2 BYTES/4 CYCLES

RETI: 1 BYTE/2 CYCLES

VA00181

RESET

POWER

WATCHDOG R ESE T

LVD RESET

1) Resis tive ESD protection. Val ue not guaranteed.

ESD

ON RESET

OSC

AND. Wired

RESET

COUNTER

RESET

ST6 INTERNAL RESET

VR02107A

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