M24C64
M24C32
64/32 Kbit Serial I²C Bus EEPROM
■ Compat ible with I
■ Two Wire I
2
C Extended Addressing
2
C Serial Interface
Supports 400 kHz Protocol
■ Single Supply Voltage:
– 4.5V to 5.5V for M24Cxx
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 3.6V for M24Cxx-R
■ Hardware Write Control
■ BYTE and PAGE WRITE (up to 32 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Tim ed P ro g ra m ming Cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Behavior
■ 1 Million Erase/Write Cycles (minimum)
■ 40 Year Data Retention (minimum)
DESCRIPTION
These I
2
C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192x8 bits (M24C64) and 4096x8 bits
(M24C32), and operate down to 2.5 V (for the -W
version of each device), and down to 1.8 V (for the
-R version of each device).
The M24C64 and M24C32 are available in Plastic
Dual-in-Line, Plastic Small Outline and Thin Shrink
Small Outline packages.
8
1
PSDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
Figure 1. Logic Diagram
V
CC
14
1
TSSOP14 (DL)
169 mil width
8
1
SO8 (MW)
200 mil width
Table 1. Signal Names
E0, E1, E2 Chip Enable Inputs
SDA Serial Data/Address Input/
Output
SCL Serial Clock
WC
V
CC
V
SS
Write Control
Supply Voltage
Ground
3
E0-E2 SDA
SCL
WC
M24C64
M24C32
V
SS
AI01844B
1/18July 1999
M24C64, M24C32
Figure 2A. DIP Connections
M24C64
M24C32
1
E0 V
2
3
E2
4
SS
AI01845B
Figure 2B. SO C on ne ct i on s
M24C64
M24C32
E0 V
E2
SS
1
2
3
4
AI01846B
Figure 2C. TSSOP Connections
M24C64
M24C32
14
1
E0 V
13
E2
2
12
3
4
11
5
10
69
7
8
AI02129
8
CC
7
WCE1
6
SCL
5
SDAV
NC
NC NC
SS
Note: 1. NC = Not Connected
These memory devices are compatible with the
2
I
C extended memory standard. This is a two wire
CC
WCE1
NC
NCNC
SCL
SDAV
serial interface that uses a bi-directiona l data bus
and serial clock. The memory carries a built-in 4bit unique Device Type Identifier code (1010) in
accordance with the I
8
7
6
5
CC
WCE1
SCL
SDAV
The memory behaves as a slave device in the I
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, genera ted by the
bus master. The START condition is followed by a
Device Select Code and RW
2
C bus definition.
bit (as described in
2
C
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the mem ory in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD Electrostatic Discharge Voltage (Human Body model)
Note: 1. Exc ept for the rating “Operating Temperature Range”, stresses above those l i sted in the Table “Absolute Maximum Ratings” may
2/18
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indica te d i n the Operating secti ons of this specification is not im plied. Exposure to Absolute Ma xim um Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL -STD-883C, 3015.7 (100 pF, 1500 Ω)
Ambient Operating Temperature -40 to 125 °C
Storage Temperature -65 to 150 °C
Lead Temperature during Soldering
Input or Output range -0.6 to 6.5 V
Supply Voltage -0.3 to 6.5 V
1
PSDIP8: 10 sec
SO8: 40 sec
TSSOP14: t.b.c.
2
260
215
t.b.c.
4000 V
°C
M24C64, M24C32
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and after a NoAck for READ.
Power On Reset: V
Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is
held active until the V
voltage has reached the
CC
POR threshold value, and all operations are dis-
abled – the device will not respond to any command. In the same way, when V
drops from the
CC
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any com ma nd. A s table a nd v alid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from
the SCL line to V
. (Figure 3 indicates how the
CC
value of the pull-up res istor c an be calculated). In
most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
. (Figure 3 indicates how the value of the
to V
CC
pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs may be driven dynamically or tied to
or VSS to establish the device select code (but
V
CC
note that the V
and VIH levels for the inputs are
IL
CMOS compatible, not TTL compatible).
Write Control (WC
The hardware Write Control pin (WC
)
) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC
=VIL) or disable (WC=VIH)
write instructions to the entire memory area. When
unconnected, the WC
V
, and write operations are allowed.
IL
When WC
=1, Device Select and Address bytes
input is internally read as
are acknowledged, Data bytes are not acknowledged.
Please see the Application Note
AN404
for a more
detailed description of the Write Control feature.
DEVICE OPERATION
2
The memory device supports the I
C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001
. Any device that sends data on to the bus
is defined to be a transm itter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is k nown as the master,
and the other as the slave. A data transfer can only
be initiated by the mas ter, which wi ll also provide
the serial clock for synchronization. The memory
Figure 3. Maximum R
20
16
12
8
Maximum RP value (kΩ)
4
0
10 1000
Value versus Bus Capacitance (C
L
fc = 100kHz
fc = 400kHz
100
C
(pF)
BUS
) for an I2C Bus
BUS
V
MASTER
CC
SDA
SCL
R
R
C
BUS
L
C
BUS
AI01665
3/18
L
M24C64, M24C32
2
Figure 4. I
C Bus Protocol
SCL
SDA
SCL
SDA
SCL
SDA
START
CONDITION
START
CONDITION
SDA
INPUT
1 23 789
MSB
1 23 789
MSB ACK
SDA
CHANGE
CONDITION
ACK
STOP
STOP
CONDITION
device is always a slave device in all comm unication.
Start Condition
START is identified by a high t o low transition of
the SDA line while the clock, SCL, is stable i n the
high state. A START condition must precede any
data transfer comman d. Th e m em ory devi ce continuously monitors (except during a program ming
cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates com munication between the memory device and the bus master. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
4/18
AI00792
condition at the end of a Write command triggers
the interna l EEPRO M write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9
th
clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transition, and the data must change
only
when the SCL
line is low.
Memory Addressing
To start communication betwee n the bus master
and the slave memory, the master must initiate a
M24C64, M24C32
Table 3. Device Select Code
b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code 1 0 1 0 E2 E1 E 0 RW
Note: 1. The most significant bit, b7, is sent first.
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code i s fur-
1
Device Type Identifier Chip Enable RW
Table 4. Most Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8
Note: 1. b15 to b13 are Don’t Care on the M24C6 4 series.
b15 to b12 are Don’t Care on the M 24C32 serie s.
ther su bdi v i d ed i n to : a 4 -b i t D e vi c e T y pe Iden t if i er,
and a 3-bit Chip Enable “Address” (E2, E1, E0).
To address the memory array, the 4-bit Device
Table 5. Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I
code on its Chip Enable inputs. When the Dev ice
2
C bus. Each one is given a uniq ue 3-bit
to b12 are treated as Don’t Care bits on the
M24C32 me m o r y .
Select Code is received on the SDA bus, the memory only responds if the Chip Select Code is the
same as the pattern applied to its Chip Enable
pins.
th
The 8
bit is th e RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Cod e, th e corresponding memory gives an acknowledgment on the SDA bus during the 9
th
bit time. If the memo ry does n ot match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the m aster and
the slave is ended with a STOP condition.
Each data byte in the m emory has a 16-bit (two
byte wide) address. The Most Significant Byte (Table 4) is sent first, f ollowed by the Least significant
Byte (Table 5). Bits b15 to b0 form t he addre ss of
the byte in memory. Bits b15 to b13 are treated as
a Don’t Care bit on the M24C64 memory. Bits b15
Write Operations
Following a START con dition the ma ster sends a
Device Select Code with the RW
bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory responds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC
=1 (during a period o f time from the START
condition until the end of the two address bytes)
will not modify the me mory c ontents, and t he ac-
not
companying data bytes will
be acknowledged
(as shown in Figure 5).
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed lo cation is write
protected by the WC
pin, the memory replies with
a NoAck, and the location is not modified. If, in-
Table 6. Operating Modes
Mode RW bit
Current Address Read 1 X 1 START, Device Select, RW
Random Address Read
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0 V
Page Write 0 V
Note: 1. X = V
IH
or V
.
IL
0X
1 X reSTART, Device Select, RW
WC
1
IL
IL
Bytes Initial Sequence
= ‘1’
1
START, Device Select, RW
1 START, Device Select, RW = ‘0’
≤ 32 START, Device Select, RW = ‘0’
= ‘0’, Address
= ‘1’
5/18
M24C64, M24C32
Figure 5. Wri te Mo de S e qu e nces with WC=1 (data write inhib i ted)
WC
ACK ACK ACK NO ACK
BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN
R/W
START
WC
ACK ACK ACK NO ACK
PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1
R/W
START
WC (cont'd)
NO ACK NO ACK
PAGE WRITE
(cont'd)
DATA IN N
STOP
STOP
DATA IN 2
AI01120B
stead, the WC pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
Page Write
The Page Write mode allows u p to 32 by tes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory add ress bits
(b12-b5 for the M24C64 and b11-b5 for the
M24C32) are the same. If more bytes are sent
than will fit up to the end of t he row, a conditi on
known as ‘roll-over’ occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).
The master sends from one up to 32 bytes of data,
each of which is acknow ledged by the memory if
the W C
pin is low. If the WC pin is high, the contents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte i s tran sferred, the i nte rnal
6/18
byte address counter (the 5 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition immediately after the Ack bit (in the “10
th
bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not t rigger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not respond to any requests.
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