M24C64
M24C32
64/32 Kbit Serial I²C Bus EEPROM
■ Compat ible with I
■ Two Wire I
2
C Extended Addressing
2
C Serial Interface
Supports 400 kHz Protocol
■ Single Supply Voltage:
– 4.5V to 5.5V for M24Cxx
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 3.6V for M24Cxx-R
■ Hardware Write Control
■ BYTE and PAGE WRITE (up to 32 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Tim ed P ro g ra m ming Cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Behavior
■ 1 Million Erase/Write Cycles (minimum)
■ 40 Year Data Retention (minimum)
DESCRIPTION
These I
2
C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192x8 bits (M24C64) and 4096x8 bits
(M24C32), and operate down to 2.5 V (for the -W
version of each device), and down to 1.8 V (for the
-R version of each device).
The M24C64 and M24C32 are available in Plastic
Dual-in-Line, Plastic Small Outline and Thin Shrink
Small Outline packages.
8
1
PSDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
Figure 1. Logic Diagram
V
CC
14
1
TSSOP14 (DL)
169 mil width
8
1
SO8 (MW)
200 mil width
Table 1. Signal Names
E0, E1, E2 Chip Enable Inputs
SDA Serial Data/Address Input/
Output
SCL Serial Clock
WC
V
CC
V
SS
Write Control
Supply Voltage
Ground
3
E0-E2 SDA
SCL
WC
M24C64
M24C32
V
SS
AI01844B
1/18July 1999
M24C64, M24C32
Figure 2A. DIP Connections
M24C64
M24C32
1
E0 V
2
3
E2
4
SS
AI01845B
Figure 2B. SO C on ne ct i on s
M24C64
M24C32
E0 V
E2
SS
1
2
3
4
AI01846B
Figure 2C. TSSOP Connections
M24C64
M24C32
14
1
E0 V
13
E2
2
12
3
4
11
5
10
69
7
8
AI02129
8
CC
7
WCE1
6
SCL
5
SDAV
NC
NC NC
SS
Note: 1. NC = Not Connected
These memory devices are compatible with the
2
I
C extended memory standard. This is a two wire
CC
WCE1
NC
NCNC
SCL
SDAV
serial interface that uses a bi-directiona l data bus
and serial clock. The memory carries a built-in 4bit unique Device Type Identifier code (1010) in
accordance with the I
8
7
6
5
CC
WCE1
SCL
SDAV
The memory behaves as a slave device in the I
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, genera ted by the
bus master. The START condition is followed by a
Device Select Code and RW
2
C bus definition.
bit (as described in
2
C
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the mem ory in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD Electrostatic Discharge Voltage (Human Body model)
Note: 1. Exc ept for the rating “Operating Temperature Range”, stresses above those l i sted in the Table “Absolute Maximum Ratings” may
2/18
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indica te d i n the Operating secti ons of this specification is not im plied. Exposure to Absolute Ma xim um Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL -STD-883C, 3015.7 (100 pF, 1500 Ω)
Ambient Operating Temperature -40 to 125 °C
Storage Temperature -65 to 150 °C
Lead Temperature during Soldering
Input or Output range -0.6 to 6.5 V
Supply Voltage -0.3 to 6.5 V
1
PSDIP8: 10 sec
SO8: 40 sec
TSSOP14: t.b.c.
2
260
215
t.b.c.
4000 V
°C
M24C64, M24C32
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and after a NoAck for READ.
Power On Reset: V
Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is
held active until the V
voltage has reached the
CC
POR threshold value, and all operations are dis-
abled – the device will not respond to any command. In the same way, when V
drops from the
CC
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any com ma nd. A s table a nd v alid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from
the SCL line to V
. (Figure 3 indicates how the
CC
value of the pull-up res istor c an be calculated). In
most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
. (Figure 3 indicates how the value of the
to V
CC
pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs may be driven dynamically or tied to
or VSS to establish the device select code (but
V
CC
note that the V
and VIH levels for the inputs are
IL
CMOS compatible, not TTL compatible).
Write Control (WC
The hardware Write Control pin (WC
)
) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC
=VIL) or disable (WC=VIH)
write instructions to the entire memory area. When
unconnected, the WC
V
, and write operations are allowed.
IL
When WC
=1, Device Select and Address bytes
input is internally read as
are acknowledged, Data bytes are not acknowledged.
Please see the Application Note
AN404
for a more
detailed description of the Write Control feature.
DEVICE OPERATION
2
The memory device supports the I
C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001
. Any device that sends data on to the bus
is defined to be a transm itter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is k nown as the master,
and the other as the slave. A data transfer can only
be initiated by the mas ter, which wi ll also provide
the serial clock for synchronization. The memory
Figure 3. Maximum R
20
16
12
8
Maximum RP value (kΩ)
4
0
10 1000
Value versus Bus Capacitance (C
L
fc = 100kHz
fc = 400kHz
100
C
(pF)
BUS
) for an I2C Bus
BUS
V
MASTER
CC
SDA
SCL
R
R
C
BUS
L
C
BUS
AI01665
3/18
L
M24C64, M24C32
2
Figure 4. I
C Bus Protocol
SCL
SDA
SCL
SDA
SCL
SDA
START
CONDITION
START
CONDITION
SDA
INPUT
1 23 789
MSB
1 23 789
MSB ACK
SDA
CHANGE
CONDITION
ACK
STOP
STOP
CONDITION
device is always a slave device in all comm unication.
Start Condition
START is identified by a high t o low transition of
the SDA line while the clock, SCL, is stable i n the
high state. A START condition must precede any
data transfer comman d. Th e m em ory devi ce continuously monitors (except during a program ming
cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates com munication between the memory device and the bus master. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
4/18
AI00792
condition at the end of a Write command triggers
the interna l EEPRO M write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9
th
clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transition, and the data must change
only
when the SCL
line is low.
Memory Addressing
To start communication betwee n the bus master
and the slave memory, the master must initiate a
M24C64, M24C32
Table 3. Device Select Code
b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code 1 0 1 0 E2 E1 E 0 RW
Note: 1. The most significant bit, b7, is sent first.
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code i s fur-
1
Device Type Identifier Chip Enable RW
Table 4. Most Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8
Note: 1. b15 to b13 are Don’t Care on the M24C6 4 series.
b15 to b12 are Don’t Care on the M 24C32 serie s.
ther su bdi v i d ed i n to : a 4 -b i t D e vi c e T y pe Iden t if i er,
and a 3-bit Chip Enable “Address” (E2, E1, E0).
To address the memory array, the 4-bit Device
Table 5. Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I
code on its Chip Enable inputs. When the Dev ice
2
C bus. Each one is given a uniq ue 3-bit
to b12 are treated as Don’t Care bits on the
M24C32 me m o r y .
Select Code is received on the SDA bus, the memory only responds if the Chip Select Code is the
same as the pattern applied to its Chip Enable
pins.
th
The 8
bit is th e RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Cod e, th e corresponding memory gives an acknowledgment on the SDA bus during the 9
th
bit time. If the memo ry does n ot match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the m aster and
the slave is ended with a STOP condition.
Each data byte in the m emory has a 16-bit (two
byte wide) address. The Most Significant Byte (Table 4) is sent first, f ollowed by the Least significant
Byte (Table 5). Bits b15 to b0 form t he addre ss of
the byte in memory. Bits b15 to b13 are treated as
a Don’t Care bit on the M24C64 memory. Bits b15
Write Operations
Following a START con dition the ma ster sends a
Device Select Code with the RW
bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory responds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC
=1 (during a period o f time from the START
condition until the end of the two address bytes)
will not modify the me mory c ontents, and t he ac-
not
companying data bytes will
be acknowledged
(as shown in Figure 5).
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed lo cation is write
protected by the WC
pin, the memory replies with
a NoAck, and the location is not modified. If, in-
Table 6. Operating Modes
Mode RW bit
Current Address Read 1 X 1 START, Device Select, RW
Random Address Read
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0 V
Page Write 0 V
Note: 1. X = V
IH
or V
.
IL
0X
1 X reSTART, Device Select, RW
WC
1
IL
IL
Bytes Initial Sequence
= ‘1’
1
START, Device Select, RW
1 START, Device Select, RW = ‘0’
≤ 32 START, Device Select, RW = ‘0’
= ‘0’, Address
= ‘1’
5/18
M24C64, M24C32
Figure 5. Wri te Mo de S e qu e nces with WC=1 (data write inhib i ted)
WC
ACK ACK ACK NO ACK
BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN
R/W
START
WC
ACK ACK ACK NO ACK
PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1
R/W
START
WC (cont'd)
NO ACK NO ACK
PAGE WRITE
(cont'd)
DATA IN N
STOP
STOP
DATA IN 2
AI01120B
stead, the WC pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
Page Write
The Page Write mode allows u p to 32 by tes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory add ress bits
(b12-b5 for the M24C64 and b11-b5 for the
M24C32) are the same. If more bytes are sent
than will fit up to the end of t he row, a conditi on
known as ‘roll-over’ occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).
The master sends from one up to 32 bytes of data,
each of which is acknow ledged by the memory if
the W C
pin is low. If the WC pin is high, the contents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte i s tran sferred, the i nte rnal
6/18
byte address counter (the 5 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition immediately after the Ack bit (in the “10
th
bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not t rigger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not respond to any requests.
Figure 6. Wri te Mo de S e qu e nces with WC=0 (data write enab led )
WC
M24C64, M24C32
ACK
BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN
R/W
START
WC
ACK ACK ACK ACK
PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1
R/W
START
WC (cont'd)
ACKACK
PAGE WRITE
(cont'd)
DATA IN N
ACK ACK ACK
STOP
DATA IN 2
STOP
AI01106B
7/18
M24C64, M24C32
Figure 7. Wri te Cy cle Pol l in g Fl owchart using A CK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
NO
Returned
First byte of instruction
with RW = 0 already
decoded by M24xxx
ReSTART
STOP
YES
Next
Operation is
Addressing the
Memory
WRITE Operation
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory disconnects itself from the bus, and copies the data from
its internal latches to the memory cells. The maximum write time (t
) is shown in Table 9, but the
w
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the m aster issues a ST ART condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it responds with
an Ack, indicating that the m emory is ready to
receive the second part of the nex t instruction
(the first byte of this instruction having been sent
during Step 1).
YESNO
Send
Byte Address
Proceed
Proceed
Random Address
READ Operation
AI01847
Read Operations
Read operations are performed independently of
the state of the WC
pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then,
without
sending a STOP condition, the master sends another START condi tion, and repeats
the Device Select Code, with the RW
The memory acknowledge s this, and outputs the
contents of the addressed byte. The master m ust
not
acknowledge the by te output, and terminates
the transfer with a STOP condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read m ode, following a START
condition, the master sends a Device Select Code
with the RW
bit set to ‘1’. The memory acknowl-
edges this, and outputs the byte addressed by the
bit set to ‘1’.
8/18
Figure 8. Read Mode Sequences
M24C64, M24C32
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
ACK
DEV SEL DATA OUT
R/W
START
ACK
DEV SEL * BYTE ADDR BYTE ADDR
R/W
START
ACK ACK ACK NO ACK
DEV SEL DATA OUT 1
R/W
START
ACK ACK ACK
DEV SEL * BYTE ADDR BYTE ADDR
NO ACK
STOP
ACK ACK ACK
DEV SEL * DATA OUT
R/W
START
DATA OUT N
STOP
ACK ACK
DEV SEL * DATA OUT 1
NO ACK
STOP
R/W
START
ACK NO ACK
DATA OUT N
STOP
Note: 1. The seven most signi fi cant bits of the D evice Select Code of a Random Read (in the 1st and 4th bytes) must be i d entica l.
internal address counter. The counter is then incremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8,
out
acknowledging the byte output.
with-
Sequenti a l Rea d
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master
does
acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
not
bytes, the master must
byte output, and
must
acknowledge the last
generate a STOP condition.
The output data comes from consecutive addresses, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address coun ter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9
bit time. If the master does n ot pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
START
R/W
AI01105C
th
9/18
M24C64, M24C32
Table 7. DC Characteristics
(T
= 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V)
A
(T
= 0 to 70 °C or –20 to 85 °C; VCC = 1.8 to 3.6 V)
A
Symbol Parameter Test Condition Min. Max. Unit
Input Leakage Current
I
LI
(SCL, SDA)
0V ≤ V
IN
≤ V
CC
± 2 µA
I
I
I
CC1
V
V
V
V
V
Note: 1. This is preliminary data.
Output Leakage Current 0 V ≤ V
LO
Supply Current
CC
Supply Current
(Stand-by)
Input Low Voltage
IL
(E0-E2, SCL, SDA)
Input High Voltage
IH
(E0-E2, SCL, SDA)
Input Low Voltage (WC) – 0.3 0.5 V
IL
Input High Voltage (WC)
IH
Output Low
OL
Voltage
V
=5V, fc=400kHz (rise/fall time < 30ns)
CC
V
-W series:
-R series:
=2.5V, fc=400kHz (rise/fall time < 30ns)
CC
V
=1.8V, fc=100kHz (rise/fall time < 30ns)
CC
-W series: V
-R series: V
-W series: I
-R series:
≤ V
OUT
SDA in Hi-Z ± 2 µA
CC,
2mA
1mA
0.8
V
= VSS or V
IN
= VSS or V
IN
= VSS or V
IN
CC
CC
, V
CC
= 5 V 10 µA
CC
, V
= 2.5 V 2 µA
CC
, V
= 1.8 V
CC
1
– 0.3 0.3 V
CC
CC
VCC+1 V
VCC+1
0.4 V
0.2
0.7V
0.7V
I
= 3 mA, VCC = 5 V
OL
= 2.1 mA, VCC = 2.5 V 0.4 V
OL
I
= 0.7 mA, VCC = 1.8 V
OL
1
mA
1
µA
V
CC
V
1
V
Table 8. Input Parameters1 (TA = 25 °C, f = 400 kHz)
Symbol Parameter Test Condition Min. Max. Unit
C
IN
C
IN
Z
L
Z
H
t
NS
Note: 1. Sampled only, not 100% tested.
10/18
Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
WC Input Impedance VIN < 0.5 V 5 20 kΩ
WC Input Impedance VIN > 0.7V
Low Pass Filter Input Time
Constant (SCL and SDA)
CC
500 kΩ
100 ns
M24C64, M24C32
Table 9. AC Characteristics
M24C64 / M24C32
=1.8 to 3.6 V
V
CC
T
=0 to 70°C or
A
–20 to 85°C
Symbol Alt. Parameter
=4.5 to 5.5 V
V
CC
T
=0 to 70°C or
A
–40 to 85°C
=2.5 to 5.5 V
V
CC
T
=0 to 70°C or
A
–40 to 85°C
Min Max Min Max Min Max
t
t
CH1CH2
t
CL1CL2
2
t
DH1DH2
2
t
DL1DL2
1
t
CHDX
t
CHCL
t
DLCLtHD:STA
t
CLDXtHD:DAT
t
CLCH
t
DXCXtSU:DAT
t
CHDHtSU:STO
t
DHDL
t
CLQV
t
CLQX
t
Note: 1. For a r eS T ART conditio n, or following a w ri te cycle.
t
3
f
C
W
2. Samp l ed only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This i s preliminary dat a.
R
t
F
t
R
t
F
SU:STA
t
HIGH
t
LOW
t
BUF
t
AA
t
DH
f
SCL
t
WR
Clock Rise Time 300 300 1000 ns
Clock Fall Time 300 300 300 ns
SDA Rise Time 20 300 20 300 20 1000 ns
SDA Fall Time 20 300 20 300 20 300 ns
Clock High to Input Transition 600 600 4700 ns
Clock Pulse Width High 600 600 4000 ns
Input Low to Clock Low (START) 600 600 4000 ns
Clock Low to Input Transition 0 0 0 µs
Clock Pulse Width Low 1.3 1.3 4.7 µs
Input Transition to Clock
Transition
100 100 250 ns
Clock High to Input High (STOP) 600 600 4000 ns
Input High to Input Low (Bus
Free)
1.3 1.3 4.7 µs
Clock Low to Data Out Valid 200 900 200 900 200 3500 ns
Data Out Hold Time After Clock
Low
200 200 200 ns
Clock Frequency 400 400 100 kHz
Write Time 10 10 10 ms
Unit
4
Table 10. AC Measurement Conditions
Input Rise and Fall Times ≤ 50 ns
0.2V
0.3V
to 0.8V
CC
to 0.7V
CC
Input Pulse Voltages
Input and Output Timing
Reference Voltages
CC
CC
Figure 9. AC Testing Input Output Waveforms
0.8V
0.2V
CC
CC
0.7V
0.3V
AI00825
CC
CC
11/18
M24C64, M24C32
Figure 10. AC Waveforms
SCL
SDA IN
SCL
SDA OUT
SCL
tCHCL
tDLCL
tCHDX
START
CONDITION
tCLQV tCLQX
tCLDX
SDA
INPUT
DATA VALID
DATA OUTPUT
SDA
CHANGE
tW
tCLCH
tDXCX
tCHDH
tDHDL
STOP &
BUS FREE
SDA IN
tCHDH
STOP
CONDITION
WRITE CYCLE
tCHDX
START
CONDITION
AI00795B
12/18
M24C64, M24C32
Table 11. Ordering Information Scheme
Example: M24C64 –R MN 1 T
Memory Capacity Option
64 64 Kbit (8K x 8) T Tape and Reel Packing
32 32 Kbit (4K x 8)
Operating Voltage
blank 4.5 V to 5.5 V
W 2.5V to 5.5 V
4
1.8 V to 3.6 V
R
Package Temperature Range
2
BN PSDIP8 (0.25 mm frame)
MN SO8 (150 mil width) 6 –40 °C to 85 °C
MW SO8 (200 mil width)
1
TSSOP14 (169 mil width) 5 –20 °C to 85 °C
DL
0 °C to 70 °C
1
3
–40 °C to 125 °C
3
Note: 1. For the availability of the M24C64 and M24C32 in TSSOP14, please contact the ST Sales Office nearest to you.
2. Temperature range available only on request.
3. For conformity to the High Reliability Certified Flow (HRCF), please contact the ST Sales Office nearest to you.
4. The -R version (V
range 1.8 V t o 3. 6 V) only availab l e i n temperature ranges 5 or 1.
CC
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact the ST
Sales Office nearest to you.
13/18
M24C64, M24C32
Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
Symb.
Typ. Min. Max. Typ. Min. Max.
A 3.90 5.90 0.154 0.232
A1 0 .49 – 0.019 –
A2 3 .30 5.30 0.130 0.209
B 0.36 0.56 0.014 0.022
B1 1 .15 1.65 0.045 0.065
C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390
E 7.62 – – 0. 300 – –
E1 6 .00 6.70 0.236 0.264
e1 2.54 – – 0. 100 – –
eA 7 .80 – 0.307 –
eB 10.00 0.394
L 3.00 3.80 0.118 0.150
N8 8
mm inches
Figure 11. PSDIP8 (BN)
Note: 1. Drawing is not to sc al e.
A2
A1AL
B
N
1
e1
B1
D
E1 E
eA
eB
C
PSDIP-a
14/18
Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.35 1 .75 0.053 0.069
A1 0 .10 0.25 0.004 0.010
B 0.33 0 .51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4 .00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N8 8
CP 0.10 0.004
M24C64, M24C32
Figure 12. SO8 narrow (MN)
B
SO-a
Note: 1. Drawing is not to sc al e.
h x 45˚
A
e
D
N
1
CP
E
H
C
LA1 α
15/18
M24C64, M24C32
Table 14. SO8 - 8 lead Plastic Small Outline, 200 mils body width
Symb.
Typ. Min. Max. Typ. Min. Max.
A 2.03 0.080
A1 0 .10 0.25 0.004 0.010
A2 1.78 0.070
B 0.35 0 .45 0.014 0.018
C 0.20 – – 0.008 – –
D 5.15 5.35 0.203 0.211
E 5.20 5 .40 0.205 0.213
e 1.27 – – 0.050 – –
H 7.70 8.10 0.303 0.319
L 0.50 0.80 0.020 0.031
α 0° 10° 0° 10°
N8 8
CP 0.10 0.004
mm inches
Figure 13. SO8 wide (MW)
B
Note: 1. Drawing is not to sc al e.
N
1
SO-b
A2
e
D
CP
E
H
A
C
LA1 α
16/18
Table 15. TSSOP14 - 14 lead Thin Shrink Small Outline
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.10 0.043
A1 0 .05 0.15 0.002 0.006
A2 0 .85 0.95 0.033 0.037
B 0.19 0 .30 0.007 0.012
C 0.09 0.20 0.004 0.008
D 4.90 5.10 0.193 0.197
E 6.25 6 .50 0.246 0.256
E1 4 .30 4.50 0.169 0.177
e 0.65 – – 0.026 – –
L 0.50 0.70 0.020 0.028
α 0° 8° 0° 8°
N14 14
CP 0.08 0.003
M24C64, M24C32
Figure 14. TSSOP14 (DL)
CP
Note: 1. Drawing is not to sc al e.
D
A1
DIE
C
α
L
TSSOP
N
EE1
1
N/2
A2A
eB
17/18
M24C64, M24C32
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18/18
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