ST MICROELECTRONICS ST 24C256 MN6 Datasheet

Features

SO8 (MW)

208 mils width

TSSOP8 (DW)

SO8 (MN)

150 mils width

WLCSP (CS)

UFDFPN8 (MB)

2 × 3 mm (MLP)

■ 256 Kbit EEPROM addressed through the I

bus

■ Supports the I

– 1 MHz Fast-mode Plus
– 400 kHz Fast mode
– 100 kHz Standard mode

■ Supply voltage ranges:

– 1.7 V to 5.5 V
– 1.8 V to 5.5 V
– 2.5 V to 5.5 V

■ Write Control input

■ Byte and Page Write

■ Random and sequential read modes

■ Self-timed programming cycle

■ Automatic address incrementing

■ Enhanced ESD/latch-up protection

■ More than 1 000 000 write cycles

■ More than 40-year data retention

■ Packages

–ECOPACK

2

C bus modes:

®

(RoHS compliant)

M24256-BF M24256-BR

M24256-BW M24256-DR

256 Kbit serial I²C bus EEPROM

with three Chip Enable lines

2

C

January 2010 Doc ID 6757 Rev 20 1/42

www.st.com

1

Contents M24256-BF, M24256-BR, M24256-BW, M24256-DR

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Write Control (WC

2.5 V

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SS

2.6 Supply voltage (V

2.6.1 Operating supply voltage V

2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.5 Addressing the memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.8 Page Write (memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.9 Identification Page Write (M24256-DR only) . . . . . . . . . . . . . . . . . . . . . . 17

3.10 Lock Identification Page (M24256-DR only) . . . . . . . . . . . . . . . . . . . . . . . 17

3.11 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17

3.12 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19

3.13 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.14 Random Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 20

3.15 Current Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 21

3.16 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.17 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Contents

3.18 Read Identification Page status (locked/unlocked) . . . . . . . . . . . . . . . . . . 22

3.19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Doc ID 6757 Rev 20 3/42

List of tables M24256-BF, M24256-BR, M24256-BW, M24256-DR

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Device select code (for memory array). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Device select code to access the Identification page (M24256-DR only). . . . . . . . . . . . . . 11

Table 4. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 8. Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 9. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 10. Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 13. DC characteristics (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14. DC characteristics (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15. DC characteristics (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 16. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 18. SO8W – 8-lead plastic small outline, 208 mils body width, package data . . . . . . . . . . . . . 31

Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 32

Table 20. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 33

Table 21. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 22. WLCSP 0.5 mm pitch, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 23. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 24. Available M24256-BR, M24256-BW, M24256-BF products (package,

voltage range, temperature grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 25. Available M24256-DR products (package, voltage range, temperature grade) . . . . . . . . . 37

Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7

Figure 4. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. I

Figure 6. I

Figure 7. I
Figure 8. Write mode sequences with WC
Figure 9. Write mode sequences with WC

Figure 10. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 14. SO8W – 8-lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . 31

Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 32

Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 17. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

Figure 18. WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2

C Fast mode (fC = 400 kHz): maximum R

bus parasitic capacitance (C

2

C Fast mode Plus (fC = 1 MHz): maximum R

bus parasitic capacitance (C

2

C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

bus

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

bus

value versus

bus

value versus

bus

= 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15

= 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 18

2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Doc ID 6757 Rev 20 5/42

Description M24256-BF, M24256-BR, M24256-BW, M24256-DR

!)G

3$!

6

##

-XXX

7#

3#,

6

33

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%%

1 Description

The M24256-Bx devices are I2C-compatible electrically erasable programmable memories

(EEPROM). They are organized as 32 Kb × 8 bits.

The M24256-Bx and M24256-DR can decode the type identifier code (1010) in accordance

with the I

2

C bus definition. The M24256-DR also decodes the type identifier code (1011)

when accessing the identification page.

The device behaves as a slave in the I

2

C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW

) (as described in Ta bl e 2 ), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9

th

bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Figure 1. Logic diagram

Table 1. Signal names

Signal name Function Direction

E0, E1, E2 Chip Enable Inputs

SDA Serial Data I/O

SCL Serial Clock Input

WC

V

CC

V

SS

Write Control Input

Supply voltage

Ground

6/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Description

V

CC

E1

SDA

SCL

V

SS

WC

E0

E2

ai14712

Figure 2. Package connections

E0 V

1
2

E2

SS

1. See Package mechanical data section for package dimensions, and how to identify pin-1.

3
4

8
7
6
5

CC

WCE1
SCL
SDAV

AI04035e

Figure 3. WLCSP connections (top view, marking side, with balls on the underside)

Doc ID 6757 Rev 20 7/42

Signal description M24256-BF, M24256-BR, M24256-BW, M24256-DR

Ai12806

V

CC

M24xxx

V

SS

E

i

V

CC

M24xxx

V

SS

E

i

2 Signal description

2.1 Serial Clock (SCL)

This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to V
most applications, though, this method of synchronization is not employed, and so the pull­up resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.

2.2 Serial Data (SDA)

This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to V
the value of the pull-up resistor can be calculated).

. (Figure 6 indicates how the value of the pull-up resistor can be calculated). In

CC

. (Figure 6 indicates how

CC

2.3 Chip Enable (E0, E1, E2)

These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to V
or V

, to establish the device select code. When not connected (left floating), these inputs

SS

are read as Low (0,0,0).

Figure 4. Device select code

2.4 Write Control (WC)

This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC
Write operations are allowed.

) is driven High. When unconnected, the signal is internally read as VIL, and

CC

When Write Control (WC

) is driven High, device select and address bytes are

acknowledged, Data bytes are not acknowledged.

8/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Signal description

2.5 VSS ground

VSS is the reference for the VCC supply voltage.

2.6 Supply voltage (VCC)

2.6.1 Operating supply voltage V

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V

(min), VCC(max)] range must be applied (see Tab l e 8 , Tab le 9 and

CC

Ta bl e 1 0 ). In order to secure a stable DC supply voltage, it is recommended to decouple the

V

line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the

CC

V

CC/VSS

package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t

2.6.2 Power-up conditions

VCC has to rise continuously from 0 V up to VCC(min) (see Ta bl e 8 , Ta bl e 9 and Tab le 1 0 ),
and the rise time must not vary faster than 1 V/µs.

2.6.3 Device reset

In order to prevent inadvertent write operations during power-up, a power on reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
reaches an internal reset threshold voltage. This threshold is lower than the minimum V
operating voltage defined in Ta bl e 8 , Ta bl e 9 and Ta bl e 1 0.

When V
Power mode. However, the device must not be accessed until V
stable V

In a similar way, during power-down (continuous decrease in V
below the power on reset threshold voltage, the device stops responding to any instruction
sent to it.

passes over the POR threshold, the device is reset and enters the Standby

CC

voltage within the specified [VCC(min), VCC(max)] range.

CC

CC

).

W

reaches a valid and

CC

), as soon as VCC drops

CC

CC

CC

2.6.4 Power-down conditions

During power-down (where V
Power mode (mode reached after decoding a Stop condition, assuming that there is no
internal Write cycle in progress).

decreases continuously), the device must be in the Standby

CC

Doc ID 6757 Rev 20 9/42

Signal description M24256-BF, M24256-BR, M24256-BW, M24256-DR

1

10

100

10 100 1000

Bus line capacitor (pF)

Bus line pull-up resistor

(k

)

When t

LOW

= 1.3 µs (min value for

f

C

= 400 kHz), the R

bus

× C

bus

time constant m ust be below the
400 ns time constant line
represented on the left.

1

10

100

10 100

Bus line capacitor (pF)

Bus line pull-up resistor (k )

ai14795d

I²C bus
master

M24xxx

R

bus

V

CC

C

bus

SCL

SDA

R

bus

× C

bus

= 270 ns

When t

LOW

= 700 ns
(max possible value for
f

C

= 1 MHz), the R

bus

× C

bus

time constant must be below
the 270 ns time constant line
represented on the left.

When t

LOW

= 400 ns
(min value for f

C

= 1 MHz),

the R

bus

× C

bus

time constant
must be below the 100 ns
time constant line represented
on the left.

Here,

R

bus

× C

bus

= 150 ns

R

bus

× C

bus

= 100 ns

5

30

Figure 5. I2C Fast mode (fC = 400 kHz): maximum R

4 kΩ

Figure 6. I

bus parasitic capacitance (C

R

bus

× C

bus

Here R

× C

= 120 ns

bus

bus

30 pF

2

C Fast mode Plus (fC = 1 MHz): maximum R

= 400 ns

bus parasitic capacitance (C

bus

bus

)

)

value versus

bus

value versus

bus

I²C bus
master

SCL

SDA

V

CC

R

bus

M24xxx

C

bus

ai14796b

10/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Signal description

SCL

SDA

SCL

SDA

SDA

Start

condition

SDA

Input

SDA

Change

AI00792c

Stop

condition

1 23 7 89

MSB

ACK

Start

condition

SCL

1 23 7 89

MSB ACK

Stop

condition

Figure 7. I2C bus protocol

Table 2. Device select code (for memory array)

Device type identifier

b7 b6 b5 b4 b3 b2 b1 b0

Device select code 1010E2E1E0RW

1. The most significant bit, b7, is sent first.

2. E0, E1 and E2 are compared against the respective external pins on the memory device.

Table 3. Device select code to access the Identification page (M24256-DR only)

Device type identifier

b7 b6 b5 b4 b3 b2 b1 b0

Device select code 1011E2E1E0RW

1. The most significant bit, b7, is sent first.

2. E0, E1 and E2 are compared against the respective external pins on the memory device.

Doc ID 6757 Rev 20 11/42

(1)

(1)

Chip Enable address

Chip Enable address

(2)

(2)

RW

RW

Signal description M24256-BF, M24256-BR, M24256-BW, M24256-DR

Table 4. Most significant address byte

b15 b14 b13 b12 b11 b10 b9 b8

Table 5. Least significant address byte

b7 b6 b5 b4 b3 b2 b1 b0

12/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Device operation

3 Device operation

The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always slave in all
communications.

3.1 Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.

3.2 Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode. A Stop condition at the end of a Write
instruction triggers the internal Write cycle.

3.3 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9
acknowledge the receipt of the eight data bits.

th

clock pulse period, the receiver pulls Serial Data (SDA) Low to

3.4 Data input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.

Doc ID 6757 Rev 20 13/42

Device operation M24256-BF, M24256-BR, M24256-BW, M24256-DR

3.5 Addressing the memory array

To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Ta bl e 2 (on Serial Data (SDA), most significant bit first).

The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.

Up to eight memory devices can be connected on a single I
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.

th

The 8

bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

2

C bus. Each one is given a

If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9

th

bit time. If the device does not match

the device select code, it deselects itself from the bus, and goes into Standby mode.

Table 6. Operating modes

Mode RW bit WC

Current Address
Read

Random Address
Read

Sequential Read 1 X  1

Byte Write 0 V

Page Write 0 V

1. X = VIH or VIL.

1 X 1 Start, device select, RW

0X

1 X re-Start, device select, RW

(1)

IL

IL

Bytes Initial sequence

= 1

Start, device select, RW = 0, Address

1

= 1

Similar to Current or Random Address
Read

1 Start, device select, RW = 0

 64 Start, device select, RW = 0

14/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Device operation

Stop

Start

Byte Write Dev sel Byte addr Byte addr Data in

WC

Start

Page Write Dev sel Byte addr Byte addr Data in 1

WC

Data in 2

AI01120d

Page Write
(cont'd)

WC (cont'd)

Stop

Data in N

ACK ACK ACK NO ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK NO ACK

Figure 8. Write mode sequences with WC = 1 (data write inhibited)

Doc ID 6757 Rev 20 15/42

Device operation M24256-BF, M24256-BR, M24256-BW, M24256-DR

3.6 Write operations

Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data byte.

) reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two

Writing to the memory may be inhibited if Write Control (WC
instruction with Write Control (WC
condition until the end of the two address bytes) will not modify the memory contents, and
the accompanying data bytes are not acknowledged, as shown in Figure 8.

Each data byte in the memory has a 16-bit (two byte wide) address. The most significant
byte (Ta bl e 4 ) is sent first, followed by the least significant byte (Tab le 5 ). Bits b15 to b0 form
the address of the byte in memory.

When the bus master generates a Stop condition immediately after the Ack bit (in the “10
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.

After the Stop condition, the delay t
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.

During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.

3.7 Byte Write

After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 9.

) is driven High. Any Write

) driven High (during a period of time from the Start

, and the successful completion of a Write operation,

W

) being driven High, the

th

3.8 Page Write (memory array)

The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided
that they are all located in the same ‘row’ in the memory: that is, the most significant
memory address bits (b15-b6) are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.

The bus master sends from 1 to 64 bytes of data, each of which is acknowledged by the
device if Write Control (WC
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (the 7 least significant
address bits only) is incremented. The transfer is terminated by the bus master generating a
Stop condition.

16/42 Doc ID 6757 Rev 20

) is Low. If Write Control (WC) is High, the contents of the

M24256-BF, M24256-BR, M24256-BW, M24256-DR Device operation

3.9 Identification Page Write (M24256-DR only)

The Identification page is written by issuing an ID Write instruction. This instruction uses the
same protocol and format as the Page Write in memory array, except for the following
differences:

● Device Type Identifier = 1011b

● MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’.

LSB address bits A5/A0 define the byte address inside the identification page.

If the Identification page is locked, the data bytes transferred during the Identification Page
Write instruction are not acknowledged (NoAck).

3.10 Lock Identification Page (M24256-DR only)

The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:

● Device Type Identifier = 1011b

● Address bit A10 must be ‘1’; all other address bits are don't care

● The data byte must be equal to the binary value xxxx xx1x, where x is don't care.

If the Identification Page is locked, the data bytes transferred during the ID Write instruction
are not acknowledged (NoAck).

3.11 ECC (error correction code) and write cycling

The M24256-Bx and M24256-DRdevices offer an ECC (error correction code) logic which
compares each 4-byte word with its six associated ECC EEPROM bits. As a result, if a
single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC
detects it and replaces it by the correct value. The read reliability is therefore much improved
by the use of this feature.

Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes
making up the word. It is therefore recommended to write by word (4 bytes) in order to
benefit from the larger amount of Write cycles.

The M24256-Bx and M24256-DR devices are qualified at 1 million (1 000 000) Write cycles,
using a cycling routine that writes to the device by multiples of 4-bytes.

Doc ID 6757 Rev 20 17/42

Device operation M24256-BF, M24256-BR, M24256-BW, M24256-DR

Stop

Start

Byte Write Dev sel Byte addr

Byte addr Data in

WC

Start

Page Write Dev sel Byte addr Byte addr Data in 1

WC

Data in 2

AI01106d

Page Write
(cont'd)

WC (cont'd)

Stop

Data in N

ACK

R/W

ACK ACK ACK

ACK ACK ACK ACK

R/W

ACKACK

Figure 9. Write mode sequences with WC = 0 (data write enabled)

18/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Device operation

Write cycle

in progress

AI01847d

Next

operation is

addressing the

memory

Start condition

Device select

with RW = 0

ACK

Returned

YES

NO

YESNO

ReStart

Stop

Data for the

Write operation

Device select

with RW = 1

Send Address

and Receive ACK

First byte of instruction
with RW = 0 already
decoded by the device

YESNO

Start

condition

Continue the

Write operation

Continue the

Random Read operation

Figure 10. Write cycle polling flowchart using ACK

3.12 Minimizing system delays by polling on ACK

During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
shown in Ta bl e 1 6 , but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.

The sequence, as shown in Figure 10, is:

● Initial condition: a Write cycle is in progress.

● Step 1: the bus master issues a Start condition followed by a device select code (the

● Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and

first byte of the new instruction).

the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second

w

) is

part of the instruction (the first byte of this instruction having been sent during Step 1).

Doc ID 6757 Rev 20 19/42

Device operation M24256-BF, M24256-BR, M24256-BW, M24256-DR

Start

Dev sel * Byte addr Byte addr

Start

Dev sel Data out 1

AI01105d

Data out N

Stop

Start

Current
Address
Read

Dev sel Data out

Random
Address
Read

Stop

Start

Dev sel * Data out

Sequential
Current
Read

Stop

Data out N

Start

Dev sel * Byte addr Byte addr

Sequential
Random
Read

Start

Dev sel * Data out 1

Stop

ACK

R/W

NO ACK

ACK

R/W

ACK ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

3.13 Read operations

Read operations are performed independently of the state of the Write Control (WC) signal.

After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.

Figure 11. Read mode sequences

3.14 Random Address Read (in memory array)

A dummy Write is first performed to load the address into this address counter (as shown in

Figure 11) but without sending a Stop condition. Then, the bus master sends another Start

condition, and repeats the device select code, with the Read/Write
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.

bit (RW) set to 1. The

20/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Device operation

3.15 Current Address Read (in memory array)

For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in

Figure 11, without acknowledging the byte.

bit (RW) set to 1. The device acknowledges

3.16 Sequential Read

This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 11.

The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.

3.17 Read Identification Page

This instruction uses the same protocol and format as the Random Address Read (in

memory array) instruction. The only differences between the two instructions are that, in the

Read Identification Page instruction:

● the device type identifier = 1011b

● MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’.

LSB address bits A5/A0 define the byte address inside the identification page. During a
Read Identification Page instruction, the (A5/A0) address should not exceed 3Fh.

Doc ID 6757 Rev 20 21/42

Device operation M24256-BF, M24256-BR, M24256-BW, M24256-DR

3.18 Read Identification Page status (locked/unlocked)

The locked/unlocked status of the Identification page can be checked by issuing a specific
truncated instruction consisting of the Identification Page Write instruction followed by one
data byte. The data byte will be acknowledged if the Identification page is unlocked, while it
will not be acknowledged if the Identification page is locked.

Once the acknowledge bit of this data byte is read, it is recommended to generate a Start
condition followed by a Stop condition, so that:

● The instruction is truncated and not executed as the Start condition resets the device

internal logic.

● The device is set to Standby mode by the Stop condition.

3.19 Acknowledge in Read mode

For all Read instructions, the device waits, after each byte read, for an acknowledgment
during the 9
time, the device terminates the data transfer and switches to its Standby mode.

th

bit time. If the bus master does not drive Serial Data (SDA) Low during this

22/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Initial delivery state

4 Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

5 Maximum rating

Stressing the device outside the ratings listed in Ta bl e 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Table 7. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

T

T

STG

T

LEAD

V

IO

V

CC

I

OL

V

ESD

1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on the restriction of the use of certain hazardous
substances in electrical and electronic equipment (RoHS) 2002/95/EC.

2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 pF, R1 = 1500 , R2 = 500 )

Ambient operating temperature –40 130 °C

A

Storage temperature –65 150 °C

Lead temperature during soldering See note

(1)

Input or output range –0.50 6.5 V

Supply voltage –0.50 6.5 V

DC output current (SDA = 0) 5 mA

Electrostatic discharge voltage (human body model)

(2)

–3000 3000 V

°C

Doc ID 6757 Rev 20 23/42

DC and AC parameters M24256-BF, M24256-BR, M24256-BW, M24256-DR

AI00825B

0.8V

CC

0.2V

CC

0.7V

CC

0.3V

CC

Input and Output

Timing Reference Levels

Input Levels

6 DC and AC parameters

This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.

Table 8. Operating conditions (voltage range W)

Symbol Parameter Min. Max. Unit

V

CC

Supply voltage 2.5 5.5 V

Ambient operating temperature (device grade 6) –40 85 °C

T

A

Ambient operating temperature (device grade 3) –40 125 °C

Table 9. Operating conditions (voltage range R)

Symbol Parameter Min. Max. Unit

V

CC

T

Table 10. Operating conditions (voltage range F)

Supply voltage 1.8 5.5 V

Ambient operating temperature –40 85 °C

A

Symbol Parameter Min. Max. Unit

V

CC

T

Table 11. AC test measurement conditions

Supply voltage 1.7 5.5 V

Ambient operating temperature –40 85 °C

A

Symbol Parameter Min. Max. Unit

C

Load capacitance 100 pF

L

Input rise and fall times 50 ns

Input levels 0.2V

Input and output timing reference levels 0.3V

to 0.8V

CC

to 0.7V

CC

CC

CC

V

V

Figure 12. AC test measurement I/O waveform

24/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR DC and AC parameters

Table 12. Input parameters

Symbol Parameter

(1)

Test condition Min. Max. Unit

C

C

Z

Z

H

1. Sampled only, not 100% tested.

2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition).

Table 13. DC characteristics (voltage range W)

Symbol Parameter

I

LI

I

LO

I

CC

I

CC0

I

CC1

V

V

IH

V

OL

1. Characterized value, not tested in production.

2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).

Input capacitance (SDA) 8 pF

IN

Input capacitance (other pins) 6 pF

IN

Input impedance

(2)

L

(E2, E1, E0, WC

Input impedance

(2)

(E2, E1, E0, WC)

Input leakage current
(SCL, SDA, E0, E1,
E2)

Output leakage
current

)

Test conditions (see Table 8 and

V

= VSS or V

IN

device in Standby mode

SDA in Hi-Z, external voltage applied
on SDA: VSS or V

V

= 2.5 V, fc = 400 kHz

CC

< 0.3V

V

IN

V

> 0.7V

IN

Table 11)

CC

CC

CC

CC

30 k

500 k

Min. Max. Unit

(rise/fall time < 50 ns)

Supply current (Read)

= 5.5 V, fc = 400 kHz

V

CC

(rise/fall time < 50 ns)

Supply current (Write) During tW, 2.5 V < VCC < 5.5 V 5

(2)

,

Device grade 3 5

CC

Device grade 6 2

= 5.5 V 5 µA

CC

–0.45 0.3V

0.7V

CC

0.7V

CCVCC

Standby supply
current

Input low voltage

IL

(SCL, SDA, WC

Input high voltage
(SCL, SDA)

Input high voltage
(W

C, E0, E1, E2)

Device not selected
V

= VSS or VCC, V

IN

= 2.5 V

= VSS or VCC, V

V

IN

)

Output low voltage IOL = 2.1 mA, VCC = 2.5 V 0.4 V

± 2 µA

± 2 µA

1mA

2mA

(1)

CC

6.5

+0.6

mA

µA

V

V

Doc ID 6757 Rev 20 25/42

DC and AC parameters M24256-BF, M24256-BR, M24256-BW, M24256-DR

Table 14. DC characteristics (voltage range R)

Symbol Parameter

Input leakage current

I

LI

(E1, E2, SCL, SDA)

I

I

I

CC0

I

CC1

V

Output leakage current

LO

Supply current (Read)

CC

Supply current (Write) During tW, 1.8 V < VCC < 5.5 V 5

Standby supply current

Input low voltage

IL

(SCL, SDA, WC)

Input high voltage
(SCL, SDA)

V

IH

Input high voltage

, E0, E1, E2)

(WC

V

1. Only for devices operating at fC max = 1 MHz (see Ta bl e 1 7 ).

2. Characterized value, not tested in production.

3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).

Output low voltage

OL

Test conditions (in addition to

those in Tabl e 9 )

= VSS or V

V

IN

CC

Min. Max. Unit

device in Standby mode

SDA in Hi-Z, external voltage

applied on SDA: V

= 1.8 V, fc= 400 kHz

V

CC

SS

or V

CC

(rise/fall time < 50 ns)

= 2.5 V, fc= 400 kHz

V

CC

(rise/fall time < 50 ns)

= 5.0 V, fc= 400 kHz

V

CC

(rise/fall time < 50 ns)

1.8 V < V

< 5.5 V, fc= 1 MHz

CC

(1)

(rise/fall time < 50 ns)

Device not selected

V

= VSS or VCC, VCC = 1.8 V

IN

Device not selected

V

= VSS or VCC, VCC = 2.5 V

IN

Device not selected
= VSS or VCC, VCC = 5.5 V

V

IN

1.8 V  V

2.5 V  V

1.8 V  V

2.5 V  V

1.8 V  V

2.5 V  V

I

= 1 mA, VCC = 1.8 V 0.2 V

OL

= 2.1 mA, VCC = 2.5 V 0.4 V

I

OL

I

= 3.0 mA, VCC = 5.5 V 0.4 V

OL

CC

CC

CC

CC

CC

CC

(3)

,

(3)

,

(3)

,

< 2.5 V –0.45 0.25 V

 5.5 V –0.45 0.3 V

< 2.5 V 0.75V

< 5.5 V 0.7V

< 2.5 V 0.75V

 5.5 V 0.7V

CC

CC

CCVCC

CCVCC

± 2 µA

± 2 µA

0.8 mA

1mA

2mA

2.5 mA

(2)

1µA

2µA

3µA

CC

CC

6.5

6.5

+0.6

+0.6

mA

V

V

V

26/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR DC and AC parameters

Table 15. DC characteristics (voltage range F)

Symbol Parameter

Input leakage current

I

LI

(E1, E2, SCL, SDA)

I

Output leakage current

LO

Test condition (in addition to

those in Tabl e 9 )

V

IN

device in Standby mode

SDA in Hi-Z, external voltage

applied on SDA: V

V

= 1.7 V, fc= 400 kHz

CC

(rise/fall time < 50 ns)

= 2.5 V, fc= 400 kHz

V

I

Supply current (Read)

CC

CC

(rise/fall time < 50 ns)

= 5.0 V, fc= 400 kHz

V

CC

(rise/fall time < 50 ns)

I

CC0

Supply current (Write) During tW, 1.7 V < VCC < 5.5 V 5

Device not selected

= VSS or VCC, VCC = 1.7 V

V

IN

I

CC1

Standby supply current

Device not selected

V

= VSS or VCC, VCC = 2.5 V

IN

Device not selected

V

= VSS or VCC, VCC = 5.5 V

IN

V

Input low voltage

IL

(SCL, SDA, WC

)

Input high voltage
(SCL, SDA)

V

IH

Input high voltage

, E0, E1, E2)

(WC

V

1. Preliminary data.

2. Characterized value, not tested in production.

3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).

Output low voltage

OL

1.7 V  VCC < 2.5 V –0.45 0.25 V

2.5 V  V

1.7 V  V

2.5 V  V

1.7 V  V

2.5 V  V

= 1 mA, VCC = 1.7 V 0.2 V

I

OL

I

= 2.1 mA, VCC = 2.5 V 0.4 V

OL

= 3.0 mA, VCC = 5.5 V 0.4 V

I

OL

(1)

= VSS or V

CC

or V

SS

CC

(3)

,

(3)

,

(3)

,

 5.5 V –0.45 0.3 V

CC

< 2.5 V 0.75V

CC

 5.5 V 0.7V

CC

< 2.5 V 0.75V

CC

 5.5 V 0.7V

CC

Min. Max. Unit

± 2 µA

± 2 µA

0.8 mA

1mA

2mA

(2)

1µA

2µA

3µA

CC

CC

CC

CC

CCVCC

CCVCC

6.5

6.5

+0.6

+0.6

mA

V

V

V

Doc ID 6757 Rev 20 27/42

DC and AC parameters M24256-BF, M24256-BR, M24256-BW, M24256-DR

Table 16. 400 kHz AC characteristics

Test conditions specified in Table 8, Ta b l e 9 , Ta b l e 1 0 and Ta b l e 1 1

Symbol Alt. Parameter Min.

(1)

Max.

(1)

Unit

f

C

t

CHCL

t

CLCH

t

QL1QL2

t

XH1XH2

t

XL1XL2

t

DXCX

t

CLDX

t

CLQX

(6)(7)

t

CLQV

t

CHDL

t

DLCL

t

CHDH

t

DHDL

t

W

t

NS

1. All values are referred to VIL(max) and VIH(min).

2. Characterized only, not tested in production.

3. With CL = 10 pF.

4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f

< 400 kHz.

C

5. The new M24xxx-W, M24xxx-R, and M24xxx-BF devices (identified by the process letter K) offer
t

CLQX

t

CLQX

specification which recommends t

6. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.

7. t

CLQV

0.7VCC, assuming that R

8. The current M24xxx devices (identified by the Process letter A) offer tNS=100 ns (min), the new M24256­BR and M24256-DR device (identified by the process letter K) offer t
safe margin compared to the 50 ns minimum value recommended by the I

f

t

HIGH

t

LOW

(2)

t

SU:DAT

t

HD:DAT

t

t

SU:STA

t

HD:STA

t

SU:STO

t

t

= 100 ns (min) and t
= 200 ns (min) and t

is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or

Clock frequency 400 kHz

SCL

Clock pulse width high 600 ns

Clock pulse width low 1300 ns

t

SDA (out) fall time 20

F

t

Input signal rise time

R

t

Input signal fall time

F

(3)

(4)

(4) (4)

Data in set up time 100 ns

Data in hold time 0 ns

Data out hold time 100

DH

t

Clock low to next data valid (access time) 100

AA

(5)

(5)

Start condition setup time 600 ns

Start condition hold time 600 ns

Stop condition set up time 600 ns

Time between Stop condition and next Start

BUF

condition

Write time 5 ms

WR

1300 ns

Pulse width ignored (input filter on SCL and
SDA) - single glitch

= 100 ns (min), while the current devices (process letter A) offer

CLQV

= 200 ns (min). Both series offer a safe margin compared to the I2C

CLQV

bus

× C

= 0 ns (min).

CLQV

time constant is within the values specified in Figure 6.

bus

=80 ns (min). Both products offer a

NS

2

C specification.

120 ns

(4)

900 ns

(8)

80

ns

ns

ns

ns

28/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR DC and AC parameters

Table 17. 1 MHz AC characteristics

(1)

Test conditions specified in Tab l e 9 and Ta b l e 1 1

Symbol Alt. Parameter Min.

f

C

t

CHCL

t

CLCH

t

XH1XH2

t

XL1XL2

t

QL1QL2

t

DXCX

t

CLDX

t

CLQX

(7)(8)

t

CLQV

t

CHDL

t

DLCL

t

CHDH

t

DHDL

t

W

(4)

t

NS

1. Only new M24256-BR and M24256-DR devices identified by the process letter K are qualified at 1 MHz.

2. All values are referred to VIL(max) and VIH(min).

3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC< 400 kHz, or less than 120 ns when fC<1MHz.

4. Characterized only, not tested in production.

5. With CL = 10 pF.

6. The new M24xxx devices (identified by the process letter K) offer t
(min) which is an improved value compared to the t
current M24xxx devices (identified with the Process letter A)

7. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.

8. t

CLQV

0.7V

9. The new M24xxx devices (identified with the process letter K) offer tNS = 80 ns (min) which is an improved
value compared to the current M24xxx devices (identified by the process letter A).

(4)

f

SCL

t

HIGH

t

LOW

t

R

t

F

t

F

t

SU:DAT

t

HD:DAT

t

SU:STA

t

HD:STA

t

SU:STO

t

BUF

t

WR

Clock frequency 0 1 MHz

Clock pulse width high 300 - ns

Clock pulse width low 400 - ns

Input signal rise time

Input signal fall time

SDA (out) fall time 20

Data in setup time 80 - ns

Data in hold time 0 - ns

t

Data out hold time 50

DH

t

Clock low to next data valid (access time) 50

AA

Start condition setup time 250 - ns

Start condition hold time 250 - ns

Stop condition setup time 250 - ns

Time between Stop condition and next
Start condition

Write time - 5 ms

Pulse width ignored (input filter on SCL and
SDA)

=100 ns (min) and t

=50 ns (min) and t

CLQX

is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or

, assuming that the R

CC

bus

× C

time constant is within the values specified in Figure 6.

bus

CLQX

(2)

(3)

(3) (3)

(5)

(6)

(6)

500 - ns

-50

=50 ns (min) offered by the

CLQV

(2)

Max.

(3)

Unit

ns

ns

120 ns

-ns

500 ns

(9)

CLQV

ns

=100 ns

Doc ID 6757 Rev 20 29/42

DC and AC parameters M24256-BF, M24256-BR, M24256-BW, M24256-DR

SCL

SDA In

SCL

SDA Out

SCL

SDA In

tCHCL

tDLCL

tCHDL

Start

condition

tCLCH

tDXCHtCLDX

SDA

Input

SDA

Change

tCHDH tDHDL

Stop

condition

Data valid

tCLQV tCLQX

tCHDH

Stop

condition

tCHDL

Start

condition

Write cycle

tW

AI00795e

Start

condition

tCHCL

tXH1XH2

tXH1XH2

tXL1XL2

tXL1XL2

Data valid

tQL1QL2

Figure 13. AC waveforms

30/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Package mechanical data

6L_ME

E

N

CP

b

e

A2

D

c

LA1 k

E1

A

1

7 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

Figure 14. SO8W – 8-lead plastic small outline, 208 mils body width, package outline

1. Drawing is not to scale.

Table 18. SO8W – 8-lead plastic small outline, 208 mils body width, package data

millimeters inches

Symbol

Typ Min Max Typ Min Max

(1)

A 2.5 0.0984

A1 0 0.25 0 0.0098

A2 1.51 2 0.0594 0.0787

b 0.4 0.35 0.51 0.0157 0.0138 0.0201

c 0.2 0.1 0.35 0.0079 0.0039 0.0138

CP 0.1 0.0039

D 6.05 0.2382

E 5.02 6.22 0.1976 0.2449

E1 7.62 8.89 0.3 0.35

e 1.27 - - 0.05 - -

k 0° 10° 0° 10°

L 0.5 0.8 0.0197 0.0315

N (number of pins) 8 8

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 6757 Rev 20 31/42

Package mechanical data M24256-BF, M24256-BR, M24256-BW, M24256-DR

SO-A

E1

8

ccc

b

e

A

D

c

1

E

h x 45˚

A2

k

0.25 mm

L

L1

A1

GAUGE PLANE

Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline

1. Drawing is not to scale.

Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package

mechanical data

millimeters inches

Symbol

Typ Min Max Typ Min Max

(1)

A 1.75 0.0689

A1 0.1 0.25 0.0039 0.0098

A2 1.25 0.0492

b 0.28 0.48 0.011 0.0189

c 0.17 0.23 0.0067 0.0091

ccc 0.1 0.0039

D 4.9 4.8 5 0.1929 0.189 0.1969

E 6 5.8 6.2 0.2362 0.2283 0.2441

E1 3.9 3.8 4 0.1535 0.1496 0.1575

e 1.27 - - 0.05 - -

h 0.25 0.5 0.0098 0.0197

k 0°8° 0°8°

L 0.4 1.27 0.0157 0.05

L1 1.04 0.0409

1. Values in inches are converted from mm and rounded to 4 decimal digits.

32/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Package mechanical data

TSSOP8AM

1

8

CP

c

L

EE1

D

A2A

α

eb

4

5

A1

L1

Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline

1. Drawing is not to scale.

Table 20. TSSOP8 – 8-lead thin shrink small outline, package mechanical data

millimeters inches

Symbol

Typ Min Max Typ Min Max

(1)

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 1.000 0.800 1.050 0.0394 0.0315 0.0413

b 0.190 0.300 0.0075 0.0118

c 0.090 0.200 0.0035 0.0079

CP 0.100 0.0039

D 3.000 2.900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

E 6.400 6.200 6.600 0.2520 0.2441 0.2598

E1 4.400 4.300 4.500 0.1732 0.1693 0.1772

L 0.600 0.450 0.750 0.0236 0.0177 0.0295

L1 1.000 0.0394

 0° 8° 0° 8°

N8 8

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 6757 Rev 20 33/42

Package mechanical data M24256-BF, M24256-BR, M24256-BW, M24256-DR

Figure 17. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

2 x 3 mm, outline

e

D

b

L3

E

A

D2

A1

1. Drawing is not to scale.

2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to V
allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering
process.

3. The circle in the top view of the package indicates the position of pin 1.

Table 21. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

ddd

L1

E2

L

UFDFPN-01

. It must not be

SS

2 x 3 mm, data

millimeters inches

Symbol

Typ Min Max Typ Min Max

(1)

A 0.55 0.45 0.6 0.0217 0.0177 0.0236

A1 0.02 0 0.05 0.0008 0 0.002

b 0.25 0.2 0.3 0.0098 0.0079 0.0118

D 2 1.9 2.1 0.0787 0.0748 0.0827

D2 1.6 1.5 1.7 0.063 0.0591 0.0669

E 3 2.9 3.1 0.1181 0.1142 0.122

E2 0.2 0.1 0.3 0.0079 0.0039 0.0118

e 0.5 - - 0.0197 - -

L 0.45 0.4 0.5 0.0177 0.0157 0.0197

L1 0.15 0.0059

L3 0.3 0.0118

(2)

ddd

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.

0.08 0.08

34/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Package mechanical data

D

E

e2

G

321

B

e

A

B

C

D

E

F

e3

e1

Orientation reference

A1

A

A2

Figure 18. WLCSP, 0.5 mm pitch, package outline

1. Drawing is not to scale.

Table 22. WLCSP 0.5 mm pitch, package mechanical data

Millimeters Inches

(1)

(2)

Symbol

Typ Min Max Typ Min Max

A 0.60 0.55 0.65 0.0236 0.0217 0.0256

A1 0.245 0.22 0.27 0.0096 0.0087 0.0106

A2 0.355 0.330 0.380 0.0140 0.0130 0.0150

B Ø 0.311 Ø 0.0122

D 1.97 1.95 1.99 0.0776 0.0768 0.0783

E 1.785 1.765 1.805 0.0703 0.0695 0.0711

e 0.5 0.0197

e1 0.866 0.0341

e2 0.25 0.0098

e3 0.433 0.0170

F 0.552 0.502 0.602 0.0217 0.0198 0.0237

G 0.392 0.342 0.442 0.0154 0.0135 0.0174

(3)

N

1. Preliminary data.

2. Values in inches are converted from mm and rounded to 4 decimal digits.

3. N is the total number of terminals.

8 8

Doc ID 6757 Rev 20 35/42

Part numbering M24256-BF, M24256-BR, M24256-BW, M24256-DR

8 Part numbering

Table 23. Ordering information scheme

Example: M24256–B W MW 6 T P /AB

Device type

2

M24 = I

C serial access EEPROM

Device function

256– = 256 Kbit (32 Kb × 8)

Device family

B: Without Identification page
D: With additional Identification page

Operating voltage

W = V

= 2.5 to 5.5 V

CC

R = VCC = 1.8 to 5.5 V
F = V

= 1.7 to 5.5 V

CC

Package

MW = SO8 (208 mils width)
MN = SO8 (150 mils body width)
DW = TSSOP8
MB = UFDFPN8 (MLP8)
CS = WLCSP

Device grade

6 = Industrial temperature range, –40 to 85 °C. Device tested with standard test flow
3 = Automotive: device tested with high reliability certified flow

(1)

over –40 to 125 °C

Option

blank = standard packing
T = tape and reel packing

Plating technology

P or G = ECOPACK

Process

(2)

®

(RoHS compliant)

/A = F8L process (CSP package)
/AB = F8L process (for device grade 3)
/K = F8H process

1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High
Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a
copy.

2. Used only for device grade 3 and WLCSP packages.

36/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Part numbering

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.

Table 24. Available M24256-BR, M24256-BW, M24256-BF products (package,

voltage range, temperature grade)

Package

M24256-BW

2.5 V to 5.5 V

M24256-BR

1.8 V to 5.5 V

M24256-BF

1.7 V to 5.5 V

SO8N (MN) Range 6, Range 3 Range 6 -

SO8W (MW) Range 6 - -

TSSOP (DW) Range 6 Range 6 Range 6

WLCSP (CS) - Range 6 -

UFDFPN8 (MB) - - Range 6

Table 25. Available M24256-DR products (package, voltage range, temperature

grade)

Package

SO8N (MN) Range 6

TSSOP (DW) Range 6

M24256-DR

1.8 V to 5.5 V

Doc ID 6757 Rev 20 37/42

Revision history M24256-BF, M24256-BR, M24256-BW, M24256-DR

9 Revision history

Table 26. Document revision history

Date Revision Changes

Lead Soldering Temperature in the Absolute Maximum Ratings table
amended

29-Jan-2001 1.1

10-Apr-2001 1.2

16-Jul-2001 1.3 LGA8 Package given the designator “LA”

02-Oct-2001 1.4 LGA8 Package mechanical data updated

13-Dec-2001 1.5

12-Jun-2001 1.6 Document promoted to Full Datasheet

22-Oct-2003 2.0

02-Sep-2004 3.0

22-Feb-2005 4.0

Write Cycle Polling Flow Chart using ACK illustration updated
LGA8 and SO8(wide) packages added
References to PSDIP8 changed to PDIP8, and Package Mechanical data

updated

LGA8 Package Mechanical data and illustration updated
SO16 package removed

Document becomes Preliminary Data
Test conditions for ILI, ILO, ZL and ZH made more precise
VIL and VIH values unified. tNS value changed

Table of contents, and Pb-free options added. Minor wording changes in
Summary Description, Power-On Reset, Memory Addressing, Write
Operations, Read Operations. V

(min) improved to –0.45V.

IL

LGA8 package is Not for New Design. 5V and -S supply ranges, and
Device Grade 5 removed. Absolute Maximum Ratings for V

(min) and

IO

VCC(min) changed. Soldering temperature information clarified for RoHS
compliant devices. Device grade information clarified. AEC-Q100-002
compliance. V

specification unified for SDA, SCL and WC

IL

Initial delivery state is FFh (not necessarily the same as Erased).

LGA package removed, TSSOP8 and SO8N packages added (see

Package mechanical data section and Table 23: Ordering information
scheme).

Voltage range R (1.8V to 5.5V) also offered. Minor wording changes.

Test Conditions modified in Table 12: Input parameters and Note 2

Z

L

added.
I

CC

and I

values for VCC = 5.5V added to Table 13: DC characteristics

CC1

(voltage range W).

Note added to Table 13: DC characteristics (voltage range W).

Power On Reset paragraph specified.

max value modified in Table 16: 400 kHz AC characteristics and note 4

t

W

added. Plating technology changed in Table 23: Ordering information

scheme.

Resistance and capacitance renamed in Figure 6.

38/42 Doc ID 6757 Rev 20

M24256-BF, M24256-BR, M24256-BW, M24256-DR Revision history

Table 26. Document revision history (continued)

Date Revision Changes

Power On Reset paragraph replaced by Section 2.6: Supply voltage

). Figure 4: Device select code added.

(V

CC

ECC (error correction code) and write cycling added and specified at 1

05-May-2006 5

16-Oct-2006 6

02-Jul-2007 7

16-Oct-2007 8

Million cycles.

added and I

I

CC0

specified over the whole voltage range in Ta b le 1 3

CC1

and Ta bl e 1 4 .
PDIP8 package removed. Packages are ECOPACK® compliant. Small

text changes.

M24256-BW and M24256-BR part numbers added.

Section 3.11: ECC (error correction code) and write cycling updated.

I

CC

and I

modified in Table 14: DC characteristics (voltage range R).

CC1

tW modified in Table 16: 400 kHz AC characteristics.
SO8Narrow package specifications updated (see Ta b l e 1 9 and

Figure 15). Blank option removed from below Plating technology in
Table 23: Ordering information scheme.

Section 2.6: Supply voltage (VCC) modified.
Section 3.11: ECC (error correction code) and write cycling modified.

JEDEC standard and European directive references corrected below

Table 7: Absolute maximum ratings.

Rise/fall time conditions modified for I

and VIH max modified in

CC

Table 13: DC characteristics (voltage range W) and Table 14: DC
characteristics (voltage range R)

Note 1 removed from Table 13: DC characteristics (voltage range W).
SO8W package specifications modified in Section 7: Package mechanical

data.
Table 24: Available M24256-BR, M24256-BW, M24256-BF products

(package, voltage range, temperature grade) and Table 26: Available
M24512-x products (package, voltage range, temperature grade) added.

Section 2.5: V

max changed and Note 1 updated to latest standard revision in

V

IO

ground added. Small text changes.

SS

Table 7: Absolute maximum ratings.

Note removed from Table 12: Input parameters.

min and VIL max modified in Table 14: DC characteristics (voltage

V

IH

range R).

Removed t

CH1CH2

, t

CL1CL2

and t

DH1DH2

, and added t

XL1XL2

, t

DL1DL2

and

Note 3 in Table 16: 400 kHz AC characteristics.

t

XH1XH2

, t

and Note 2 added to Table 17: 1 MHz AC characteristics.

XL1XL2

Figure 13: AC waveforms modified.

Package mechanical data inch values calculated from mm and rounded to
4 decimal digits (see Section 7: Package mechanical data).

Doc ID 6757 Rev 20 39/42

Revision history M24256-BF, M24256-BR, M24256-BW, M24256-DR

Table 26. Document revision history (continued)

Date Revision Changes

1 MHz frequency introduced (M24512-HR root part number).

14-Dec-2007 9

27-Mar-2008 10

22-Apr-2008 11

Section 2.6.3: Device reset modified.
Figure 5: I

parasitic capacitance (C
1 MHz): maximum R

added.
t

NS

Ta bl e 1 3 .
Table 14: DC characteristics (voltage range R) and Table 17: 1 MHz AC

characteristics modified. Small text changes.

Small text changes. M24256-BHR root part number added.

Section 2.6.3: Device reset on page 9 updated.
Figure 6: I

bus parasitic capacitance (C

Caution removed in Section 3.11: ECC (error correction code) and write

cycling.

M24512-W and M24256-BW offered in the device grade 3 option
(automotive temperature range):

– Table 8: Operating conditions (voltage range W),
– Table 13: DC characteristics (voltage range W),
– /AB Process letters added to Table 23: Ordering information scheme,
– Table 24: Available M24256-BR, M24256-BW, M24256-BF products

(package, voltage range, temperature grade) and

– Table 26: Available M24512-x products (package, voltage range,

temperature grade) updated accordingly).

Small text changes.

2

C Fast mode (fC = 400 kHz): maximum R

) modified, Figure 6: I2C Fast mode Plus (fC =

bus

value versus bus parasitic capacitance (C

bus

value versus bus

bus

bus

moved from Ta bl e 1 2 to Ta bl e 1 6 . ILO test conditions modified in

2

C Fast mode Plus (fC = 1 MHz): maximum R

) on page 10 updated.

bus

value versus

bus

)

WLCSP package added (see Figure 3: WLCSP connections (top view,

22-Dec-2008 12

marking side, with balls on the underside) and Section 7: Package
mechanical data).

M24256-BF part number added (V
added, see Ta bl e 1 0 , Tab l e 1 5 , Tab le 1 6 and Ta bl e 2 4 ).

21-Jan-2009 13

test conditions modified in Table 13: DC characteristics (voltage

I

CC1

range W), Table 14: DC characteristics (voltage range R) and Ta bl e 1 5:
DC characteristics (voltage range F).

M24512-DR part number and Identification page feature added.
Command replaced by instruction in the whole document.
UFDFPN8 added.

Figure 6 updated.
Section 2.6.2: Power-up conditions and Section 2.6.3: Device reset

05-Jun-2009 14

updated.

and t

t

CLQX

and t

t

CLQX

updated in Ta bl e 1 6 , Note 5 and Note 8 added.

CLQV

updated in Ta b le 1 7 , Note 6 and Note 9 added.

CLQV

Section 8: Part numbering updated.

Reference to the SURE program removed in Section 5: Maximum rating.
Previous 1 MHz M24512-HR and M24512-BHR devices replaced by new

M24512-R and M24256-BR (process letter K).

40/42 Doc ID 6757 Rev 20

= 1.7 V to 5.5 V voltage range

CC

M24256-BF, M24256-BR, M24256-BW, M24256-DR Revision history

Table 26. Document revision history (continued)

Date Revision Changes

16-Jun-2009 15 Part numbers updated in cover page header.

added to Table 8: Operating conditions (voltage range W).

I

20-Aug-2009 16

13-Oct-2009 17

05-Nov-2009 18

OL

Note 1and ICC modified in Table 13: DC characteristics (voltage range W);
Note and I

modified in Table 14: DC characteristics (voltage range R);

CC

Datasheet split to leave only devices with 256 Kbit capacity.
M24256-DR part number added (see Table 25: Available M24256-DR

products (package, voltage range, temperature grade).

2

Figure 4: Device select code and Figure 5: I
maximum R

max modified in Table 7: Absolute maximum ratings.

V

IO

value versus bus parasitic capacitance (C

bus

C Fast mode (fC = 400 kHz):

) updated.

bus

VIH modified in Table 13: DC characteristics (voltage range W), Ta b le 1 4:

DC characteristics (voltage range R) and Table 15: DC characteristics
(voltage range F).

In Table16: 400kHz AC characteristics and Table 17: 1 MHz AC

characteristics:

DL1DL2

changed to t

CHDX

XH1XH2

changed to t

and t

XL1XL2

QL1QL2

CHDL

values removed

–t
–t
–t
– Notes modified

Figure 13: AC waveforms modified.

Section 3.9: Identification Page Write (M24256-DR only)

corrected.Section 3.17: Read Identification Page clarified.

UFDFPN8 package is now offered (see Section 7: Package mechanical

10-Dec-2009 19

data, Table 23: Ordering information scheme and Table 24: Available
M24256-BR, M24256-BW, M24256-BF products (package, voltage
range, temperature grade).

19-Jan-2010 20 Revision number corrected at bottom of pages.

Doc ID 6757 Rev 20 41/42

M24256-BF, M24256-BR, M24256-BW, M24256-DR

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Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

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