Features
SO8 (MW)
208 mils width
TSSOP8 (DW)
SO8 (MN)
150 mils width
WLCSP (CS)
UFDFPN8 (MB)
2 × 3 mm (MLP)
■ 256 Kbit EEPROM addressed through the I
bus
■ Supports the I
– 1 MHz Fast-mode Plus
– 400 kHz Fast mode
– 100 kHz Standard mode
■ Supply voltage ranges:
– 1.7 V to 5.5 V
– 1.8 V to 5.5 V
– 2.5 V to 5.5 V
■ Write Control input
■ Byte and Page Write
■ Random and sequential read modes
■ Self-timed programming cycle
■ Automatic address incrementing
■ Enhanced ESD/latch-up protection
■ More than 1 000 000 write cycles
■ More than 40-year data retention
■ Packages
–ECOPACK
2
C bus modes:
®
(RoHS compliant)
M24256-BF M24256-BR
M24256-BW M24256-DR
256 Kbit serial I²C bus EEPROM
with three Chip Enable lines
2
C
January 2010 Doc ID 6757 Rev 20 1/42
www.st.com
1
Contents M24256-BF, M24256-BR, M24256-BW, M24256-DR
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Write Control (WC
2.5 V
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
2.6 Supply voltage (V
2.6.1 Operating supply voltage V
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 Addressing the memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8 Page Write (memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9 Identification Page Write (M24256-DR only) . . . . . . . . . . . . . . . . . . . . . . 17
3.10 Lock Identification Page (M24256-DR only) . . . . . . . . . . . . . . . . . . . . . . . 17
3.11 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17
3.12 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14 Random Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 20
3.15 Current Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 21
3.16 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.17 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/42 Doc ID 6757 Rev 20
M24256-BF, M24256-BR, M24256-BW, M24256-DR Contents
3.18 Read Identification Page status (locked/unlocked) . . . . . . . . . . . . . . . . . . 22
3.19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Doc ID 6757 Rev 20 3/42
List of tables M24256-BF, M24256-BR, M24256-BW, M24256-DR
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device select code (for memory array). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Device select code to access the Identification page (M24256-DR only). . . . . . . . . . . . . . 11
Table 4. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. DC characteristics (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. DC characteristics (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. DC characteristics (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18. SO8W – 8-lead plastic small outline, 208 mils body width, package data . . . . . . . . . . . . . 31
Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 32
Table 20. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 33
Table 21. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 22. WLCSP 0.5 mm pitch, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 23. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 24. Available M24256-BR, M24256-BW, M24256-BF products (package,
voltage range, temperature grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 25. Available M24256-DR products (package, voltage range, temperature grade) . . . . . . . . . 37
Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4/42 Doc ID 6757 Rev 20
M24256-BF, M24256-BR, M24256-BW, M24256-DR List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7
Figure 4. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. I
Figure 6. I
Figure 7. I
Figure 8. Write mode sequences with WC
Figure 9. Write mode sequences with WC
Figure 10. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 14. SO8W – 8-lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . 31
Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 32
Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
Figure 18. WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2
C Fast mode (fC = 400 kHz): maximum R
bus parasitic capacitance (C
2
C Fast mode Plus (fC = 1 MHz): maximum R
bus parasitic capacitance (C
2
C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
bus
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
bus
value versus
bus
value versus
bus
= 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15
= 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 6757 Rev 20 5/42
Description M24256-BF, M24256-BR, M24256-BW, M24256-DR
!)G
3$!
6
##
-XXX
7#
3#,
6
33
%%
1 Description
The M24256-Bx devices are I2C-compatible electrically erasable programmable memories
(EEPROM). They are organized as 32 Kb × 8 bits.
The M24256-Bx and M24256-DR can decode the type identifier code (1010) in accordance
with the I
2
C bus definition. The M24256-DR also decodes the type identifier code (1011)
when accessing the identification page.
The device behaves as a slave in the I
2
C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW
) (as described in Ta bl e 2 ), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9
th
bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Figure 1. Logic diagram
Table 1. Signal names
Signal name Function Direction
E0, E1, E2 Chip Enable Inputs
SDA Serial Data I/O
SCL Serial Clock Input
WC
V
CC
V
SS
Write Control Input
Supply voltage
Ground
6/42 Doc ID 6757 Rev 20
M24256-BF, M24256-BR, M24256-BW, M24256-DR Description
V
CC
E1
SDA
SCL
V
SS
WC
E0
E2
ai14712
Figure 2. Package connections
E0 V
1
2
E2
SS
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
3
4
8
7
6
5
CC
WCE1
SCL
SDAV
AI04035e
Figure 3. WLCSP connections (top view, marking side, with balls on the underside)
Doc ID 6757 Rev 20 7/42
Signal description M24256-BF, M24256-BR, M24256-BW, M24256-DR
Ai12806
V
CC
M24xxx
V
SS
E
i
V
CC
M24xxx
V
SS
E
i
2 Signal description
2.1 Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to V
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2 Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to V
the value of the pull-up resistor can be calculated).
. (Figure 6 indicates how the value of the pull-up resistor can be calculated). In
CC
. (Figure 6 indicates how
CC
2.3 Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to V
or V
, to establish the device select code. When not connected (left floating), these inputs
SS
are read as Low (0,0,0).
Figure 4. Device select code
2.4 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC
Write operations are allowed.
) is driven High. When unconnected, the signal is internally read as VIL, and
CC
When Write Control (WC
) is driven High, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
8/42 Doc ID 6757 Rev 20
M24256-BF, M24256-BR, M24256-BW, M24256-DR Signal description
2.5 VSS ground
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (VCC)
2.6.1 Operating supply voltage V
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V
(min), VCC(max)] range must be applied (see Tab l e 8 , Tab le 9 and
CC
Ta bl e 1 0 ). In order to secure a stable DC supply voltage, it is recommended to decouple the
V
line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the
CC
V
CC/VSS
package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t
2.6.2 Power-up conditions
VCC has to rise continuously from 0 V up to VCC(min) (see Ta bl e 8 , Ta bl e 9 and Tab le 1 0 ),
and the rise time must not vary faster than 1 V/µs.
2.6.3 Device reset
In order to prevent inadvertent write operations during power-up, a power on reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
reaches an internal reset threshold voltage. This threshold is lower than the minimum V
operating voltage defined in Ta bl e 8 , Ta bl e 9 and Ta bl e 1 0.
When V
Power mode. However, the device must not be accessed until V
stable V
In a similar way, during power-down (continuous decrease in V
below the power on reset threshold voltage, the device stops responding to any instruction
sent to it.
passes over the POR threshold, the device is reset and enters the Standby
CC
voltage within the specified [VCC(min), VCC(max)] range.
CC
CC
).
W
reaches a valid and
CC
), as soon as VCC drops
CC
CC
CC
2.6.4 Power-down conditions
During power-down (where V
Power mode (mode reached after decoding a Stop condition, assuming that there is no
internal Write cycle in progress).
decreases continuously), the device must be in the Standby
CC
Doc ID 6757 Rev 20 9/42
Signal description M24256-BF, M24256-BR, M24256-BW, M24256-DR
1
10
100
10 100 1000
Bus line capacitor (pF)
Bus line pull-up resistor
(k
)
When t
LOW
= 1.3 µs (min value for
f
C
= 400 kHz), the R
bus
× C
bus
time constant m ust be below the
400 ns time constant line
represented on the left.
1
10
100
10 100
Bus line capacitor (pF)
Bus line pull-up resistor (k )
ai14795d
I²C bus
master
M24xxx
R
bus
V
CC
C
bus
SCL
SDA
R
bus
× C
bus
= 270 ns
When t
LOW
= 700 ns
(max possible value for
f
C
= 1 MHz), the R
bus
× C
bus
time constant must be below
the 270 ns time constant line
represented on the left.
When t
LOW
= 400 ns
(min value for f
C
= 1 MHz),
the R
bus
× C
bus
time constant
must be below the 100 ns
time constant line represented
on the left.
Here,
R
bus
× C
bus
= 150 ns
R
bus
× C
bus
= 100 ns
5
30
Figure 5. I2C Fast mode (fC = 400 kHz): maximum R
4 kΩ
Figure 6. I
bus parasitic capacitance (C
R
bus
× C
bus
Here R
× C
= 120 ns
bus
bus
30 pF
2
C Fast mode Plus (fC = 1 MHz): maximum R
= 400 ns
bus parasitic capacitance (C
bus
bus
)
)
value versus
bus
value versus
bus
I²C bus
master
SCL
SDA
V
CC
R
bus
M24xxx
C
bus
ai14796b
10/42 Doc ID 6757 Rev 20
M24256-BF, M24256-BR, M24256-BW, M24256-DR Signal description
SCL
SDA
SCL
SDA
SDA
Start
condition
SDA
Input
SDA
Change
AI00792c
Stop
condition
1 23 7 89
MSB
ACK
Start
condition
SCL
1 23 7 89
MSB ACK
Stop
condition
Figure 7. I2C bus protocol
Table 2. Device select code (for memory array)
Device type identifier
b7 b6 b5 b4 b3 b2 b1 b0
Device select code 1010E2E1E0RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 3. Device select code to access the Identification page (M24256-DR only)
Device type identifier
b7 b6 b5 b4 b3 b2 b1 b0
Device select code 1011E2E1E0RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Doc ID 6757 Rev 20 11/42
(1)
(1)
Chip Enable address
Chip Enable address
(2)
(2)
RW
RW
Signal description M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 4. Most significant address byte
b15 b14 b13 b12 b11 b10 b9 b8
Table 5. Least significant address byte
b7 b6 b5 b4 b3 b2 b1 b0
12/42 Doc ID 6757 Rev 20
M24256-BF, M24256-BR, M24256-BW, M24256-DR Device operation
3 Device operation
The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always slave in all
communications.
3.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
3.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode. A Stop condition at the end of a Write
instruction triggers the internal Write cycle.
3.3 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9
acknowledge the receipt of the eight data bits.
th
clock pulse period, the receiver pulls Serial Data (SDA) Low to
3.4 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.
Doc ID 6757 Rev 20 13/42
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