Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 3.6V)
• Internally Organized 2048 x 8 (16K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (3.6V, 2.7V, 2.5V), 400 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 16-byte Page (16K) Write Modes
• Partial Page Writes Allowed
• Self-timed Write Cycle (5 ms max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra-Thin Mini-MAP (MLP 2x3), 5-lead SOT23,
8-lead TSSOP and 8-ball dBGA2 Packages
• Lead-free/Halogen-free
• Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
Two-wire
Serial EEPROM
16K (2048 x 8)
Description
The AT24C16B provides 16384 bits of serial electrically erasable and programmable
read-only memory (EEPROM) organized as 2048 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low-power
and low-voltage operation are essential. The AT24C16B is available in space-saving
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3)
SOT23, 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire
serial interface. In addition, the AT24C16B is available in 1.8V (1.8V to 3.6V) version.
Table 1. Pin Configuration
Pin Name Function
A0 - A2 No Connect
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
GND Ground
VCC Power Supply
8-lead Ultra Thin
Mini-MAP (MLP 2x3)
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
A2
GND
8-ball dBGA2
8
VCC
7
WP
6
SCL
5
SDA
Bottom View Bottom View
A0
A1
A2
GND
8-lead SOIC
1
2
3
4
8-lead TSSOP
1
A0
2
A1
3
A2
GND
4
8
VCC
7
WP
6
SCL
5
SDA
, 5-lead
1
A0
2
A1
3
A2
4
GND
8
7
6
5
VCC
WP
SCL
SDA
AT24C16B
Preliminary
SCL
GND
SDA
8-lead PDIP5-lead SOT23
8
1
1
2
3
WP
5
VCC
4
A0
A1
A2
GND
2
3
4
VCC
7
WP
6
SCL
5
SDA
5175B–SEEPR–4/07
1
Absolute Maximum Ratings
Operating Temperature..................................–55°C to +125°C
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground ....................................–1.0V to +5.0V
Maximum Operating Voltage ............................................ 4.3V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
2
AT24C16B [Preliminary]
5175B–SEEPR–4/07
AT24C16B [Preliminary]
Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or opencollector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The AT24C16B does not use the device
address pins, which limits the number of devices on a single bus to one. The A0, A1, A2
are no connects and can be connected to ground.
WRITE PROTECT (WP): The AT24C16B has a write protect pin that provides hardware
data protection. The write protect pin allows normal read/write operations when connected to ground (GND). When the write protect pin is connected to V
protection feature is enabled and operates as shown in Table 2.
Table 2. Write Protect
Part of the Array Protected
WP Pin
Status
At V
CC
At GND Normal Read/Write Operations
Full (16K) Array
24C16B
, the write
CC
Memory Organization AT24C16B, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes
each, the 16K requires an 11-bit data word address for random word addressing.
5175B–SEEPR–4/07
3
Table 3. Pin Capacitance
(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol Test Condition Max Units Conditions
C
I/O
C
IN
Input/Output Capacitance (SDA) 8 pF V
Input Capacitance (SCL) 6 pF VIN = 0V
I/O
= 0V
Note: 1. This parameter is characterized and is not 100% tested.
Table 4. DC Characteristics
Applicable over recommended operating range from: T
Symbol Parameter Test Condition Min Typ Max Units
= −40°C to +85°C, VCC = +1.8V to +3.6V (unless otherwise noted)
AI
V
I
I
I
I
I
V
V
V
V
CC1
CC1
CC2
SB1
LI
LO
IL
IH
OL2
OL1
Supply Voltage 1.8 3.6 V
Supply Current VCC = 3.6V READ at 400 kHz 1.0 2.0 mA
Supply Current VCC = 3.6V WRITE at 400 kHz 2.0 3.0 mA
= 1.8V
V
Standby Current
(1.8V option)
Input Leakage Current VIN = V
Output Leakage
Current
Input Low Level
Input High Level
(1)
(1)
CC
= 3.6V 3.0
V
CC
CC or VSS
= V
V
OUT
CC or VSS
VIN = VCC or V
Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
Notes: 1. VIL min and VIH max are reference only and are not tested.
1.0 µA
SS
0.10 3.0 µA
0.05 3.0 µA
−0.6 VCC x 0.3 V
VCC x 0.7 VCC + 0.5 V
4
AT24C16B [Preliminary]
5175B–SEEPR–4/07
Table 5. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from T
erwise noted). Test conditions are listed in Note 2.
Symbol Parameter
AT24C16B [Preliminary]
= −40°C to +85°C, VCC = +1.8V to +3.6V, CL = 100 pF (unless oth-
AI
1.8-volt 2.5-volt 3.6-volt
UnitsMin Max Min Max Min Max
f
SCL
t
LOW
t
HIGH
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
Clock Frequency, SCL 400 1000 1000 kHz
Clock Pulse Width Low 1.3 0.4 0.4 µs
Clock Pulse Width High 0.6 0.4 0.4 µs
Clock Low to Data Out Valid 0.05 0.9 0.05 0.55 0.05 0.55 µs
Time the bus must be free before a
new transmission can start
(1)
1.3 0.5 0.5 µs
Start Hold Time 0.6 0.25 0.25 µs
Start Set-up Time 0.6 0.25 0.25 µs
Data In Hold Time 0 0 0 µs
Data In Set-up Time 100 100 100 ns
Inputs Rise Time
Inputs Fall Time
(1)
(1)
Stop Set-up Time 0.6 0.25 0.25 µs
Data Out Hold Time 50 50 50 ns
Write Cycle Time 5 5 5 ms
(1)
25°C, Page Mode, 3.3V 1,000,000
Notes: 1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
(connects to VCC): 1.3 kΩ (2.5V, 3.6V), 10 kΩ (1.8V)
R
L
Input pulse voltages: 0.3 VCC to 0.7 V
CC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 V
CC
0.3 0.3 0.3 µs
300 100 100 ns
Write
Cycles
5175B–SEEPR–4/07
5
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on
page 7). Data changes during SCL high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C16B features a low-power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset,
any 2-wire part can be protocol reset by following these steps:
1. Create a start bit condition.
2. Clock 9 cycles.
3. Create another start bit followed by stop bit condition as shown below.
SCL
SDA
Start Bit Start Bit Stop Bit
123 89
Dummy Clock Cycles
6
AT24C16B [Preliminary]
5175B–SEEPR–4/07
Bus Timing
S
S
Figure 2. SCL: Serial Clock, SDA: Serial Data I/O®
Write Cycle Timing
Figure 3. SCL: Serial Clock, SDA: Serial Data I/O
AT24C16B [Preliminary]
CL
DA
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
8th BIT
WORDn
ACK
STOP
CONDITION
(1)
t
wr
START
CONDITION
Figure 4. Data Validity
7
5175B–SEEPR–4/07