ST MICROELECTRONICS ST 24C16 MN6 Datasheet

M24C16, M24C08

PDIP8 (BN)

SO8 (MN)

150 mils width

TSSOP8 (DW)

169 mils width

TSSOP8 (DS)

3 × 3 mm body size (MSOP)

UFDFPN8 (MB)
2 × 3 mm (MLP)

WLCSP (CS)

(1)

Thin WLCSP (CT)

(2)

M24C04, M24C02, M24C01

16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit serial I²C bus EEPROM

Features

■

Supports both the 100 kHz I2C Standard-mode
and the 400 kHz I2C Fast-mode

■

Single supply voltage:
– 2.5 V to 5.5 V for M24Cxx-W
– 1.8 V to 5.5 V for M24Cxx-R
– 1.7 V to 5.5 V for M24Cxx-F

■

Write Control input

■

Byte and Page Write (up to 16 bytes)

■

Random and Sequential Read modes

■

Self-timed programming cycle

■

Automatic address incrementing

■

Enhanced ESD/latch-up protection

■

More than 1 million write cycles

■

More than 40-year data retention

■

Packages
– ECOPACK® (RoHS compliant)

Table 1. Device summary

Reference Part number

M24C16-W

M24C16

M24C16-R
M24C16-F

M24C08-W

M24C08

M24C08-R
M24C08-F

M24C04

M24C04-W

M24C04-R
M24C04-F

M24C02

M24C01

May 2009 Doc ID 5067 Rev 13 1/40

M24C02-W

M24C02-R

M24C01-W

M24C01-R

1. Only M24C08-F and M24C16-F devices are offered in
the WLCSP package.

2. Only M24C08-F devices are offered in the Thin
WLCSP package.

www.st.com

1

Contents M24C16, M24C08, M24C04, M24C02, M24C01

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3.1 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4.1 Operating supply voltage V

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.4.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6.3 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . 16

3.7 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.7.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.7.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7.4 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/40 Doc ID 5067 Rev 13

M24C16, M24C08, M24C04, M24C02, M24C01 Contents

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Doc ID 5067 Rev 13 3/40

List of tables M24C16, M24C08, M24C04, M24C02, M24C01

List of tables

Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Operating conditions (M24Cxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. Operating conditions (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Operating conditions (M24Cxx-F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. DC characteristics (M24Cxx-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. DC characteristics (M24Cxx-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11. DC characteristics (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. DC characteristics (M24Cxx-F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 14. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 15. AC characteristics at 400 kHz (I2C Fast-mode) (M24Cxx-W, M24Cxx-R,

M24Cxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16. AC characteristics at 100 kHz (I2C Standard-mode) (M24Cxx-W,

M24Cxx-R, M24Cxx-F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. M24C08: WLCSP (0.5 mm height) 0.4 mm pitch, 5 bumps, package data . . . . . . . . . . . . 27

Table 18. M24C08: Thin WLCSP (0.3 mm height), 0.4 mm pitch, 5 bumps, package data . . . . . . . . 28

Table 19. M24C16: WLCSP (0.5 mm height) 0.4 mm pitch, 5 bumps, package data . . . . . . . . . . . . 28

Table 20. SO8 narrow – 8 lead plastic small outline, 150 mils body width,

package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 22. TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 31

Table 23. TSSOP8 3 x 3 mm – 8 lead thin shrink small outline, 3 x 3 mm body size,

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 24. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 33

Table 25. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 26. Available M24C16 products (package, voltage range, temperature grade) . . . . . . . . . . . . 35

Table 27. Available M24C08 products (package, voltage range, temperature grade) . . . . . . . . . . . . 35

Table 28. Available M24C04 products (package, voltage range, temperature grade) . . . . . . . . . . . . 35

Table 29. Available M24C02 products (package, voltage range, temperature grade) . . . . . . . . . . . . 35

Table 30. Available M24C01 products (package, voltage range, temperature grade) . . . . . . . . . . . . 36

Table 31. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4/40 Doc ID 5067 Rev 13

M24C16, M24C08, M24C04, M24C02, M24C01 List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. M24C08-F WLCSP and thin WLCSP connections

(top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. Maximum RP value versus bus parasitic capacitance (C) for an I²C bus . . . . . . . . . . . . . 10

Figure 6. I²C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 7. Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 13. WLCSP (0.5 mm) and Thin WLCSP (0.3 mm) 0.4 mm pitch 5 bumps,

package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 29

Figure 15. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 16. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 17. TSSOP8 3 x 3 mm – 8 lead thin shrink small outline, 3 x 3 mm body size,

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 18. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 33

Doc ID 5067 Rev 13 5/40

Description M24C16, M24C08, M24C04, M24C02, M24C01

AI02033

3

E0-E2 SDA

V

CC

M24Cxx

WC

SCL

V

SS

1 Description

These I²C-compatible electrically erasable programmable memory (EEPROM) devices are

organized as 2048/1024/512/256/128 x 8 (M24C16, M24C08, M24C04, M24C02 and

M24C01).

Figure 1. Logic diagram

I²C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The

devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I²C

bus definition.

The device behaves as a slave in the I²C protocol, with all memory operations synchronized

by the serial clock. Read and Write operations are initiated by a Start condition, generated

by the bus master. The Start condition is followed by a device select code and Read/Write

bit (RW) (as described in Table 3), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit

time, following the bus master’s 8-bit transmission. When data is read by the bus master, the

bus master acknowledges the receipt of the data byte in the same way. Data transfers are

terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Table 2. Signal names

Signal name Function Direction

E0, E1, E2 Chip Enable Input
SDA Serial Data Input/output
SCL Serial Clock Input
WC Write Control Input
V

CC

V

SS

Supply voltage
Ground

6/40 Doc ID 5067 Rev 13

M24C16, M24C08, M24C04, M24C02, M24C01 Description

SDAV

SS

SCL

WC

V

CC

/ E2

AI02034E

M24Cxx

1
2
3
4

8
7
6
5

/ E2/ E2/ E2NC

/ E1

/ E1/ E1/ NCNC

/ E0

/ E0/ NC/ NCNC

/1Kb

/2Kb/4Kb/8Kb16Kb

V

CC

WC

SDA

SCL

V

SS

ai14908



Figure 2. 8-pin package connections (top view)

1. NC = Not connected

2. See Section 7: Package mechanical data for package dimensions, and how to identify pin-1.

Figure 3. M24C08-F WLCSP and thin WLCSP connections

(top view, marking side, with balls on the underside)

Doc ID 5067 Rev 13 7/40

Signal description M24C16, M24C08, M24C04, M24C02, M24C01

Ai11650

V

CC

M24Cxx

V

SS

E

i

V

CC

M24Cxx

V

SS

E

i

2 Signal description

2.1 Serial Clock (SCL)

This input signal is used to strobe all data in and out of the device. In applications where this

signal is used by slave devices to synchronize the bus to a slower clock, the bus master

must have an open drain output, and a pull-up resistor can be connected from Serial Clock

(SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). In

most applications, though, this method of synchronization is not employed, and so the pull-

up resistor is not necessary, provided that the bus master has a push-pull (rather than open

drain) output.

2.2 Serial Data (SDA)

This bidirectional signal is used to transfer data in or out of the device. It is an open drain

output that may be wire-ORed with other open drain or open collector signals on the bus. A

pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 5 indicates how

the value of the pull-up resistor can be calculated).

2.3 Chip Enable (E0, E1, E2)

These input signals are used to set the value that is to be looked for on the three least

significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC

or VSS, to establish the device select code as shown in Figure 4. When not connected (left

floating), E0, E1, E2 are read as low (0,0,0).

Figure 4. Device select code

2.3.1 Write Control (WC)

This input signal is useful for protecting the entire contents of the memory from inadvertent

write operations. Write operations are disabled to the entire memory array when Write

Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and

Write operations are allowed.

When Write Control (WC) is driven High, device select and address bytes are

acknowledged, data bytes are not acknowledged.

8/40 Doc ID 5067 Rev 13

M24C16, M24C08, M24C04, M24C02, M24C01 Signal description

2.4 Supply voltage (VCC)

2.4.1 Operating supply voltage V

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Table 6, Table 7 and

Table 8). In order to secure a stable DC supply voltage, it is recommended to decouple the

VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the

VCC/VSS package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal write cycle (tW).

2.4.2 Power-up conditions

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage

defined in Table 6, Table 7 and Table 8 and the rise time must not vary faster than 1 V/µs.

2.4.3 Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)

circuit is included. At power-up (continuous rise of VCC), the device does not respond to any

instruction until VCC reaches the power-on-reset threshold voltage (this threshold is lower

than the minimum VCC operating voltage defined in Table 6, Table 7 and Table 8). When

VCC passes over the POR threshold, the device is reset and enters the Standby Power

mode. The device, however, must not be accessed until VCC reaches a valid and stable VCC

voltage within the specified [VCC(min), VCC(max)] range.

CC

In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops

below the power-on-reset threshold voltage, the device stops responding to any instruction

sent to it.

2.4.4 Power-down conditions

During power-down (continuous decrease in VCC), the device must be in the Standby Power

mode (mode reached after decoding a Stop condition, assuming that there is no internal

write cycle in progress).

Doc ID 5067 Rev 13 9/40

Signal description M24C16, M24C08, M24C04, M24C02, M24C01

1

10

100

10 100 1000

Bus line capacitor (pF)

Bus line pull-up resistor

(k

)

fC = 400 kHz, t

LOW

= 1.3 µs
Rbus x Cbus time
constant must be less than
500 ns

I²C bus
master

M24xxx

R

bus

V

CC

C

bus

SCL

SDA

ai14796



SCL

SDA

SCL

SDA

SDA

Start

condition

SDA

Input

SDA

Change

AI00792c

Stop

condition

1 2 3 7 8 9

MSB

ACK

Start

condition

SCL

1 2 3 7 8 9

MSB ACK

Stop

condition

Figure 5. Maximum RP value versus bus parasitic capacitance (C) for an I²C bus

Figure 6. I²C bus protocol

10/40 Doc ID 5067 Rev 13

M24C16, M24C08, M24C04, M24C02, M24C01 Signal description

Table 3. Device select code

Device type identifier

(1)

Chip Enable

b7 b6 b5 b4 b3 b2 b1 b0

M24C01 select code 1 0 1 0 E2 E1 E0 RW
M24C02 select code 1 0 1 0 E2 E1 E0 RW
M24C04 select code 1 0 1 0 E2 E1 A8 RW
M24C08 select code 1 0 1 0 E2 A9 A8 RW
M24C16 select code 1 0 1 0 A10 A9 A8 RW

1. The most significant bit, b7, is sent first.

2. E0, E1 and E2 are compared against the respective external pins on the memory device.

3. A10, A9 and A8 represent most significant bits of the address.

(2),(3)

RW

Doc ID 5067 Rev 13 11/40

Device operation M24C16, M24C08, M24C04, M24C02, M24C01

3 Device operation

The device supports the I²C protocol. This is summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The M24Cxx device is always a slave in all
communication.

3.1 Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.

3.2 Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal Write cycle.

3.3 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.

3.4 Data input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.

12/40 Doc ID 5067 Rev 13