M24256
M24128
256/128 Kbit Serial I²C Bus EEPROM
Without Chip Enable Lines
■ Compat ible with I
■ Two Wire I
2
C Extended Addressing
2
C Serial Interface
Supports 400 kHz Protocol
■ Single Supply Voltage:
– 4.5V to 5.5V for M24xxx
– 2.5V to 5.5V for M24xxx-W
■ Hardware Write Control
■ BYTE and PAGE WRITE (up to 64 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Tim e d P ro g r amming Cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Behavior
■ More than 100,000 Erase/Write Cycles
■ More than 40 Year Data Retention
DESCRIPTION
These I
2
C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32Kx8 bits (M24256) and 16Kx8 bits
(M24128), and operate down to 2.5 V (for the -W
version of each device).
The M24256B, M2 4128B and M24256A are also
available, and offer the extra functionality of the
chip enable inputs. Please see the separate data
sheets for details of these products.
The M24256 and M 24128 are available in Plastic
Dual-in-Line and Plastic Small Outline packages.
These memory devices are compatible with the
2
C extended memory standard. This is a two wire
I
Table 1. Signal Names
SDA Serial Data/Address Input/
Output
8
PDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
Figure 1. Logic Diagram
V
CC
SCL
M24256
WC
M24128
1
8
1
SO8 (MW)
200 mil width
SDA
SCL Serial Clock
WC
V
CC
V
SS
Write Control
Supply Voltage
Ground
V
SS
AI01882
1/17June 2001
M24256, M24128
Figure 2A. DIP Connections
M24256
M24128
1
NC V
2
3
NC
4
SS
Note: 1. NC = Not Connected
8
7
6
5
AI01883
CC
WCNC
SCL
SDAV
serial interface that uses a bi-directiona l data bus
and serial clock. The memory carries a built-in 4bit unique Device Type Identifier code (1010) in
accordance with the I
The memory behaves as a slave device in the I
2
C bus definition.
2
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, gene rated by the
bus master. The START condition is followed by a
Device Select Code and RW
bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the mem ory in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and after a NoAck for READ.
Figure 2B. SO C on ne ct i on s
M24256
M24128
NC V
1
2
NC
SS
Note: 1. NC = Not Connected
Power On Reset: V
3
4
CC
8
7
6
5
AI01884
CC
WCNC
SCL
SDAV
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is
C
held active until the V
voltage has reached the
CC
POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when V
drops from the
CC
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any com ma nd. A s table a nd v alid V
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow-
CC
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD Electrostatic Discharge Voltage (Human Body model)
Note: 1. Exc ept for the rating “Operating Temperature Range”, stresses above those l i sted in the Table “Absolute Maximum Ratings” may
2/17
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indica te d i n the Operating secti ons of this specification is not im plied. Exposure to Absolute Ma xim um Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. IPC/ JEDEC J-STD- 02 0A
3. JED EC St d JESD22-A11 4A (C1=100 pF, R1=15 00 Ω, R2=500 Ω)
Ambient Operating Temperature –40 to 125 °C
Storage Temperature –65 to 150 °C
Lead Temperature during Soldering
Input or Output range –0.6 to 6.5 V
Supply Voltage –0.3 to 6.5 V
1
PDIP: 10 seconds
SO: 20 seconds (max)
3
2
260
235
4000 V
°C
M24256, M24128
er clock, the master must have an open drain output, and a pull-up resistor must be connected from
the SCL line to V
. (Figure 3 indicates how the
CC
value of the pull-up res istor c an be calculated). In
most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V
. (Figure 3 indicates how the value of the
CC
pull-up resistor can be calculated).
Write Control (WC
The hardware Write Control pin (WC
)
) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC
=VIL) or disable (WC=VIH)
write instructions to the entire memory area. When
unconnected, the WC
V
, and write operations are allowed.
IL
When WC
=1, Device Select and Address bytes
input is internally read as
are acknowledged, Data bytes are not acknowledged.
Please see the Application Note
AN404
for a more
detailed description of the Write Control feature.
DEVICE OPERATION
2
The memory device supports the I
C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001
. Any device that sends data on to the bus
is defined to be a transm itter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is k nown as the master,
and the other as the slave. A data transfer can only
be initiated by the mas ter, which wi ll also provide
the serial clock for synchronization. The memory
device is always a slave device in all comm unication.
Start Condition
START is identified by a high t o low transition of
the SDA line while the clock, SCL, is stable i n the
high state. A START condition must precede any
data transfer comman d. Th e m em ory devi ce continuously monitors (except during a program ming
cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line wh ile th e clock S CL is sta ble in the h igh
state. A STO P condition terminates c ommunication between the memory device and the bus master. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the interna l EEPRO M write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9
th
clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
Figure 3. Maximum R
20
16
12
8
Maximum RP value (kΩ)
4
0
10 1000
Value versus Bus Capacitance (C
L
fc = 100kHz
fc = 400kHz
100
C
(pF)
BUS
) for an I2C Bus
BUS
V
MASTER
CC
SDA
SCL
R
R
C
BUS
L
C
BUS
AI01665
3/17
L
M24256, M24128
2
Figure 4. I
C Bus Protocol
SCL
SDA
SCL
SDA
SCL
SDA
START
Condition
START
Condition
1 23 789
MSB
1 23 789
MSB ACK
SDA
Input
SDA
Change
STOP
Condition
ACK
STOP
Condition
AI00792B
must be stable during the clock low-to-high transition, and the data must change
only
when the SCL
line is low.
Memory Addressing
To start communication betwee n the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code i s fur-
Table 3. Device Select Code
b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code 1 0 1 0 0 0 0 RW
Note: 1. The most significant bit, b7, is sent first.
4/17
1
Device Type Identifier Chip Enable RW
ther su bdi v i de d i n to : a 4 -b i t D ev i ce Ty pe I d en t if i er ,
and a 3-bit Chip Enable “Address” (0, 0, 0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
th
The 8
bit is th e RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Cod e, th e corresponding memory gives an acknowledgment on the SDA bus during the 9
th
bit time. If the memo ry does n ot ma tch
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
Table 4. Operating Modes
Mode RW bit
Current Address Read 1 X 1 START, Device Select, RW
0X
Random Address Read
1 X reSTART, Device Select, RW
Sequential Read 1 X
Byte Write 0
Page Write 0
Note: 1. X = V
IH
or V
.
IL
WC
V
V
1
Data Bytes Initial Sequence
START, Device Select, RW
1
1 Similar to Current or Random Address Read
≥
IL
IL
1 START, Device Select, RW = ‘0’
64 START, Device Select, RW
≤
M24256, M24128
= ‘1’
= ‘0’, Address
= ‘1’
= ‘0’
There are two modes both for read and write.
These are summarized in Table 4 and described
later. A communication between the m aster and
the slave is ended with a STOP condition.
Each data byte in the m emory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 5) is sent first, f ollowed by the Least significant
Byte (Table 6). Bits b15 to b0 form t he add ress of
the byte in memory. Bit b15 is t reated as a Don’t
Care bit on the M24256 memory. Bits b15 and b14
are treated as Don’t Care bits on the M24128
memory.
Figure 5. Wri te Mo de S e qu e nces with WC=1 (data write inhib i ted)
WC
ACK ACK ACK NO ACK
BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN
R/W
START
WC
ACK ACK ACK NO ACK
PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1
STOP
DATA IN 2
WC (cont'd)
PAGE WRITE
(cont'd)
R/W
START
NO ACK NO ACK
DATA IN N
STOP
AI01120C
5/17
M24256, M24128
Figure 6. Wri te Mo de S e qu e nces with WC=0 (data write enab led )
WC
ACK
BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN
R/W
START
WC
ACK ACK ACK ACK
PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1
R/W
START
WC (cont'd)
ACKACK
PAGE WRITE
(cont'd)
DATA IN N
ACK ACK ACK
STOP
DATA IN 2
STOP
Table 5. Most Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8
Note: 1. b15 is tr eated as Don’t Ca re on the M24256 series.
b15 and b14 ar e Don’t Care on the M24128 series.
Table 6. Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
Write Operations
Following a START con dition the ma ster sends a
Device Select Code with the RW
bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for two address bytes. The memory responds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
=1 (during a period of time from the START
WC
AI01106B
condition until the end of the two address bytes)
will not modify the me mory c ontents, and t he ac-
not
companying data bytes will
be acknowledged,
as shown in Figure 5.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed lo cation is write
protected by the WC
pin, the memory replies with
a NoAck, and the location is not modified. If, instead, the WC
pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
Page Write
The Page Write mode allows u p to 64 by tes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory add ress bits
(b14-b6 for the M24256 and b13-b6 for the
M24128) are the same. If more bytes are sent than
6/17
Figure 7. Wri te Cy cle Pol l in g Fl owchart using A CK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
NO
Returned
M24256, M24128
First byte of instruction
with RW = 0 already
decoded by the device
ReSTART
STOP
YES
Next
Operation is
Addressing the
Memory
DATA for the
WRITE Operation
Continue the
WRITE Operation
will fit up to t he en d of t he row, a condition known
as ‘roll-over’ occurs. Data starts to become overwritten (in a way not formally specified in this data
sheet).
The master sends from one up to 64 bytes of data,
each of which is acknow ledged by the memory if
the W C
pin is low. If the WC pin is high, the contents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte i s tran sferred, the i nte rnal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition immediately after the Ack bit (in the “10
th
bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not t rigger the internal write cycle.
YESNO
Send Address
and Receive ACK
START
Condition
YESNO
DEVICE SELECT
with RW = 1
Continue the
Random READ Operation
AI01847C
During the internal write cycle, the SDA input is
disabled internally, and the device does not respond to any requests.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory disconnects itself from the bus, and copies the data from
its internal latches to the memory cells. The maximum writ e time (t
) is shown in Table 10, but the
w
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the m aster issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is bus y with the internal
write cycle, no Ack will be returned and the master goes back to Step 1. If the memory has ter-
7/17
M24256, M24128
Figure 8. Read Mode Sequences
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
ACK
DEV SEL DATA OUT
R/W
START
ACK
DEV SEL * BYTE ADDR BYTE ADDR
R/W
START
ACK ACK ACK NO ACK
DEV SEL DATA OUT 1
R/W
START
ACK ACK ACK
DEV SEL * BYTE ADDR BYTE ADDR
NO ACK
STOP
ACK ACK ACK
DEV SEL * DATA OUT
R/W
START
DATA OUT N
STOP
ACK ACK
DEV SEL * DATA OUT 1
NO ACK
STOP
R/W
START
ACK NO ACK
DATA OUT N
STOP
Note: 1. The seven most signi fi cant bits of the D evice Select Code of a Random Read (in the 1st and 4th bytes) must be i d entica l.
minated the internal write cycle, it responds with
an Ack, indicating that the m emory is ready to
receive the second part of the nex t instruction
(the first byte of this instruction having been sent
during Step 1).
Read Operations
Read operations are performed independently of
the state of the WC
pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then,
without
sending a STOP condition, the mas-
ter sends another START condi tion, and repeats
the Device Select Code, with the RW bit set to ‘1’.
The memory acknowledge s this, and outputs the
contents of the addressed byte. The master m ust
not
acknowledge the by te output, and terminates
the transfer with a STOP condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read m ode, following a START
condition, the master sends a Device Select Code
with the RW
edges this, and outputs the byte addressed by the
internal address counter. The counter is then in-
START
bit set to ‘1’. The memory acknowl-
R/W
AI01105C
8/17
M24256, M24128
Table 7. DC Characteristics
(T
= –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V)
A
Symbol Parameter Test Condition Min. Max. Unit
Input Leakage Current
I
LI
(SCL, SDA)
0V ≤ V
IN
≤ V
CC
± 2 µA
I
I
I
CC1
V
V
V
V
V
Output Leakage Current 0 V ≤ V
LO
Supply Current
CC
Supply Current
(Stand-by)
Input Low Voltage
IL
(SCL, SDA)
Input High Voltage
IH
(SCL, SDA)
Input Low Voltage (WC) –0.3 0.5 V
IL
Input High Voltage (WC) 0.7V
IH
Output Low
OL
Voltage
Table 8. Input Parameters
V
=5V, fc=400kHz (rise/fall time < 30ns)
CC
V
-W series:
-W series: V
-W series:
1
(TA = 25 °C, f = 400 kHz)
=2.5V, fc=400kHz (rise/fall time < 30ns)
CC
V
IN
IN
I
OL
≤ V
OUT
= VSS or V
= VSS or V
I
= 3 mA, VCC = 5 V
OL
SDA in Hi-Z ± 2 µA
CC,
, V
CC
CC
, V
CC
= 2.5 V 2 µA
CC
= 2.1 mA, VCC = 2.5 V
= 5 V
–0.3
0.7V
CC
CC
Symbol Parameter Test Condition Min. Max. Unit
C
IN
C
IN
Z
L
Z
H
t
NS
Note: 1. Sampled only, not 100% tested.
Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
V
Input Impedance (WC)
Input Impedance (WC)V
Low Pass Filter Input Time
Constant (SCL and SDA)
≤ 0.5 V
IN
≥ 0.7V
IN
CC
5k
500 k
100 ns
2mA
1mA
10 µA
0.3V
VCC+1
CC
V
V
VCC+1 V
0.4 V
0.4 V
Ω
Ω
Table 9. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing
Reference Voltages
0.2V
0.3V
≤
CC
CC
50 ns
to 0.8V
to 0.7V
CC
CC
Figure 9. AC Testing Input Output Waveforms
0.8V
0.2V
CC
CC
0.7V
0.3V
AI00825
CC
CC
9/17
M24256, M24128
Table 10. AC Characteristics
Symbol Alt. Parameter
M24256 / M24128
V
=4.5 to 5.5 V
CC
T
=–40 to 85°C
A
=2.5 to 5.5 V
V
CC
T
=–40 to 85°C
A
MinMaxMinMax
Unit
t
CH1CH2
t
CL1CL2
t
DH1DH2
t
DL1DL2
1
t
CHDX
t
CHCL
t
DLCL
t
CLDX
t
CLCH
t
DXCX
t
CHDH
t
DHDL
3
t
CLQV
t
CLQX
f
C
t
W
Note: 1. For a r eS T ART conditio n, or following a w ri te cycle.
2. Samp l ed only, not 100 % t ested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
t
Clock Rise Time 300 300 ns
R
t
Clock Fall Time 300 300 ns
F
2
t
SDA Rise Time 20 300 20 300 ns
R
2
t
SDA Fall Time 20 300 20 300 ns
F
t
SU:STA
t
t
HD:STA
t
HD:DAT
t
t
SU:DAT
t
SU:STO
t
f
Clock High to Input Transition 600 600 ns
Clock Pulse Width High 600 600 ns
HIGH
Input Low to Clock Low (START) 600 600 ns
Clock Low to Input Transition 0 0 µs
Clock Pulse Width Low 1.3 1.3 µs
LOW
Input Transition to Clock Transition 100 100 ns
Clock High to Input High (STOP) 600 600 ns
Input High to Input Low (Bus Free) 1.3 1.3 µs
BUF
t
Clock Low to Data Out Valid 200 900 200 900 ns
AA
t
Data Out Hold Time After Clock Low 200 200 ns
DH
Clock Frequency 400 400 kHz
SCL
t
Write Time 10 10 ms
WR
cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8,
out
acknowledging the byte output.
with-
Sequenti a l Rea d
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
does
master
acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
not
bytes, the master must
byte output, and
must
acknowledge the last
generate a STOP condition.
The output data comes from consecutive addresses, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address coun ter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
10/17
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9
bit time. If the master does n ot pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
th
Figure 10. AC Waveforms
M24256, M24128
SCL
SDA In
SCL
SDA In
SCL
tCHCL
tDLCL
tCHDX
START
Condition
tCHDH
STOP
Condition
tCLQV tCLQX
SDA
Input
tCLCH
SDA
Change
tW
Write Cycle
tDXCXtCLDX
tCHDH tDHDL
tCHDX
START
Condition
STOP
Condition
START
Condition
SDA Out
Data Valid
AI00795C
11/17
M24256, M24128
Table 11. Ordering Information Scheme
Example: M24256 – W MN 1 T
Memory Capacity Option
256 256 Kbit (32K x 8) T Tape and Reel Packing
128 Kbit (16K x 8)
128
Temperature Range
6 –40 °C to 85 °C
5 –20 °C to 85 °C
Operating Voltage
1
4.5 V to 5.5 V Package
blank
W 2.5 V to 5.5 V BN PDIP8 (0.25 mm frame)
2
SO8 (150 mil width)
MN
3
SO8 (200 mil width)
MW
Note: 1. Available only on request.
2. Avail able for M24128 only.
3. Avail able for M24256 only.
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all 1s (FFh).
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
12/17
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame
M24256, M24128
b2
A2
A1AL
be
D
8
E1
1
Note: 1. Drawing is not to scale.
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 5.33 0.210
A1 0.38 0.015
E
c
eA
eB
PDIP-8
A2 3.30 2.92 4 .95 0.130 0.115 0.195
b 0.46 0.36 0.56 0. 018 0.014 0.022
b2 1 .52 1.14 1.78 0. 060 0.045 0.070
c 0.25 0.20 0 .36 0.010 0.008 0.014
D 9.27 9.02 10.16 0.365 0.355 0.400
E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7 .11 0.250 0.240 0.280
e 2.54 – – 0.100 – –
eA 7.62 – – 0.300 – –
eB 10.92 0.430
L 3.30 2.92 3.81 0. 130 0.115 0.150
13/17
M24256, M24128
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
h x 45˚
A
B
e
D
N
1
SO-a
Note: Drawing is not to scale.
CP
E
H
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
mm inches
C
LA1 α
14/17
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.0 10
D 4.80 5.00 0.189 0.1 97
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.2 44
h 0.25 0.50 0.010 0.0 20
L 0.40 0.90 0.016 0.0 35
α
0° 8° 0° 8°
N8 8
CP 0.10 0.004
SO8 wide – 8 lead Plastic Small Outline, 200 mils body width
M24256, M24128
A
Note: Drawing is not to scale.
A2
B
e
D
N
1
SO-b
CP
E
H
SO8 wide – 8 lead Plastic Small Outline, 200 mils body width
Symb.
Typ. Min. Max. Typ. Min. Max.
A 2.03 0.080
A1 0.10 0.25 0.004 0.010
mm inches
C
LA1 α
A2 1.78 0.070
B 0.35 0.45 0.014 0.018
C 0.20 – – 0.008 – –
D 5.15 5.35 0.203 0.211
E 5.20 5.40 0.205 0.213
e 1.27 – – 0.050 – –
H 7.70 8.10 0.303 0.319
L 0.50 0.80 0.020 0.031
α
0° 10° 0° 10°
N8 8
CP 0.10 0.004
15/17
M24256, M24128
Table 12. Revision History
Date Rev. Description of Revision
References added to the M24256B and M24128B products
30-Mar-2001 2.2
01-Jun-2001 2.3 Document promoted from “Preliminary Data” to “Full Data Sheet”
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP8 changed to PDIP8, and Package Mechanical data updated
16/17
M24256, M24128
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17/17
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