ST MICROELECTRONICS ST 24C128 MN6 Datasheet

M24256 M24128
256/128 Kbit Serial I²C Bus EEPROM
Without Chip Enable Lines
Compat ible with I
Two Wire I
2
C Extended Addressing
C Serial Interface
Supports 400 kHz Protocol
Single Supply Voltage:
– 4.5V to 5.5V for M24xxx – 2.5V to 5.5V for M24xxx-W
Hardware Write Control
BYTE and PAGE WRITE (up to 64 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Tim e d P ro g r amming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Behavior
More than 100,000 Erase/Write Cycles
More than 40 Year Data Retention
DESCRIPTION
These I
2
C-compatible electrically erasable pro­grammable memory (EEPROM) devices are orga­nized as 32Kx8 bits (M24256) and 16Kx8 bits (M24128), and operate down to 2.5 V (for the -W version of each device).
The M24256B, M2 4128B and M24256A are also available, and offer the extra functionality of the chip enable inputs. Please see the separate data sheets for details of these products.
The M24256 and M 24128 are available in Plastic Dual-in-Line and Plastic Small Outline packages.
These memory devices are compatible with the
2
C extended memory standard. This is a two wire
I
Table 1. Signal Names
SDA Serial Data/Address Input/
Output
8
PDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
Figure 1. Logic Diagram
V
CC
SCL
M24256
WC
M24128
1
8
1
SO8 (MW)
200 mil width
SDA
SCL Serial Clock WC V
CC
V
SS
Write Control Supply Voltage Ground
V
SS
AI01882
1/17June 2001
M24256, M24128
Figure 2A. DIP Connections
M24256 M24128
1
NC V
2 3
NC
4
SS
Note: 1. NC = Not Connected
8 7 6 5
AI01883
CC
WCNC SCL SDAV
serial interface that uses a bi-directiona l data bus and serial clock. The memory carries a built-in 4­bit unique Device Type Identifier code (1010) in accordance with the I
The memory behaves as a slave device in the I
2
C bus definition.
2
protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, gene rated by the bus master. The START condition is followed by a Device Select Code and RW
bit (as described in
Table 3), terminated by an acknowledge bit. When writing data to the memory, the mem ory in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and af­ter a NoAck for READ.
Figure 2B. SO C on ne ct i on s
M24256 M24128
NC V
1 2
NC
SS
Note: 1. NC = Not Connected
Power On Reset: V
3 4
CC
8 7 6 5
AI01884
CC
WCNC SCL SDAV
Lock-Out Write Protect
In order to prevent data corruption and inadvertent write operations during power up, a Power On Re­set (POR) circuit is included. The internal reset is
C
held active until the V
voltage has reached the
CC
POR threshold value, and all operations are dis­abled – the device will not respond to any com­mand. In the same way, when V
drops from the
CC
operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any com ma nd. A s table a nd v alid V must be applied before applying any logic signal.
SIGNAL DESCRIPTION Serial Clock (SCL)
The SCL input pin is used to strobe all data in and out of the memory. In applications where this line is used by slaves to synchronize the bus to a slow-
CC
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD Electrostatic Discharge Voltage (Human Body model)
Note: 1. Exc ept for the rating “Operating Temperature Range”, stresses above those l i sted in the Table “Absolute Maximum Ratings” may
2/17
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indica te d i n the Operating secti ons of this specification is not im plied. Exposure to Absolute Ma xim um Rating condi­tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. IPC/ JEDEC J-STD- 02 0A
3. JED EC St d JESD22-A11 4A (C1=100 pF, R1=15 00 Ω, R2=500 Ω)
Ambient Operating Temperature –40 to 125 °C Storage Temperature –65 to 150 °C
Lead Temperature during Soldering
Input or Output range –0.6 to 6.5 V Supply Voltage –0.3 to 6.5 V
1
PDIP: 10 seconds SO: 20 seconds (max)
3
2
260 235
4000 V
°C
M24256, M24128
er clock, the master must have an open drain out­put, and a pull-up resistor must be connected from the SCL line to V
. (Figure 3 indicates how the
CC
value of the pull-up res istor c an be calculated). In most applications, though, this method of synchro­nization is not employed, and so the pull-up resis­tor is not necessary, provided that the master has a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans­fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to V
. (Figure 3 indicates how the value of the
CC
pull-up resistor can be calculated).
Write Control (WC
The hardware Write Control pin (WC
)
) is useful for protecting the entire contents of the memory from inadvertent erase/write. The Write Control signal is used to enable (WC
=VIL) or disable (WC=VIH) write instructions to the entire memory area. When unconnected, the WC V
, and write operations are allowed.
IL
When WC
=1, Device Select and Address bytes
input is internally read as
are acknowledged, Data bytes are not acknowl­edged.
Please see the Application Note
AN404
for a more
detailed description of the Write Control feature.
DEVICE OPERATION
2
The memory device supports the I
C protocol. This is summarized in Figure 4, and is compared with other serial bus protocols in Application Note
AN1001
. Any device that sends data on to the bus
is defined to be a transm itter, and any device that
reads the data to be a receiver. The device that controls the data transfer is k nown as the master, and the other as the slave. A data transfer can only be initiated by the mas ter, which wi ll also provide the serial clock for synchronization. The memory device is always a slave device in all comm unica­tion.
Start Condition
START is identified by a high t o low transition of the SDA line while the clock, SCL, is stable i n the high state. A START condition must precede any data transfer comman d. Th e m em ory devi ce con­tinuously monitors (except during a program ming cycle) the SDA and SCL lines for a START condi­tion, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the SDA line wh ile th e clock S CL is sta ble in the h igh state. A STO P condition terminates c ommunica­tion between the memory device and the bus mas­ter. A STOP condition at the end of a Read command, after (and only after) a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write command triggers the interna l EEPRO M write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc­cessful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9
th
clock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal
Figure 3. Maximum R
20
16
12
8
Maximum RP value (k)
4
0
10 1000
Value versus Bus Capacitance (C
L
fc = 100kHz
fc = 400kHz
100
C
(pF)
BUS
) for an I2C Bus
BUS
V
MASTER
CC
SDA
SCL
R
R
C
BUS
L
C
BUS
AI01665
3/17
L
M24256, M24128
2
Figure 4. I
C Bus Protocol
SCL
SDA
SCL
SDA
SCL
SDA
START
Condition
START
Condition
1 23 789
MSB
1 23 789
MSB ACK
SDA Input
SDA
Change
STOP
Condition
ACK
STOP
Condition
AI00792B
must be stable during the clock low-to-high transi­tion, and the data must change
only
when the SCL
line is low.
Memory Addressing
To start communication betwee n the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first). This consists of the 7-bit Device Select Code, and the 1-bit Read/Write Designator (RW). The Device Select Code i s fur-
Table 3. Device Select Code
b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code 1 0 1 0 0 0 0 RW
Note: 1. The most significant bit, b7, is sent first.
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1
Device Type Identifier Chip Enable RW
ther su bdi v i de d i n to : a 4 -b i t D ev i ce Ty pe I d en t if i er ,
and a 3-bit Chip Enable “Address” (0, 0, 0). To address the memory array, the 4-bit Device
Type Identifier is 1010b.
th
The 8
bit is th e RW bit. This is set to ‘1’ for read and ‘0’ for write operations. If a match occurs on the Device Select Cod e, th e corresponding mem­ory gives an acknowledgment on the SDA bus dur­ing the 9
th
bit time. If the memo ry does n ot ma tch the Device Select Code, it deselects itself from the bus, and goes into stand-by mode.
Table 4. Operating Modes
Mode RW bit
Current Address Read 1 X 1 START, Device Select, RW
0X
Random Address Read
1 X reSTART, Device Select, RW Sequential Read 1 X Byte Write 0 Page Write 0
Note: 1. X = V
IH
or V
.
IL
WC
V V
1
Data Bytes Initial Sequence
START, Device Select, RW
1
1 Similar to Current or Random Address Read
IL
IL
1 START, Device Select, RW = ‘0’
64 START, Device Select, RW
M24256, M24128
= ‘1’ = ‘0’, Address
= ‘1’
= ‘0’
There are two modes both for read and write. These are summarized in Table 4 and described later. A communication between the m aster and the slave is ended with a STOP condition.
Each data byte in the m emory has a 16-bit (two byte wide) address. The Most Significant Byte (Ta-
ble 5) is sent first, f ollowed by the Least significant Byte (Table 6). Bits b15 to b0 form t he add ress of
the byte in memory. Bit b15 is t reated as a Don’t Care bit on the M24256 memory. Bits b15 and b14 are treated as Don’t Care bits on the M24128 memory.
Figure 5. Wri te Mo de S e qu e nces with WC=1 (data write inhib i ted)
WC
ACK ACK ACK NO ACK
BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN
R/W
START
WC
ACK ACK ACK NO ACK
PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1
STOP
DATA IN 2
WC (cont'd)
PAGE WRITE (cont'd)
R/W
START
NO ACK NO ACK
DATA IN N
STOP
AI01120C
5/17
M24256, M24128
Figure 6. Wri te Mo de S e qu e nces with WC=0 (data write enab led )
WC
ACK
BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN
R/W
START
WC
ACK ACK ACK ACK
PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1
R/W
START
WC (cont'd)
ACKACK
PAGE WRITE (cont'd)
DATA IN N
ACK ACK ACK
STOP
DATA IN 2
STOP
Table 5. Most Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8
Note: 1. b15 is tr eated as Don’t Ca re on the M24256 series.
b15 and b14 ar e Don’t Care on the M24128 series.
Table 6. Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
Write Operations
Following a START con dition the ma ster sends a Device Select Code with the RW
bit set to ’0’, as shown in Table 4. The memory acknowledges this, and waits for two address bytes. The memory re­sponds to each address byte with an acknowledge bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC input pin is taken high. Any write command with
=1 (during a period of time from the START
WC
AI01106B
condition until the end of the two address bytes) will not modify the me mory c ontents, and t he ac-
not
companying data bytes will
be acknowledged,
as shown in Figure 5.
Byte Write
In the Byte Write mode, after the Device Select Code and the address bytes, the master sends one data byte. If the addressed lo cation is write protected by the WC
pin, the memory replies with a NoAck, and the location is not modified. If, in­stead, the WC
pin has been held at 0, as shown in Figure 6, the memory replies with an Ack. The master terminates the transfer by generating a STOP condition.
Page Write
The Page Write mode allows u p to 64 by tes to be written in a single write cycle, provided that they are all located in the same ’row’ in the memory: that is the most significant memory add ress bits (b14-b6 for the M24256 and b13-b6 for the M24128) are the same. If more bytes are sent than
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