M24C16, M24C08
M24C04, M24C02, M24C01
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
■ Two-Wire I²C Serial Interface
Supports 400kHz Protocol
■ Single Supply Voltage:
– 2.5 to 5.5V for M24Cxx-W
– 1.8 to 5.5V for M24Cxx-R
■ Write Control Input
■ BYTE and PAGE WRITE (up to 16 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Protection
■ More than 1 Million Erase/Write Cycles
■ More than 40-Year Data Retention
■ Packages
– ECOPACK® (RoHS compliant)
Table 1. Product List
Reference Part Number
M24C16-W
M24C16
M24C16-R
M24C08-W
M24C08
M24C08-R
M24C04-W
M24C04
M24C04-R
M24C02-W
M24C02
M24C02-R
M24C01-W
M24C01
M24C01-R
Figure 1. Packages
PDIP8 (BN)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
TSSOP8 (DS)
3x3mm² body size (MSOP)
UFDFPN8 (MB)
2x3mm² (MLP)
1/28January 2006
M24C16, M24C08, M24C04, M24C02, M24C01
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. 8-Pin Package Connections (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data (SDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Device Select Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Control (WC
Supply voltage (V
Operating supply voltage V
Internal Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I²C Bus . . . . . . . . . . . 6
Figure 6. I²C Bus Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Device Select Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
CC
CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Write Mode Sequences with WC
=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Write Mode Sequences with WC
=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10.Read Mode Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2/28
M24C16, M24C08, M24C04, M24C02, M24C01
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Operating Conditions (M24Cxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Operating Conditions (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. DC Characteristics (M24Cxx-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. DC Characteristics (M24Cxx-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. DC Characteristics (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. AC Characteristics (M24Cxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 14. AC Characteristics (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 21
Table 15. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 21
Figure 14.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . .22
Table 16. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 17. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 24
Table 18. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 24
Figure 17.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size,
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size,
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3/28
M24C16, M24C08, M24C04, M24C02, M24C01
SUMMARY DESCRIPTION
These I²C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 2048/1024/512/256/128 x 8 (M24C16,
M24C08, M24C04, M24C02 and M24C01).
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
ECOPACK® packages are Lead-free and RoHS
compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 2. Logic Diagram
V
CC
3
E0-E2 SDA
SCL
WC
M24Cxx
V
SS
AI02033
I²C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I²C bus definition.
The device behaves as a slave in the I²C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiated by a Start condition, generate d by the bus master. The Start condition is followed by a Device
Select Code and Read/Write
bit (RW) (as described in Table 3.), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Writ e, and afte r a
NoAck for Read.
Table 2. Signal Names
E0, E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC
V
CC
V
SS
Write Control
Supply Voltage
Ground
Figure 3. 8-Pin Package Connections (Top View)
M24Cxx
/2Kb/4Kb/8Kb16Kb
/1Kb
/ E0/ NC/ NCNC
/ E1/ E1/ NCNC
/ E2/ E2/ E2NC
Note: 1. NC = Not Connected
2. See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.
4/28
/ E0
/ E1
/ E2
SS
1
2
3
4
V
8
CC
WC
7
SCL
6
SDAV
5
AI02034E
SIGNAL DESCRIPTION
M24C16, M24C08, M24C04, M24C02, M24C01
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to V
. (Figure 5.
CC
indicates how the value of the pull-up resistor can
be calculated). In most applicat ions, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V
CC
. (Fig-
ure 5. indicates how the value of the pull-up resis-
tor can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used t o set the va lue that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit De vice Select Code. These
inputs must be tied to V
or VSS, to establish the
CC
Device Select Code as shown in Figure 4.
Figure 4. Device Select Code
V
CC
M24Cxx
E
i
V
SS
V
CC
M24Cxx
E
i
V
SS
Ai11650
Write Control (WC
). This input signal is useful
for protecting the entire contents of the memory
from inadvertent write operations. Write operations are disabled to the entire memory array when
Write Control (WC
nected, the signal is internally read as V
) is driven High. When uncon-
, and
IL
Write operations are allowed.
When Write Control (WC
) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Supply voltage (V
Operating supply voltage V
CC
)
. Prior to select-
CC
ing the memory and issuing instructions to it, a valid and stable V
voltage must be applied: this
CC
voltage must be a DC voltage within the specified
(min), VCC(max)] range, as defined in Table
[V
CC
6. and Table 7. In order to secure a stable DC sup-
ply voltage, it is recommended to decouple the
line with a suitable capacitor (usually of the
V
CC
order of 10nF to 100nF) close to the V
CC/VSS
package pins.
The V
voltage must remain stable and valid until
CC
the end of the transmission of the instruction and,
for a Write instruction, until the completion of the
internal write cycle (t
).
W
Internal Device Reset. In order to pr event inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up
(continuous rise of V
spond to any instruction until V
), the device does not re-
CC
has reached the
CC
Power On Reset threshold voltage (this threshold
is lower than the minimum V
operating voltage
CC
defined in Table 6. and Table 7.).
When V
has passed the POR threshold, the de-
CC
vice is reset and in the Standby Power mode
Power-down. At Power-down (where V
creases continuously), as soon as V
drops from
CC
CC
de-
the operating voltage range below the Power On
Reset threshold voltage, the device stops responding to any instruction sent to it.
During Power-down, the device must be deselected and in the Standby Power mode (that is there
should be no internal Write cycle in progress).
5/28
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 5. Maximum RP Value versus Bus Parasitic Capacita nce (C) for an I²C Bus
V
20
16
12
8
Maximum RP value (kΩ)
4
0
10
Figure 6. I²C Bus Protocol
SCL
fc = 400kHz
100
C (pF)
fc = 100kHz
1000
CC
MASTER
SDA
SCL
R
R
P
P
C
C
AI01665b
SDA
SCL
SDA
SCL
SDA
START
Condition
START
Condition
1 23 7 89
MSB
1 23 7 89
MSB ACK
SDA
Input
SDA
Change
STOP
Condition
ACK
STOP
Condition
AI00792B
6/28
M24C16, M24C08, M24C04, M24C02, M24C01
Table 3. Device Select Code
Device Type Identifier
1
Chip Enable
b7 b6 b5 b4 b3 b2 b1 b0
M24C01 Select Code 1 0 1 0 E2 E1 E0 RW
M24C02 Select Code 1 0 1 0 E2 E1 E0 RW
M24C04 Select Code 1 0 1 0 E2 E1 A8 RW
M24C08 Select Code 1 0 1 0 E2 A9 A8 RW
M24C16 Select Code 1 0 1 0 A10 A9 A8 RW
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
3. A10, A9 and A8 represent most significant bits of the address.
2,3
RW
7/28
M24C16, M24C08, M24C04, M24C02, M24C01
DEVICE OPERATION
The device supports the I²C protocol. This is summarized in Figure 6.. Any device that sends data
on to the bus is defined to be a transmitter, and
any device that reads the data to be a receiver.
The device that controls the data transfer is known
as the bus master, and the other as the slave device. A data transfer can only be initiated by the
bus master, which will also provide the serial clock
for synchronization. The M24Cxx device is always
a slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the in ternal Write
cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
th
clock pulse period, the receiver pulls Serial
9
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driven Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 3.
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory ar ray, the 4bit Device Type Identifier is 1010b.
Each device is given a unique 3-bit code on the
Chip Enable (E0, E1, E2) inputs. When the Device
Select Code is received, the device only responds
if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. However, those devices with larger memory capacities
(the M24C16, M24C08 and M24C04) need more
address bits. E0 is not available for u se on devices
that need to use address line A8; E1 is not available for devices that need to use address line A9,
and E2 is not available for devices that need to use
address line A10 (see Figure 3. and Table 3. for
details). Using the E0, E1 and E2 inputs, up to
eight M24C02 (or M24C01), four M24C04, two
M24C08 or one M24C16 devices can be connected to one I²C bus. In each case, and in the hybrid
cases, this gives a total memory capacity of
16 Kbits, 2 KBytes (except where M24C01 devices are used).
th
The 8
bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9
th
bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into St andby mode.
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M24C16, M24C08, M24C04, M24C02, M24C01
Table 4. Operating Modes
Mode RW bit
Current Address Read 1 X 1 START, Device Select, RW
0X
Random Address Read
1 X reSTART, Device Select, RW
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0
Page Write 0
Note: 1. X = V
IH
or V
.
IL
Figure 7. Write Mode Sequences with WC=1 (data write inhibite d)
WC
Byte Write DEV SEL BYTE ADDR DATA IN
WC
(1)
Bytes Initial Sequence
START, Device Select, RW
1
V
IL
V
IL
ACK ACK NO ACK
1 START, Device Select, RW = 0
≤ 16 START, Device Select, RW = 0
= 1
= 0, Address
= 1
R/W
START
WC
ACK ACK NO ACK NO ACK
Page Write DEV SEL BYTE ADDR DATA IN 1 DATA IN 2
R/W
START
WC (cont'd)
NO ACK NO ACK
Page Write
(cont'd)
DATA IN N
STOP
STOP
DATA IN 3
AI02803C
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