- Up to 32 programmable I/O functions on 4
GPIO programmable module pins
Three Carrier Frequency versions
- 433 MHz for externally tuned antenna
- 868 MHz for externally tuned antenna
- 915 MHz for externally tuned antenna
Preliminary module picture
11.5 mm x 13.5 mm x 2.0 mm
SPSGRFC
1 Description
The SPSGRFC is an easy to use Sub1GHz transceiver module, with many
programmable features. The module provides a complete RF platform in a tiny form
factor.
The SPSGRFC enables electronic devices with wireless connectivity, not requiring any
RF experience or expertise for integration into the final product. The SPSGRFC, being a
certified solution, optimizes the time to market of the final applications.
The module is designed for maximum performance in a minimal space including 4
programmable I/O pin and SPI serial interface.
2 Applications
AMR (automatic meter reading)
Home and building automation
WSN (wireless sensors network)
Industrial monitoring and control
Wireless fire and security alarm systems
Point-to-point wireless link
P a g e | 2 Rev 0.1
SPSGRFC
UFL RF connector
for external antenna
Battery or External Supply
SPI LINE
M.C.U. clock
SPSGRF-xxx Module - 2016
SUPPLY FILTER
Bead Ferrite
RF
BALUN
+ Filter
50 MHz
Crystal
868 MHz or 915 MHz
or 433 MHz
EXTERNAL ANTENNA
I/O
SPIRIT1
DEVICE
RF
TUNING
NETWORK
Programmable
I/O
Host Controller
interface
3 Block Diagram
Figure 1 – Block Diagram
Rev 0.1 P a g e | 3
SPSGRFC
4 Short description of the module functional behaviour
The SPIRIT1 device inside the SPSGRFC module is provided with a built-in main controller which controls
the switching between the two main operating modes: transmit (TX) and receive (RX).
In shutdown condition the SPSGRFC module can be switched on/off with the external pin SDN, all other
functions/registers/commands are available through the SPI interface and GPIOs. No internal supply is
generated (in order to have minimum battery leakage), and hence, all stored data and configurations are lost.
The GPIO and SPI ports of the module during SHUTDOWN are in HiZ. From shutdown state, the SPSGRFC
module can be switched on from the SDN pin and goes into READY state, which is the default, where the
reference signal from XO is available.
From READY state, the SPSGRFC module can be moved to LOCK state to generate the high precision LO
signal and/or TX or RX modes. Switching from RX to TX and vice versa can happen only by passing through
the LOCK state. This operation is normally managed by radio control with a single user command (TX or RX).
At the end of the operations above, the SPSGRFC module can return to its default state (READY) and can
then be put into a sleeping condition (SLEEP state), having very low power consumption.
If no timeout is required, the SPSGRFC module can be moved from READY to STANDBY state, which has
the lowest possible current consumption while retaining FIFO, status and configuration registers. To manage
the transitions towards and between these operating modes, the controller works as a state machine, whose
state switching is driven by SPI commands.
Figure 2 - Module functional states transitions diagram
P a g e | 4 Rev 0.1
Rating
Min
Typical
Max
Unit
Storage temperature range
-40 - +85
°C
Supply voltage, VIN
-0.3 - + 3.9
Volts
I/O pin Voltage
-0.3 - + 3.9
Volts
RF saturation input power
-
10
-
dBm
Rating
Min
Typical
Max
Unit
Operating Temperature Range
-40 - 85
°C
Supply Voltage VIN
1.8
3.3
3.6
Volts
Signals & I/O Pin Voltage
(according Supply Voltage)
1.8 - 3.6
Volts
RF Frequency Bandwidth
(SPSGRFC-433)
433.050
434.790
MHz
RF Frequency Bandwidth
(SPSGRFC-868)
863 870
MHz
RF Frequency Bandwidth
(SPSGRFC-915)
902 928
MHz
5 Hardware Specifications
General Conditions (VIN= 3.3V and 25°C)
5.1 Absolute Maximum Ratings
Table 1 - Absolute Maximum Ratings
5.2 Recommended Operating Conditions
Table 2 - Recommended Operating Conditions
Rev 0.1 P a g e | 5
SPSGRFC
Symbol
Parameter
Test conditions
Max
Unit
Idd
Supply
current
Operating mode
Tx, +11.6 dBm, 2-FSK, 433 MHz
22
mA
Operating mode
Tx, -7 dBm, 2-FSK, 433 MHz
9
mA
Operating mode Rx, 433 MHz
10
mA
Command mode
0.6
mA
Shutdown high level Vdd
With other I/O in High impedance
0.1
µA
Symbol
Parameter
Test conditions
Max
Unit
Idd
Supply
current
Operating mode
Tx, +11.6 dBm, 2-FSK, 868 MHz
22
mA
Operating mode
Tx, -7 dBm, 2-FSK, 868 MHz
9
mA
Operating mode Rx, 868 MHz
10
mA
Command mode
0.6
mA
Shutdown high level Vdd
With other I/O in High impedance
0.1
µA
Symbol
Parameter
Test conditions
Max
Unit
Idd
Supply
current
Operating mode
Tx, +11.6 dBm, 2-FSK, 915 MHz
22
mA
Operating mode
Tx, -7 dBm, 2-FSK, 915 MHz
9
mA
Operating mode Rx, 915 MHz
10
mA
Command mode
0.6
mA
Shutdown high level Vdd
With other I/O in High impedance
0.1
µA
5.3 Module current consumption
Table 3 – SPSGRFC-433 module current consumption
Table 4 – SPSGRFC-868 module current consumption
Table 5 – SPSGRFC-915 module current consumption
P a g e | 6 Rev 0.1
Name
Type
Pin #
Description
ALT Function
V max. Tolerant
Initial State
SPI Interface
SPI_CLK
I
7
SPI CLOCK (Max. 8 MHz)
Vin
SPI_MISO
O
8
SPI MISO (MASTER in / SLAVE out)
Vin
SPI_MOSI
I
9
SPI MOSI (MASTER out SLAVE in)
Vin
SPI_CS
I
10
SPI “Chip Select” (SPI slave select)
Vin
Power and Ground
Vin
5
Vin
(1.8V + 3.6V max.)
GND
6
GND
Module SHUTDOWN
SDN
I
11
SHUTDOWN input (active high)
(1.8V + 3.6V max.).
GPIO – General Purpose Input/Output
GPIO [0]
I/O
4
Programmable Input / Output
& Analog Temperature output
(1.8V + Vin max.).
Digital Output.
Low Power
GPIO [1]
I/O
3
Programmable Input / Output
(1.8V + Vin max.).
Digital Output.
Low Power
GPIO [2]
I/O
2
Programmable Input / Output
(1.8V + Vin max.).
Digital Output.
Low Power
GPIO [3]
I/O
1
Programmable Input / Output
(1.8V + Vin max.).
Digital Output.
Low Power
Optional External Antenna connections (Not available on the standard SPSGRFC-xxx modules)
N.C.
N.C
12
Not connected
N.C.
N.C.
13
Not connected
N.C.
N.C.
14
Not connected
5.4 Pin Assignement
Figure 3 – Pin connection diagram
Table 6 – Pin Assignment
Rev 0.1 P a g e | 7
SPSGRFC
6 Mechanical dimensions
Figure 4 – Mechanical Dimensions
Figure 5 – Recommend land pattern
P a g e | 8 Rev 0.1
Modulation
Standards
Parameter
Max.
Unit
2-FSK
GFSK
MSK
FCC Part 15.207 (1)
FCC Part 15.247 (1)
IC RSS-210 (1)
EN 300 220-2 V2.4.1
EN301 489-01 V1.9.2
EN301 489-03 V1.4.1
Data Rate
500
kbps
Output
power
+11.6
dBm
OOK
ASK
FCC Part 15.207 (1)
FCC Part 15.247 (1)
IC RSS-210 (1)
Data Rate
All unused pins should be left floating; do not ground.
All GND pins must be well grounded.
The area around the module should be free of any ground planes, power planes, trace
routings, or metal for 6 mm from the module antenna position, in all directions.
Traces should not be routed underneath the module.
7.1 Modules RF compliance limits
The RF compliance limits are those tested for FCC, IC and CE certification using the dedicated
dongle (PC92A.V01). These limits are enforced by the dongle firmware. Care must be taken with
custom application firmware to ensure these limits are not exceeded, voiding the FCC, IC and CE
certification.
(1) FCC and IC standards are applicable only to the SPSGRFC-915 module.
Rev 0.1 P a g e | 9
Table 7. RF compliance limits table
SPSGRFC
8 Module user firmware short description
For more user firmware information, please refer to the SPIRIT1 Datasheet - October 2016
DocID022758 Rev 10.
Downloadable at the following link: www.st.com/resource/en/datasheet/bluenrg-1.pdf
The following are short firmware notes, useful to furnish to the user a condensed view of the many
programming ways of the SPSGRFC-xxx module. (The following “Register table” refers the SPIRIT1
datasheet, so the table numbers and the links into the table are referred to the same document).
Register table
This section describes all the registers used to configure the SPIRIT1 device, assembled into the module.
The description is structured in sections according to the register usage.
SPIRIT1 has three types of registers:
Read and write (R/W), which can be completely managed by SPI using READ and
WRITE operations
Read-only (R)
Read-and-reset (RR), is automatically cleared after a READ operation.
A further category of special registers collects the ones which cannot be categorized in any
of the three mentioned above R/W, R, or RR.
The fields named as “Reserved” must not be overridden by the user, otherwise, behavior is
not guaranteed.
The memory map is shown in the following table:
P a g e | 10 Rev 0.1
Rev 0.1 P a g e | 11
SPSGRFC
P a g e | 12 Rev 0.1
Rev 0.1 P a g e | 13
SPSGRFC
P a g e | 14 Rev 0.1
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