AN5549
Application note
SPC5x Power PC Interrupts
This document is intended for software and hardware developers who need to understand Interrupts, how to generate and handle them for all cores integrated into SPC5x Automotive Microcontroller devices.
The main goal of this document is to clarify Interrupts management, and to provide reference codes to manage Interrupts as well as the execution scenario.
This document also describes software and hardware interrupt management for External Interrupts.
AN5549 - Rev 1 - September 2020 |
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AN5549
1Interrupts and Exceptions
An interrupt is the action in which the processor saves its context (typically the machine state register [MSR] and the next instruction address) and begins the execution at a predetermined interrupt handler address with a modified MSR.
Core exception occurs when the flow of the execution is diverted, to allow the MCU to handle events generated by internal or external sources. So the exceptions are generated by signals from internal and external peripherals, instructions, the internal timer facility, debug events, or error conditions.
When an exception is received, the Core saves its context and starts executing at a predetermined address. Common types of exceptions are described in Table 1.
Table 1. Common Interrupt types
Exception types |
IVPR Offset |
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System Reset |
0x00 |
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Machine Check |
0x10 |
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Non-Maskable Input Interrupt |
0x20 |
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Critical Input Interrupt |
0x30 |
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External Input Interrupt |
0x40 |
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Performance Monitor Interrupts |
0x50 |
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Instruction Based Debug Interrupts |
0x60 |
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Debug Interrupt |
0x70 |
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Debug Imprecise Interrupt |
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Data Storage / Alignment Interrupts |
0x80 |
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Instruction Storage Interrupts |
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The Interrupt Vector Prefix Register is used during the exception processing for determining the starting address of a software handler used to handle an exception.
The value of the Vector Offset selected for a specific exception type is concatenated with the Vector Base value held in the Interrupt Vector Prefix register (IVPR) to form an instruction address from which execution is to begin.
The structure of the IVPR register is described in Figure 1 (more details can be found in the Reference Manuals of specific devices).
Figure 1. Interrupt Vector Prefix Register
The description of the process for taking an exception is described in Figure 2.
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Figure 2. Process of taking an exception
1.2Interrupts
An interrupt is an exception that is signaled to the interrupt controller (INTC) and generated by a peripheral or by the application code using software interrupts.
The interrupt controller is responsible to manage the interrupts generated by a peripheral. Source of interrupts can be:
•Internal peripherals (embedded IPs e.g.[PC1] I2C, DSPI, SWT, etc.)
•External devices via microcontroller pins
The interrupt controller operates in two modes:
•Software vector mode
•Hardware vector mode
Selection of the operating mode is done by an enable bit (HVEN) in INTC Block Configuration Register (BRC)
•Software vector mode: BCR[HVENx] = 0
•Hardware vector mode: BCR[HVENx] = 1
where ‘x’ in HVEN bit is [0,1,2] to refer to Core_0, Core_1, Core_2 (if available).
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Interrupts
In the software Vector Mode, as soon as a peripheral interrupt is raised, the External Interrupt Exception (offset 0x40) is generated. The code at offset 0x40 from IVPR is executed.
In order to take the interrupt, the code at offset 0x40 from IVPR should:
•Reserve appropriate space on the stack to save the Core context (PC, MSR, SRR0, SRR1, CR, LR, CTR, XER, GPR0, …, GPR12)
•Read the INTC IACKR register to get the pointer to the software handler managing the specific peripheral interrupt (ISR)
•Enable global interrupts (to allow nested interrupts)
•Jump to the ISR
•Disable global interrupts
•Acknowledge the interrupt on the interrupt controller (INTC)
•Restore the context
•Return from interrupt (to normal execution)
In the software Vector Mode all peripheral interrupts generate the External Interrupt Exception as described in Figure 3.
Figure 3. Software Vector Mode Interrupts
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Interrupts |
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1.2.3 |
Hardware Vector Mode |
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In the hardware Vector Mode, as soon as a peripheral interrupt is raised, the control jumps to execute the code |
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ecut on address = |
Vectorbase + 0 1000 + nterrupt number × 4 |
(1) |
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located at a specific addr ss in the Interrupt |
table which can be calculated as follows: |
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Where:
•Vector Base is the content of the IVPR register
•0x1000 is a 4 Kb fixed offset
•Interrupt Number is the interrupt number associated with the peripheral which has raised the interrupt
After taking an interrupt, the execution will continue executing code at Execution Address where there will be an unconditional jump to the peripheral ISR.
The peripheral ISR:
•Reserves appropriate space on the stack to save the Core context (PC, MSR, SRR0, SRR1, CR, LR, CTR, XER, GPR0, …, GPR12)
•Enables global interrupts (to allow nested interrupts)
•Manages the peripheral interrupt(s)
•Disables global interrupts
•Acknowledges the interrupt on the interrupt controller (INTC)
•Restores the context
•Returns from interrupt (to normal execution)
The hardware Vector Mode is described in Figure 4.
Figure 4. Hardware Vector Mode Interrupts
In the software Vector Mode all peripherals and external interrupts are routed to a single exception line (at offset 0x40, External Input) which, after reading the interrupt source ISR address from INTC IACKR register, jumps to this handler. The code handling the External Input exception is also responsible for saving and restoring the microcontroller context. In other words, there is only one place for all peripheral and external interrupts where to save/restore the microcontroller context saving code space. On the other side to take an interrupt there is an extra jump: first read the INTC in order to understand where is located the peripheral ISR, then do the jump to the ISR.
In the hardware Vector Mode, the jump to the peripheral ISR is done just after taking the interrupt (as first action) then the ISR saves the context and manages the peripheral interrupt. Compared to the software Vector Mode there is a jump less. The disadvantage is, there is an increase in code size: each interrupt service routine (ISR) must save/restore the microcontroller context before managing the handler.
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