SPC584Cx, SPC58ECx
SPC58 C Line - 32 bit Power Architecture automotive MCU Dual z4 cores 180 MHz, 4 MBytes Flash, HSM, ASIL-B
eTQFP64 (10 x 10 x 1.0 mm) |
eTQFP100 (14 x 14 x 1.0 mm) |
eTQFP144 (20 x 20 x 1.0 mm) eLQFP176 (24 x 24 x 1.4 mm)
FPBGA292 (17x17x1.8mm)
Features
• AEC-Q100 qualified
•High performance e200z420n3 dual core
–32-bit Power Architecture technology CPU
–Core frequency as high as 180 MHz
–Variable Length Encoding (VLE)
•4224 KB (4096 KB code flash + 128 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
•176 KB HSM dedicated flash memory (144 KB code + 32 KB data)
•384 KB on-chip general-purpose SRAM (in addition to 128 KB core local data RAM: 64 KB included in each CPU)
•Multi-channel direct memory access controller (eDMA) with 64 channels
•1 interrupt controller (INTC)
•Comprehensive new generation ASIL-B safety concept
–ASIL-B of ISO 26262
Datasheet -production data
–Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
–Cyclic redundancy check (CRC) unit
•Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
•Body cross triggering unit (BCTU)
–TriggersADC conversions from any eMIOS channel
–Triggers ADC conversions from up to 2 dedicated PIT_RTIs
•Enhanced modular IO subsystem (eMIOS): up to 64 timed I/O channels with 16-bit counter resolution
•Enhanced analog-to-digital converter system with:
–3 independent fast 12-bit SAR analog converters
–1 supervisor 12-bit SAR analog converter
–1 10-bit SAR analog converter with STDBY mode support
•Communication interfaces
–18 LINFlexD modules
–8 deserial serial peripheral interface (DSPI) modules
–8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support
–Dual-channel FlexRay controller
–1 ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008
•Low power capabilities
–Versatile low power modes
–Ultra low power standby with RTC
–Smart Wake-up Unit for contact monitoring
–Fast wakeup schemes
–FCCU for collection and reaction to failure notifications
•Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell
July 2020 |
DS11620 Rev 7 |
1/153 |
This is information on a product in full production. |
www.st.com |
SPC584Cx, SPC58ECx
•Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard
•BootassistFlash(BAF)supportsfactoryprogrammingusingaserialbootloadthroughthe asynchronous CAN or LIN/UART
•Junction temperature range -40 °C to 150 °C
Table 1. Device summary
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Part number |
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Package |
2 MB |
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3 MB |
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4 MB |
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Single core |
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Dual core |
Single core |
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Dual core |
Single core |
Dual core |
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eTQFP64 |
SPC584C70E1 |
SPC58EC70E1 |
SPC584C74E1 |
SPC58EC74E1 |
SPC584C80E1 |
SPC58EC80E1 |
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eTQFP100 |
SPC584C70E3 |
SPC58EC70E3 |
SPC584C74E3 |
SPC58EC74E3 |
SPC584C80E3 |
SPC58EC80E3 |
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eTQFP144 |
SPC584C70E5 |
SPC58EC70E5 |
SPC584C74E5 |
SPC58EC74E5 |
SPC584C80E5 |
SPC58EC80E5 |
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eLQFP176 |
SPC584C70E7 |
SPC58EC70E7 |
SPC584C74E7 |
SPC58EC74E7 |
SPC584C80E7 |
SPC58EC80E7 |
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FPBGA292 |
SPC584C70C3 |
SPC58EC70C3 |
SPC584C74C3 |
SPC58EC74C3 |
SPC584C80C3 |
SPC58EC80C3 |
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2/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
Contents |
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Contents
1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 6 |
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2 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
7 |
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2.1 |
Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
7 |
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2.2 |
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
8 |
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2.3 |
Features overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
3 |
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . |
13 |
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4 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
14 |
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1 Power domains and power up/down sequencing . . . . . . . . . . . . . . . . . 19
4.4 |
Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
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4.5 |
Electromagnetic compatibility characteristics . . . . . . . . . . . . . . . . . . . . . . |
21 |
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4.6 |
Temperature profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
22 |
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4.7 |
Device consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
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4.8 |
I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
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4.8.1 |
I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
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4.8.2 |
I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
29 |
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4.8.3 |
I/O pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
34 |
4.9 Reset pad (PORST) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 37 4.10 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.10.1 PLL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.10.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.11 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.11.1 Crystal oscillator 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.11.2 Crystal Oscillator 32 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.11.3 RC oscillator 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.11.4 Low power RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.12 ADC system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.12.1 ADC input description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DS11620 Rev 7 |
3/153 |
Contents |
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SPC584Cx, SPC58ECx |
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4.12.2 |
SAR ADC 12-bit electrical specification . . . . . . . . |
. . . . . . . . . . . . . . . . . 48 |
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4.12.3 |
SAR ADC 10-bit electrical specification . . . . . . . . |
. . . . . . . . . . . . . . . . . 53 |
4.13 |
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . 56 |
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4.14 |
LFAST pad electrical characteristics . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . 57 |
4.14.1 LFAST interface timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.14.2 LFAST LVDS interface electrical characteristics . . . . . . . . . . . . . . . . . . 58 4.14.3 LFAST PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.15 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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4.15.1 |
Power management integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 63 |
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4.15.2 |
Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 69 |
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4.15.3 |
Voltage monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 70 |
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4.16 |
Flash . |
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73 |
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4.17 |
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
77 |
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4.17.1 Debug and calibration interface timing . . . . . . . . . . . . . . . . . . . . . . . . |
. 77 |
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4.17.2 DSPI timing with CMOS pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 83 |
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4.17.3 |
Ethernet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 93 |
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4.17.4 |
FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 99 |
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4.17.5 |
CAN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
103 |
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4.17.6 |
UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
103 |
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4.17.7 |
I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
104 |
5 |
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
106 |
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5.1 |
eTQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
106 |
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5.1.1 |
Package mechanical drawings and data information . . . . . . . . . . . . . |
110 |
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5.2 |
eTQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
111 |
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5.2.1 |
Package mechanical drawings and data information . . . . . . . . . . . . . |
115 |
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5.3 |
eTQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
116 |
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5.3.1 |
Package mechanical drawings and data information . . . . . . . . . . . . . |
120 |
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5.4 |
eLQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
121 |
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5.4.1 |
Package mechanical drawings and data information . . . . . . . . . . . . . |
125 |
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5.5 |
FPBGA292 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
126 |
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5.5.1 |
Package mechanical drawings and data information . . . . . . . . . . . . . |
128 |
5.6 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.6.1 eTQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.6.2 eTQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.6.3 eTQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
Contents |
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5.6.4 LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.6.5 FPBGA292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.6.6General notes for specifications at maximum junction temperature . . 133
6 |
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
136 |
7 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
140 |
DS11620 Rev 7 |
5/153 |
Introduction |
SPC584Cx, SPC58ECx |
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1Introduction
This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet.
6/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
Description |
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2Description
The SPC584Cx and SPC58ECx microcontroller is the first in a new family of devices superseding the SPC564Cx and SPC56ECx family. SPC584Cx and SPC58ECx builds on the legacy of the SPC564Cx and SPC56ECx family, while introducing new features coupled with higher throughput to provide substantial reduction of cost per feature and significant power and performance improvement (MIPS per mW). On the SPC584Cx and SPC58ECx device, there are two processor cores e200z420 and one e200z0 core embedded in the Hardware Security Module.
2.1Device feature summary
Table 2 lists a summary of major features for the SPC584Cx and SPC58ECx device. The feature column represents a combination of module names and capabilities of certain modules. A detailed description of the functionality provided by each on-chip module is given later in this document.
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Table 2. Features List |
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Feature |
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Description |
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SPC58 family |
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40 nm |
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Number of Cores |
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2 |
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Local RAM |
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2x 64 KB Data |
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Single Precision Floating Point |
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Yes |
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SIMD |
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No |
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VLE |
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Yes |
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Cache |
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8 KB Instruction |
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4 KB Data |
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MPU |
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Core MPU: 24 per CPU |
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System MPU: 24 per XBAR |
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Semaphores |
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Yes |
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CRC Channels |
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2 x 4 |
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Software Watchdog Timer (SWT) |
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3 |
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Core Nexus Class |
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3+ |
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Event Processor |
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4 x SCU |
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4 x PMC |
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Run control Module |
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Yes |
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System SRAM |
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384 KB (including 256 KB of standby RAM) |
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Flash |
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4096 KB code / 128 KB data |
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Flash fetch accelerator |
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2 x 4 x 256-bit |
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DMA channels |
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64 |
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DS11620 Rev 7 |
7/153 |
Description |
SPC584Cx, SPC58ECx |
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Table 2. Features List (continued) |
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Feature |
Description |
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DMA Nexus Class |
3 |
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LINFlexD |
18 |
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MCAN (ISO CAN-FD compliant) |
8 |
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DSPI |
8 |
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I2C |
1 |
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FlexRay |
1 x Dual channel |
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Ethernet |
1 MAC with Time Stamping, AVB and VLAN support |
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SIPI / LFAST Debugger |
High Speed |
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8 PIT channels |
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System Timers |
4 AUTOSAR® (STM) |
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RTC/API |
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eMIOS |
2 x 32 channels |
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BCTU |
64 channels |
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Interrupt controller |
1 x 568 sources |
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ADC (SAR) |
5 |
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Temp. sensor |
Yes |
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Self Test Controller |
Yes |
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PLL |
Dual PLL with FM |
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Integrated linear voltage regulator |
Yes |
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External Power Supplies |
5 V, 3.3 V |
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HALT Mode |
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Low Power Modes |
STOP Mode |
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Smart Standby with output controller, analog and digital inputs |
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Standby Mode |
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2.2Block diagram
The figures below show the top-level block diagrams.
8/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
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Description |
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Figure 1. Block diagram |
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JTAGM |
JTAGC |
DCI |
SPU |
NPC |
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INTC |
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SWT_2 IAC |
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e200 z420n3 – 180 MHz |
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dual issue |
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Nexus3p |
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Main Core_2 |
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<![if ! IE]> <![endif]>Checkers |
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<![if ! IE]> <![endif]>0 |
<![if ! IE]> <![endif]>1 |
<![if ! IE]> <![endif]>2 |
<![if ! IE]> <![endif]>3 |
<![if ! IE]> <![endif]>Checkers |
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VLE |
EFPU2 |
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<![if ! IE]> <![endif]>CHMUXDMA |
<![if ! IE]> <![endif]>CHMUXDMA |
<![if ! IE]> <![endif]>CHMUXDMA |
<![if ! IE]> <![endif]>CHMUXDMA |
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I-Cache |
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Control |
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<![if ! IE]> <![endif]>Redundancywithstep-Lock |
<![if ! IE]> <![endif]>0FlexRay |
<![if ! IE]> <![endif]>0ETHERNET |
<![if ! IE]> <![endif]>1SIPI |
32 ADD |
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<![if ! IE]> <![endif]>Redundancywithstep-Lock |
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Unified |
8 KB |
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Backdoor |
2 way |
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64 Ch |
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Interface |
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With |
D-MEM |
D-Cache |
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eDMA_1 |
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E2E ECC |
Control |
Control |
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64 KB |
4 KB |
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D-MEM |
2 way |
<![if ! IE]> <![endif]>Delayed |
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<![if ! IE]> <![endif]>Delayed |
Core Memory Protection Unit |
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64 DATA |
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Concentrator_1 |
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HSM |
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(CMPU) |
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E2E ECC |
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e200 z420n3 – 180 MHz |
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Nexus3p |
dual issue |
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Main Core_0 |
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VLE |
EFPU2 |
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<![if ! IE]> <![endif]>Checkers |
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I-Cache |
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Control |
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D-MEM |
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With |
<![if ! IE]> <![endif]>Redundancy |
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8 KB |
Unified |
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2 way |
Backdoor |
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Interface |
<![if ! IE]> <![endif]>with |
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Control |
E2E ECC |
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64 KB |
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Instruction |
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Periph. |
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Periph. |
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PRAMC_2 |
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PRAMC_3 |
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PFLASHC_1 |
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256 Page Line |
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Bridge 2 |
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Bridge 1 |
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Set-Associative Prefetch |
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FLASH |
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E2E ECC |
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E2E ECC |
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ECC |
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ECC |
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Buffers |
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4 MB |
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32 |
ADD |
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EEPROM |
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32 DATA |
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64 DATA |
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Non Volatile Memory |
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Peripheral |
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Peripheral |
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SRAM |
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SRAM |
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Array 2 |
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Array 3 |
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Multiple RWW partitions |
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Cluster 2 |
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Cluster 1 |
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256 KB |
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128 KB |
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DS11620 Rev 7 |
9/153 |
Description |
SPC584Cx, SPC58ECx |
|
|
Figure 2. Periphery allocation
%&78B
67'%<B&78B
H0,26B
(7+(51(7B
6$5B$'&B ELWB
6$5B$'&B ELWB67'%<
6$5B$'&B ELWB%
)/(;5$<B
, &B
'63,B
/,1)OH['B
&$1B68%B B0(66$*(B5$0
&$1B68%B B0B&$1B
&&&8
+60
'76
-'&
67&8
-7$*0
0(08
,0$
&5&B
'0$08;B
3,7B
57&$3,
:.38
0&B3&8
30&B',*
0&B5*0
5&26&B',*
5& .B',*
26&B',*
26& .B',*
3//B',*
&08B B3// B;26&B,5&26&
0&B&*0
0&B0(
6,8/
)/$6+B
)/$6+B$/7B
3$66
66&0
<![endif]>3%5,'*(B ± 3HULSKHUDO &OXVWHU
3%5,'*(B
;%$5B
;%,&B&RQFHQWUDWRUB
6038B
;%,&B
3&0B
3)/$6+B
6(0
,17&B
6:7B
670B
H'0$B
35$0B
7'0B
H0,26B
6$5B$'&B ELWB
'63,B
/,1)OH['B
&$1B68%B B0(66$*(B5$0
&$1B68%B B0B&$1B
)&&8
&5&B
'0$08;B
3,7B
&08B B&25(B;%$5
&08B B+3%0
&08B B3%5,'*(
&08B B6$5$'&
&08B B)%5,'*(
&08B B(0,26
&08B B3)%5,'*(
6,3,B
/)$67B
3%5,'*(B
<![if ! IE]><![endif]>3%5,'*(B ± 3HULSKHUDO &OXVWHU
Note:In this diagram, ON-platform modules are shown in orange color and OFF-platform modules are shown in blue color.
10/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
Description |
|
|
2.3Features overview
On-chip modules within SPC584Cx and SPC58ECx include the following features:
•Two main CPUs, dual issue, 32-bit CPU core complexes (e200z4).
–Power Architecture embedded specification compliance
–Instruction set enhancement allowing variable length encoding (VLE), encoding a mix of 16-bit and 32-bit instructions, for code size footprint reduction
–Single-precision floating point operations
–64 KB local data RAM for Core_0 and Core_2
–8 KB I-Cache and 4 KB D-Cache for Core_0 and Core_2
•4224 KB (4096 KB code flash + 128 KB data flash) on-chip flash memory
–Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
•176 KB HSM dedicated flash memory (144 KB code + 32 KB data)
•384 KB on-chip general-purpose SRAM (+ 128 KB local data RAM: 64 KB included in each CPU)
•Multi channel direct memory access controllers
–64 eDMA channels
•One interrupt controller (INTC)
•Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell
•Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
•Hardware security module (HSM) with HW cryptographic co-processor
•System integration unit lite (SIUL)
•BootassistFlash(BAF)supportsfactoryprogrammingusingaserialbootloadthroughthe asynchronous CAN or LIN/UART.
•Hardware support for safety ASIL-B level related applications
•Enhanced modular IO subsystem (eMIOS): up to 64 (2 x 32) timed I/O channels with 16-bit counter resolution
–Buffered updates
–Support for shifted PWM outputs to minimize occurrence of concurrent edges
–Supports configurable trigger outputs for ADC conversion for synchronization to channel output waveforms
–Shared or independent time bases
–DMA transfer support available
•Body cross triggering unit (BCTU)
–Triggers ADC conversions from any eMIOS channel
–Triggers ADC conversions from up to 2 dedicated PIT_RTIs
–One event configuration register dedicated to each timer event allows to define the corresponding ADC channel
–Synchronization with ADC to avoid collision
DS11620 Rev 7 |
11/153 |
Description |
SPC584Cx, SPC58ECx |
|
|
•Enhanced analog-to-digital converter system with:
–Three independent fast 12-bit SAR analog converters
–One supervisor 12-bit SAR analog converter
–One 10-bit SAR analog converter with STDBY mode support
•Eight deserial serial peripheral interface (DSPI) modules
•Eighteen LIN and UART communication interface (LINFlexD) modules
–LINFlexD_0 is a Master/Slave
–All others are Masters
•Eight modular controller area network (MCAN) modules, all supporting flexible data rate (ISO CAN-FD compliant)
•Dual-channel FlexRay controller
•One ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008
–IEEE 1588-2008 Time stamping (internal 64-bit time stamp)
–IEEE 802.1AS and IEEE 802.1Qav (AVB-Feature)
–IEEE 802.1Q VLAN tag detection
–IPv4 and IPv6 checksum modules
•Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard.
•Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1 and IEEE 1149.7), 2-pin JTAG interface.
•Standby power domain with smart wake-up sequence
12/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
Package pinouts and signal descriptions |
|
|
3Package pinouts and signal descriptions
Refer to the SPC584Cx and SPC58ECx IO_ Definition document.
It includes the following sections:
1.Package pinouts
2.Pin descriptions
a)Power supply and reference voltage pins
b)System pins
c)LVDS pins
d)Generic pins
DS11620 Rev 7 |
13/153 |
Electrical characteristics |
SPC584Cx, SPC58ECx |
|
|
4Electrical characteristics
4.1Introduction
The present document contains the target Electrical Specification for the 40 nm family 32-bit MCU SPC584Cx and SPC58ECx products.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” (Controller Characteristics) is included in the “Symbol” column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” (System Requirement) is included in the “Symbol” column.
The electrical parameters shown in this document are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 3 are used and the parameters are tagged accordingly in the tables where appropriate.
|
Table 3. Parameter classifications |
Classification tag |
Tag description |
|
|
P |
Those parameters are guaranteed during production testing on each individual device. |
|
|
C |
Those parameters are achieved by the design characterization by measuring a statistically |
|
relevant sample size across process variations. |
|
|
T |
Those parameters are achieved by design validation on a small sample size from typical |
|
devices. |
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|
D |
Those parameters are derived mainly from simulations. |
|
|
14/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
Electrical characteristics |
|
|
4.2Absolute maximum ratings
Table 4 describes the maximum ratings for the device.Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Stress beyond the listed maxima, even momentarily, may affect device reliability or cause permanent damage to the device.
Table 4. Absolute maximum ratings
Symbol |
|
C |
Parameter |
Conditions |
|
Value |
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Unit |
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Min |
Typ |
Max |
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Core voltage |
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VDD_LV |
SR |
D |
operating life |
— |
–0.3 |
— |
1.4 |
V |
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range(1) |
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VDD_HV_IO_MAIN |
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VDD_HV_IO_FLEX |
SR |
D |
I/O supply |
— |
–0.3 |
— |
6.0 |
V |
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VDD_HV_OSC |
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voltage(2) |
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VDD_HV_FLA |
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VSS_HV_ADV |
SR |
D |
ADC ground |
Reference to |
–0.3 |
— |
0.3 |
V |
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voltage |
digital ground |
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VDD_HV_ADV |
SR |
D |
ADC Supply |
Reference to |
–0.3 |
— |
6.0 |
V |
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(2) |
VSS_HV_ADV |
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voltage |
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SAR ADC |
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VSS_HV_ADR_S |
SR |
D |
ground |
— |
–0.3 |
— |
0.3 |
V |
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reference |
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VDD_HV_ADR_S |
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SAR ADC |
Reference to |
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SR |
D |
voltage(2) |
–0.3 |
— |
6.0 |
V |
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VSS_HV_ADR_S |
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reference |
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VSS-VSS_HV_ADR_S |
SR |
D |
VSS_HV_ADR_S |
— |
–0.3 |
— |
0.3 |
V |
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differential |
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voltage |
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VSS-VSS_HV_ADV |
SR |
D |
VSS_HV_ADV |
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differential |
— |
–0.3 |
— |
0.3 |
V |
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voltage |
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— |
–0.3 |
— |
6.0 |
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VIN |
SR |
D |
I/Oinputvoltage |
Relative to Vss |
–0.3 |
— |
— |
V |
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(2)(3) (4) |
Relative to |
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range |
|
|
|
|
||
|
|
|
|
VDD_HV_IO and |
— |
— |
0.3 |
|
|
|
|
|
|
VDD_HV_ADV |
|
|
|
|
|
T |
SR |
D |
Digital Inputpad |
— |
— |
— |
1 |
ms |
|
TRIN |
|
|
transition time(5) |
|
|
|
|
|
|
|
|
|
Maximum DC |
|
|
|
|
|
|
|
|
|
injection current |
|
|
|
|
|
|
IINJ |
SR |
T |
for each |
— |
–5 |
— |
5 |
mA |
|
|
|
|
analog/digital |
|
|
|
|
|
|
|
|
|
PAD(6) |
|
|
|
|
|
DS11620 Rev 7 |
15/153 |
Electrical characteristics |
|
|
|
|
|
SPC584Cx, SPC58ECx |
||||
|
|
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|
|
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|
|
|
|
|
|
|
Table 4. Absolute maximum ratings (continued) |
|
|
|
||||
Symbol |
|
|
C |
Parameter |
Conditions |
|
|
Value |
|
Unit |
|
|
|
|
|
|
|||||
|
|
Min |
|
Typ |
Max |
|||||
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Maximum non- |
|
|
|
|
|
|
|
|
|
|
operating |
|
|
|
|
|
|
TSTG |
SR |
|
T |
Storage |
— |
–55 |
|
— |
125 |
°C |
|
|
|
|
temperature |
|
|
|
|
|
|
|
|
|
|
range |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Maximum non- |
|
|
|
|
|
|
|
|
|
|
operating |
|
|
|
|
|
|
TPAS |
SR |
|
C |
temperature |
— |
–55 |
|
— |
150(7) |
°C |
|
|
|
|
during passive |
|
|
|
|
|
|
|
|
|
|
lifetime |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Maximum |
Nosupply;storage |
|
|
|
|
|
|
|
|
|
storage time, |
|
|
|
|
|
|
T |
SR |
|
— |
assembled part |
temperature in |
— |
|
— |
20 |
years |
STORAGE |
|
|
|
programmed in |
range –40 °C to |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
ECU |
60 °C |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Maximumsolder |
|
|
|
|
|
|
TSDR |
SR |
|
T |
temperature Pb- |
— |
— |
|
— |
260 |
°C |
|
|
|
|
free packaged(8) |
|
|
|
|
|
|
|
|
|
|
Moisture |
|
|
|
|
|
|
MSL |
SR |
|
T |
sensitivity |
— |
— |
|
— |
3 |
— |
|
|
|
|
level(9) |
|
|
|
|
|
|
|
|
|
|
|
Typical range for |
|
|
|
|
|
|
|
|
|
Maximum |
X-rays source |
|
|
|
|
|
|
|
|
|
during |
|
|
|
|
|
|
TXRAY dose |
SR |
|
T |
cumulated |
— |
|
— |
1 |
grey |
|
|
inspection:80 ÷ |
|
||||||||
|
|
|
|
XRAY dose |
130 KV; 20 ÷ |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
50 μA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1.VDD_LV: allowed 1.335 V - 1.400 V for 60 seconds cumulative time at the given temperature profile. Remaining time allowed 1.260 V - 1.335 V for 10 hours cumulative time at the given temperature profile. Remaining time as defined in Section 4.3: Operating conditions.
2.VDD_HV: allowed 5.5 V – 6.0 V for 60 seconds cumulative time at the given temperature profile, for 10 hours cumulative time with the device in reset at the given temperature profile. Remaining time as defined in Section 4.3: Operating conditions.
3.The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal calculations.
4.Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameter IINJ).
5.This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum limits to the transition time.
6.The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in
Section 4.8.3: I/O pad current specifications.
7.175°C are allowed for limited time. Mission profile with passive lifetime temperature >150°C have to be evaluated by ST to confirm that are granted by product qualification.
8.Solder profile per IPC/JEDEC J-STD-020D.
9.Moisture sensitivity per JDEC test method A112.
16/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
Electrical characteristics |
|
|
4.3Operating conditions
Table 5 describes the operating conditions for the device, and for which all the specifications in the data sheet are valid, except where explicitly noted. The device operating conditions must not be exceeded or the functionality of the device is not guaranteed.
Table 5. Operating conditions
Symbol |
|
C |
Parameter |
Conditions |
|
|
Value(1) |
|
Unit |
|
Min |
|
Typ |
Max |
|||||
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
FSYS(2) |
|
|
Operating |
|
|
|
|
|
|
SR |
P |
system clock |
— |
— |
|
— |
180 |
MHz |
|
|
|
|
frequency(3) |
|
|
|
|
|
|
TA_125 Grade(4) |
|
|
Operating |
|
|
|
|
|
|
SR |
D |
Ambient |
— |
–40 |
|
— |
125 |
°C |
|
|
|
|
temperature |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TJ_125 Grade(4) |
|
|
Junction |
|
|
|
|
|
|
SR |
P |
temperature |
TA = 125 °C |
–40 |
|
— |
150 |
°C |
|
|
|
|
under bias |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TA_105 Grade(4) |
|
|
Ambient |
|
|
|
|
|
|
SR |
D |
temperature |
— |
–40 |
|
— |
105 |
°C |
|
|
|
|
under bias |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TJ_105 Grade(4) |
|
|
Operating |
|
|
|
|
|
|
SR |
D |
Junction |
TA = 105 °C |
–40 |
|
— |
130 |
°C |
|
|
|
|
temperature |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VDD_LV |
SR |
P |
Core supply |
— |
1.14 |
|
1.20 |
1.26(6) (7) |
V |
(5) |
|
||||||||
|
|
|
voltage |
|
|
|
|
|
|
VDD_HV_IO_MAIN |
|
|
|
|
|
|
|
|
|
VDD_HV_IO_FLEX |
SR |
P |
IO supply |
— |
3.0 |
|
— |
5.5 |
V |
VDD_HV_FLA |
|
|
voltage |
|
|
|
|
|
|
VDD_HV_OSC |
|
|
|
|
|
|
|
|
|
VDD_HV_ADV |
SR |
P |
ADC supply |
— |
3.0 |
|
— |
5.5 |
V |
voltage |
|
||||||||
VSS_HV_ADV- |
|
|
ADC ground |
|
|
|
|
|
|
SR |
D |
differential |
— |
–25 |
|
— |
25 |
mV |
|
VSS |
|
||||||||
|
|
voltage |
|
|
|
|
|
|
|
VDD_HV_ADR_S |
|
|
SAR ADC |
|
|
|
|
|
|
SR |
P |
reference |
— |
3.0 |
|
— |
5.5 |
V |
|
|
|
|
voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VDD_HV_ADR_S- |
|
|
SAR ADC |
|
|
|
|
|
|
SR |
D |
reference |
— |
— |
|
— |
25 |
mV |
|
VDD_HV_ADV |
|
|
differential |
|
|
|
|
|
|
|
|
|
voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SAR ADC |
|
|
|
|
|
|
VSS_HV_ADR_S |
SR |
P |
ground |
— |
|
VSS_HV_ADV |
|
V |
|
reference |
|
|
|||||||
|
|
|
voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DS11620 Rev 7 |
17/153 |
Electrical characteristics |
|
|
|
SPC584Cx, SPC58ECx |
||||
|
|
|
|
|
|
|
|
|
|
|
|
Table 5. Operating conditions (continued) |
|
|
|
||
Symbol |
|
C |
Parameter |
Conditions |
|
Value(1) |
|
Unit |
|
Min |
Typ |
Max |
|||||
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
VSS_HV_ADR_S- |
SR |
D |
VSS_HV_ADR_S |
— |
–25 |
— |
25 |
mV |
differential |
||||||||
VSS_HV_ADV |
|
|
voltage |
|
|
|
|
|
|
|
|
Slew rate on |
|
|
|
|
|
VRAMP_HV |
SR |
D |
HV power |
— |
— |
— |
100 |
V/ms |
|
|
|
supply |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VIN |
SR |
P |
I/O input |
— |
0 |
— |
5.5 |
V |
voltage range |
||||||||
|
|
|
Injection |
|
|
|
|
|
|
|
|
current (per |
Digital pins and |
|
|
|
|
IINJ1 |
SR |
T |
pin) without |
–3.0 |
— |
3.0 |
mA |
|
performance |
analog pins |
|||||||
|
|
|
degradation(8) |
|
|
|
|
|
|
|
|
(9) (10) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Dynamic |
|
|
|
|
|
|
|
|
Injection |
|
|
|
|
|
IINJ2 |
|
|
current (per |
Digital pins and |
|
|
|
|
SR |
D |
pin) with |
analog pins |
–10 |
— |
10 |
mA |
|
|
|
|
performance |
|
|
|
|
|
|
|
|
degradation(10) |
|
|
|
|
|
|
|
|
(11) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1.The ranges in this table are design targets and actual data may vary in the given range.
2.The maximum number of PRAM wait states has to be configured accordingly to the system clock frequency. Refer to
Table 6.
3.Maximum operating frequency is applicable to the cores and platform of the device. See the Clock Chapter in the Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the device.
4.In order to evaluate the actual difference between ambient and junction temperatures in the application, refer to
Section 5.6: Package thermal characteristics.
5.Core voltage as measured on device pin to guarantee published silicon performance.
6.Core voltage can exceed 1.26 V with the limitations provided in Section 4.2: Absolute maximum ratings, provided that HVD134_C monitor reset is disabled.
7.1.260 V - 1.290 V range allowed periodically for supply with sinusoidal shape and average supply value below or equal to 1.236 V at the given temperature profile.
8.Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See Section 4.2: Absolute maximum ratings for maximum input current for reliability requirements.
9.The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pins is above the supply rail, current will be injected through the clamp diode to the supply rails. For external RC network calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.
10.The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in
Section 4.8.3: I/O pad current specifications.
11.Positive and negative Dynamic current injection pulses are allowed up to this limit. I/O and ADC specifications are not granted. See the dedicated chapters for the different specification limits. See the Absolute Maximum Ratings table for maximum input current for reliability requirements. Refer to the following pulses definitions: Pulse1 (ISO 7637-2:2011), Pulse 2a(ISO 7637-2:2011 5.6.2), Pulse 3a (ISO 7637-2:2011 5.6.3), Pulse 3b (ISO 7637-2:2011 5.6.3).
18/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
Electrical characteristics |
|
|
|
|
|
Table 6. PRAM wait states configuration |
|
|
PRAMC WS |
Clock Frequency (MHz) |
|
|
|
|
1 |
< 180 |
|
|
|
|
0 |
< 120 |
|
|
|
4.3.1Power domains and power up/down sequencing
The following table shows the constraints and relationships for the different power domains. Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and column is reporting ‘ok’. This limitation is valid during power-up and power-down phases, as well as during normal device operation.
Table 7. Device supply relation during power-up/power-down sequence
|
|
|
|
Supply2 |
|
|
|
|
|
|
|
|
|
|
|
VDD_LV |
VDD_HV_IO_FLEX |
VDD_HV_IO_MAIN |
VDD_HV_ADV |
VDD_HV_ADR |
|
|
VDD_HV_FLA |
||||
|
|
|
|
VDD_HV_OSC |
|
|
|
VDD_HV_IO_FLEX |
ok |
|
not allowed |
ok |
ok |
|
VDD_HV_IO_MAIN |
|
|
|
|
|
<![if ! IE]> <![endif]>Supply1 |
VDD_HV_FLA |
ok |
ok |
not allowed |
ok |
ok |
VDD_HV_ADV |
ok |
ok |
|
ok |
||
|
VDD_HV_OSC |
|
|
|
|
|
|
|
|
|
|
|
|
|
VDD_HV_ADR |
ok |
ok |
not allowed |
not allowed |
|
During power-up, all functional terminals are maintained in a known state as described in the device pinout Microsoft Excel file attached to the IO_Definition document.
DS11620 Rev 7 |
19/153 |
Electrical characteristics |
SPC584Cx, SPC58ECx |
|
|
4.4Electrostatic discharge (ESD)
The following table describes the ESD ratings of the device:
•All ESD testing are in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits,
•Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification requirements, which include the complete DC parametric and functional testing at room temperature and hot temperature, maximum DC parametric variation within 10% of maximum specification”.
Table 8. ESD ratings
Parameter |
C |
Conditions |
Value |
Unit |
|
|
|
|
|
|
|
ESD for Human Body Model (HBM)(1) |
T |
All pins |
2000 |
V |
|
ESD for field induced Charged Device Model (CDM)(2) |
T |
All pins |
500 |
V |
|
|
|
|
|
||
T |
Corner Pins |
750 |
V |
||
|
|||||
|
|
|
|
|
1.This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing.
2.This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level.
20/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
Electrical characteristics |
|
|
4.5Electromagnetic compatibility characteristics
EMC measurements at IC-level IEC standards are available from STMicroelectronics on request.
DS11620 Rev 7 |
21/153 |
Electrical characteristics |
SPC584Cx, SPC58ECx |
|
|
4.6Temperature profile
The device is qualified in accordance to AEC-Q100 Grade1 requirements, such as HTOL 1,000 h and HTDR 1,000 hrs, TJ = 150 °C.
Mission profile exceeding AEC-Q100 Grade 1, and with junction Temperature equal to or lower than 150 °C have to be evaluated by ST to confirm that are covered by product qualification. Contact your STMicroelectronics Sales representative for validation.
22/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
Electrical characteristics |
|
|
4.7Device consumption
Table 9. Device consumption
Symbol |
|
C |
Parameter |
Conditions |
|
Value(1) |
|
Unit |
||
|
Min |
Typ |
Max |
|||||||
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
||
|
|
C |
|
TJ = 40 °C |
— |
— |
14 |
|
||
|
|
D |
|
TJ = 25 °C |
— |
— |
10 |
|
||
IDD_LKG(2),(3) |
CC |
D |
Leakagecurrentonthe |
TJ = 55 °C |
— |
— |
20 |
mA |
||
D |
VDD_LV supply |
TJ = 95 °C |
— |
— |
50 |
|||||
|
|
|
||||||||
|
|
D |
|
TJ = 120 °C |
— |
— |
90 |
|
||
|
|
P |
|
TJ = 150 °C |
— |
— |
180 |
|
||
|
|
|
Dynamic current on |
|
|
|
|
|
|
|
(3) |
CC |
P |
the VDD_LV supply, |
|
— |
— |
— |
210 |
mA |
|
IDD_LV |
very high consumption |
|
||||||||
|
|
|
profile(4) |
|
|
|
|
|
|
|
IDD_HV |
CC |
P |
Total current on the |
fMAX |
— |
— |
64 |
mA |
||
VDD_HV supply(4) |
||||||||||
|
|
|
Dynamic current on |
|
|
|
|
|
|
|
IDD_LV_GW |
CC |
T |
the VDD_LV supply, |
|
— |
— |
— |
170 |
mA |
|
|
|
|
gateway profile(5) |
|
|
|
|
|
|
|
IDD_HV_GW |
|
|
Dynamic current on |
|
|
|
|
|
|
|
CC |
T |
the VDD_HV supply, |
|
— |
— |
— |
37 |
mA |
||
|
|
|
gateway profile(5) |
|
|
|
|
|
|
|
IDD_LV_BCM |
|
|
Dynamic current on |
|
|
|
|
|
|
|
CC |
T |
the VDD_LV supply, |
|
— |
— |
— |
150 |
mA |
||
|
|
|
body profile(6) |
|
|
|
|
|
|
|
IDD_HV_BCM |
|
|
Dynamic current on |
|
|
|
|
|
|
|
CC |
T |
the VDD_HV supply, |
|
— |
— |
— |
44 |
mA |
||
|
|
|
body profile(6) |
|
|
|
|
|
|
|
I |
CC |
T |
Main Core dynamic |
f |
MAX |
— |
— |
50 |
mA |
|
DD_MAIN_CORE_AC |
|
|
(7) |
|
|
|
|
|
||
|
|
|
current |
|
|
|
|
|
|
|
I |
CC |
T |
HSMplatformdynamic |
f /2 |
— |
— |
20 |
mA |
||
DD_HSM_AC |
|
|
operating current(8) |
MAX |
|
|
|
|
||
|
|
|
Dynamic current on |
|
|
|
|
|
|
|
(9) |
CC |
T |
the VDD_LV supply |
|
— |
— |
71 |
100 |
mA |
|
IDDHALT |
+Total current on the |
|
||||||||
|
|
|
VDD_HV supply |
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|
|
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|
|
|
Dynamic current on |
|
|
|
|
|
|
|
(10) |
CC |
T |
the VDD_LV supply |
|
— |
— |
15 |
30 |
mA |
|
IDDSTOP |
+Total current on the |
|
||||||||
|
|
|
VDD_HV supply |
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DS11620 Rev 7 |
23/153 |
Electrical characteristics |
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SPC584Cx, SPC58ECx |
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Table 9. Device consumption (continued) |
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|
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|
||||
Symbol |
|
|
C |
Parameter |
Conditions |
|
|
|
Value(1) |
|
Unit |
|
|
|
Min |
|
Typ |
Max |
|||||
|
|
|
|
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|
|||
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|
D |
|
TJ = 25 °C |
|
— |
|
85 |
160 |
|
|
|
|
C |
Total standby mode |
TJ = 40 °C |
|
— |
|
— |
250 |
µA |
|
|
|
|
current on VDD_LV and |
|
|
|
|
|
|
|
IDDSTBY8 |
CC |
|
D |
TJ = 55 °C |
|
— |
|
— |
370 |
|
|
|
VDD_HV supply, 8 KB |
|
|
|
|||||||
|
|
|
D |
TJ = 120 °C |
|
— |
|
1.2 |
2.2 |
|
|
|
|
|
RAM(11) |
|
|
mA |
|||||
|
|
|
P |
|
TJ = 150 °C |
|
— |
|
2.9 |
5.0 |
|
|
|
|
|
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|
|
|||||
|
|
|
D |
|
TJ = 25 °C |
|
— |
|
100 |
180 |
|
|
|
|
C |
Total standby mode |
TJ = 40 °C |
|
— |
|
— |
270 |
µA |
|
|
|
|
current on VDD_LV and |
|
|
|
|
|
|
|
IDDSTBY32 |
CC |
|
D |
TJ = 55 °C |
|
— |
|
— |
410 |
|
|
|
VDD_HV supply, 32 KB |
|
|
|
|||||||
|
|
|
D |
RAM(11) |
TJ = 120 °C |
|
— |
|
— |
2.4 |
mA |
|
|
|
P |
|
TJ = 150 °C |
|
— |
|
— |
5.5 |
|
|
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|
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|
|||||
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D |
|
TJ = 25 °C |
|
— |
|
150 |
250 |
|
|
|
|
C |
Total standby mode |
TJ = 40 °C |
|
— |
|
— |
390 |
µA |
|
|
|
|
current on VDD_LV and |
|
|
|
|
|
|
|
IDDSTBY256 |
CC |
|
D |
TJ = 55 °C |
|
— |
|
— |
590 |
|
|
|
VDD_HV supply, |
|
|
|
|||||||
|
|
|
D |
256 KB RAM(11) |
TJ = 120 °C |
|
— |
|
2.0 |
3.5 |
mA |
|
|
|
P |
|
TJ = 150 °C |
|
— |
|
5.1 |
8 |
|
|
|
|
|
SSWU running over all |
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|
|
IDDSSWU1 |
|
|
|
STANDBY period with |
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|
|
|
|
CC |
|
D |
OPC/TU commands |
TJ = 40 °C |
|
— |
|
1.0 |
3.5 |
mA |
|
|
|
|
|
execution and keeping |
|
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|
|
ADC off(12) |
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SSWU running over all |
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STANDBY period with |
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|
|
IDDSSWU2 |
CC |
|
D |
OPC/TU/ADC |
TJ = 40 °C |
|
— |
|
3.5 |
5.0 |
mA |
|
commands execution |
|
|
||||||||
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|
|
and keeping ADC |
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on(13) |
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|
|
1.The ranges in this table are design targets and actual data may vary in the given range.
2.The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered, and they are computed in the dynamic IDD_LV and IDD_HV parameters.
3.IDD_LKG (leakage current) and IDD_LV (dynamic current) are reported as separate parameters, to give an indication of the consumption contributors. The tests used in validation, characterization and production are verifying that the total
consumption (leakage+dynamic) is lower or equal to the sum of the maximum values provided (IDD_LKG + IDD_LV). The two parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and the software profile used.
4.Use case: 2 x e200Z4 @180 MHz, HSM @90 MHz, all IPs clock enabled, Flash access with prefetch disabled, Flash consumption includes parallel read and program/erase, all SARADC in continuous conversion, DMAcontinuously triggered by ADC conversion, 4 DSPI / 8 CAN / 2 LINFlex and 2 DSPI transmitting, 2 x EMIOS running (8 channels in OPWMT mode), FIRC, SIRC, FXOSC, PLL0-1 running. The switching activity estimated for dynamic consumption does not include I/O toggling, which is highly dependent on the application. Details of the software configuration are available separately. The total device consumption is IDD_LV + IDD_HV + IDD_LKG for the selected temperature.
5.Gateway use case: Two cores running at 160 MHz, DMA, PLL, FLASH read only 25%, 8xCAN, 1xEthernet, HSM, 2xSARADC.
6.BCM use case: One Core running at 160 MHz, no lockstep no, DMA, PLL, FLASH read only 25%, 2xCAN, HSM, 4xSARADC.
24/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
Electrical characteristics |
|
|
7.Dynamic consumption of one core, including the dedicated I/D-caches and I/D-MEMS contribution.
8.Dynamic consumption of the HSM module, including the dedicated memories, during the execution of Electronic Code Book crypto algorithm on 1 block of 16 byte of shared RAM.
9.Flash in Low Power. Sysclk at 160 MHz, PLL0_PHI at 160 MHz, XTAL at 40 MHz, FIRC 16 MHz ON, RCOSC1M off. FlexCAN: instances: 0, 1, 2, 3, 4, 5, 6, 7 ON (configured but no reception or transmission), Ethernet ON (configured but no reception or transmission), ADC ON (continuously converting). All others IPs clock-gated.
10.Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power down mode.
11.STANDBY mode: device configured for minimum consumption, RC16 MHz off, RC1 MHz on, OSC32K off, SSWU off.
12.SSWU1 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC off. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size and temperature.
13.SSWU2 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC on in continuous
conversion. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size and temperature.
DS11620 Rev 7 |
25/153 |
Electrical characteristics |
SPC584Cx, SPC58ECx |
|
|
4.8I/O pad specification
The following table describes the different pad type configurations.
|
|
Table 10. I/O pad specification descriptions |
|
|
Pad type |
Description |
|
|
|
||
Weak configuration |
Provides a good compromise between transition time and low electromagnetic emission. |
||
|
|
||
Medium configuration |
Provides transition fast enough for the serial communication channels with controlled |
||
|
|
current to reduce electromagnetic emission. |
|
Strong configuration |
Provides fast transition speed; used for fast interface. |
||
|
|
|
|
|
Very strong |
Provides maximum speed and controlled symmetric behavior for rise and fall transition. |
|
|
Used for fast interface including Ethernet and FlexRay interfaces requiring fine control of |
||
configuration |
|||
rising/falling edge jitter. |
|||
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|
||
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Differential |
A few pads provide differential capability providing very fast interface together with good |
|
configuration |
EMC performances. |
||
|
|
||
Input only pads |
These low input leakage pads are associated with the ADC channels. |
||
|
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|
|
These pads (LP pads) are active during STANDBY. They are configured in CMOS level |
|
|
|
logic and this configuration cannot be changed. Moreover, when the device enters the |
|
|
|
STANDBY mode, the pad-keeper feature is activated for LP pads. It means that: |
|
Standby pads |
– if the pad voltage level is above the pad keeper high threshold, a weak pull-up resistor |
||
is automatically enabled |
|||
|
|
||
|
|
– if the pad voltage level is below the pad keeper low threshold, a weak pull-down resistor |
|
|
|
is automatically enabled. |
|
|
|
For the pad-keeper high/low thresholds please consider (VDD_HV_IO_MAIN / 2) +/-20%. |
|
|
|
|
|
Note: |
Each I/O pin on the device supports specific drive configurations. See the signal description |
||
|
table in the device reference manual for the available drive configurations for each I/O pin. |
||
|
PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for |
||
|
each IO segment. |
||
|
Logic level is configurable in running mode while it is CMOS not-configurable in STANDBY |
||
|
for LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be |
||
|
configured as CMOS also in running mode in order to prevent device wrong behavior in |
||
|
STANDBY. |
||
4.8.1 |
I/O input DC characteristics |
||
|
The following table provides input DC electrical characteristics, as described in Figure 3. |
26/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
|
Electrical characteristics |
|||||
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Figure 3. I/O input electrical characteristics |
||||
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||
VIN |
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VDD |
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VIH |
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VHYS |
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VIL |
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VINTERNAL |
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(SIUL register) |
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Table 11. I/O input electrical characteristics
|
|
Symbol |
|
C |
Parameter |
Conditions |
|
|
Value |
|
Unit |
|
|
|
|
|
|
|
|
||||||
|
|
|
Min |
|
Typ |
Max |
||||||
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TTL |
|
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|
||
V |
ihttl |
SR |
P |
Input high level |
— |
2 |
|
— |
VDD_HV_IO |
V |
||
|
|
|
|
|
TTL |
|
|
|
|
+ 0.3 |
|
|
|
Vilttl |
SR |
P |
Input low level |
— |
–0.3 |
|
— |
0.8 |
V |
||
|
TTL |
|
||||||||||
Vhysttl |
CC |
C |
Inputhysteresis |
— |
0.3 |
|
— |
— |
V |
|||
TTL |
|
|||||||||||
|
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|
CMOS |
|
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|
|
|
|
|
|
|
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|
|
|
V |
ihcmos |
SR |
P |
Input high level |
— |
0.65 * V |
DD |
— |
VDD_HV_IO |
V |
||
|
|
|
CMOS |
|
|
|
+ 0.3 |
|
||||
V |
ilcmos |
SR |
P |
Input low level |
— |
–0.3 |
|
— |
0.35 * V |
V |
||
|
|
|
|
CMOS |
|
|
|
|
DD |
|
||
Vhyscmos |
CC |
C |
Inputhysteresis |
— |
0.10 * VDD |
— |
— |
V |
||||
CMOS |
||||||||||||
|
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COMMON |
|
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|
|
ILKG |
CC |
P |
Pad input |
INPUT-ONLY pads |
— |
|
— |
200 |
nA |
||
|
leakage |
TJ = 150 °C |
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
||
|
ILKG |
CC |
P |
Pad input |
STRONG pads |
— |
|
— |
1,000 |
nA |
||
|
leakage |
TJ = 150 °C |
|
|||||||||
|
|
|
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|
|
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|
||
|
ILKG |
CC |
P |
Pad input |
VERY STRONG pads, |
— |
|
— |
1,000 |
nA |
||
|
leakage |
TJ = 150 °C |
|
|||||||||
|
|
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|
DS11620 Rev 7 |
27/153 |
Electrical characteristics |
|
|
SPC584Cx, SPC58ECx |
||||||
|
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|
|
|
|
Table 11. I/O input electrical characteristics (continued) |
|
|
||||
Symbol |
|
C |
|
Parameter |
Conditions |
|
Value |
|
Unit |
|
|
|
|
|
|||||
|
|
Min |
Typ |
Max |
|||||
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|
|||
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|
|
CP1 |
CC |
D |
|
Pad |
— |
— |
— |
10 |
pF |
|
capacitance |
||||||||
Vdrift |
|
|
|
Input Vil/Vih |
In a 1 ms period, with a |
|
|
|
|
CC |
D |
|
temperature |
temperature variation |
— |
— |
100 |
mV |
|
|
|
|
|
drift |
<30 °C |
|
|
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|
|
|
|
WFI |
SR |
C |
|
Wakeup input |
— |
— |
— |
20 |
ns |
|
filtered pulse(1) |
||||||||
|
|
|
|
Wakeup input |
|
|
|
|
|
WNFI |
SR |
C |
|
not filtered |
— |
400 |
— |
— |
ns |
|
|
|
|
pulse(1) |
|
|
|
|
|
1.In the range from WFI (max) to WNFI (min), pulses can be filtered or not filtered, according to operating temperature and voltage. Refer to the device pinout IO definition excel file for the list of pins supporting the wakeup filter feature.
Table 12. I/O pull-up/pull-down electrical characteristics
Symbol |
|
C |
Parameter |
Conditions |
|
Value |
|
Unit |
|
|
|
|
|
||||||
|
Min |
Typ |
Max |
||||||
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
T |
Weak pull-up |
VIN = 1.1 V(1) |
— |
— |
130 |
μA |
|
IWPU |
CC |
P |
current |
VIN = 0.69 * |
15 |
— |
— |
||
|
|
absolute value |
VDD_HV_IO(2) |
|
|||||
RWPU |
CC |
D |
Weak Pull-up |
VDD_HV_IO = 5.0 V ± |
33 |
— |
93 |
KΩ |
|
resistance |
10% |
||||||||
RWPU |
CC |
D |
Weak Pull-up |
VDD_HV_IO = 3.3 V ± |
19 |
— |
62 |
KΩ |
|
resistance |
10% |
||||||||
|
|
T |
Weak pull- |
VIN = 0.69 * |
— |
— |
130 |
μA |
|
|
|
|
VDD_HV_IO(1) |
|
|
|
|
||
IWPD |
CC |
|
down current |
|
|
|
|
|
|
|
VIN = 0.9 V(2) |
|
|
|
|
||||
|
|
P |
absolute value |
15 |
— |
— |
|
||
|
|
|
|
|
|
|
|
|
|
RWPD |
|
|
Weak Pull- |
VDD_HV_IO = 5.0 V ± |
|
|
|
|
|
CC |
D |
down |
29 |
— |
60 |
KΩ |
|||
10% |
|||||||||
|
|
|
resistance |
|
|
|
|
|
|
|
|
|
Weak Pull- |
VDD_HV_IO = 3.3 V ± |
19 |
— |
60 |
KΩ |
|
RWPD |
CC |
D |
down |
||||||
10% |
|||||||||
|
|
|
resistance |
|
|
|
|
|
1.Maximum current when forcing a change in the pin level opposite to the pull configuration.
2.Minimum current when keeping the same pin level state than the pull configuration.
Note: |
When the device enters into standby mode, the LP pads have the input buffer switched-on. |
|
As a consequence, if the pad input voltage VIN is VSS<VIN<VDD_HV, an additional |
|
consumption can be measured in the VDD_HV domain. The highest consumption can be |
|
seen around mid-range (VIN ~=VDD_HV/2), 2-3mA depending on process, voltage and |
|
temperature. |
28/153 |
DS11620 Rev 7 |
SPC584Cx, SPC58ECx |
Electrical characteristics |
|
|
This situation may occur if the PAD is used as a ADC input channel, and VSS<VIN<VDD_HV. The applications should ensure that LP pads are always set to VDD_HV or VSS, to avoid the extra consumption. Please refer to the device pinout IO definition excel file to identify the low-power pads which also have an ADC function.
4.8.2I/O output DC characteristics
Figure 4 provides description of output DC electrical characteristics.
Figure 4. I/O output DC electrical characteristics definition
VINTERNAL
(SIUL register)
|
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|
|
|
|
|
|
VHYS |
Vout |
|
|
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|
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|
|
|
tSKEW20-80 |
90% |
|
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|
80% |
|
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20% |
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10% |
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|
tR20-80 |
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|
tF20-80 |
||
|
tR10-90 |
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|
tF10-90 |
|||
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|
|||
tTR(max) = MAX(tR10-90; tF10-90) |
t |
TR20-80 |
(max) |
= MAX(t |
; t |
F20-80 |
) |
||||
tTR(min) |
= MIN(tR10-90; tF10-90) |
|
|
|
|
R20-80 |
|
|
|||
t |
TR20-80 |
(min) |
= MIN(t |
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; t |
F20-80 |
) |
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R20-80 |
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tSKEW20-80 |
= |tR20-80-tF20-80| |
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tSKEW10-90 |
= |tR10-90-tF10-90| |
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The following tables provide DC characteristics for bidirectional pads:
•Table 13 provides output driver characteristics for I/O pads when in WEAK/SLOW configuration.
•Table 14 provides output driver characteristics for I/O pads when in MEDIUM configuration.
•Table 15 provides output driver characteristics for I/O pads when in STRONG/FAST configuration.
•Table 16 provides output driver characteristics for I/O pads when in VERY STRONG/VERY FAST configuration.
Note: |
10%/90% is the default condition for any parameter if not explicitly mentioned differently. |
DS11620 Rev 7 |
29/153 |
Electrical characteristics |
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SPC584Cx, SPC58ECx |
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Table 13. WEAK/SLOW I/O output characteristics |
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C |
Parameter |
Conditions |
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Unit |
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Min |
Typ |
Max |
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Output low |
Iol = 0.5 mA |
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Vol_W |
CC |
D |
voltageforWeak |
VDD = 5.0 V ± 10% |
— |
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0.1*VDD |
V |
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type PADs |
VDD = 3.3 V ± 10% |
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Output high |
Ioh = 0.5 mA |
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Voh_W |
CC |
D |
voltageforWeak |
VDD = 5.0 V ± 10% |
0.9*VDD |
— |
— |
V |
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type PADs |
VDD = 3.3 V ± 10% |
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Output |
VDD = 5.0 V ± 10% |
380 |
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1040 |
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R_W |
CC |
P |
impedance for |
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Ω |
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VDD = 3.3 V ± 10% |
250 |
— |
700 |
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Weak type PADs |
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CL = 25 pF |
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Maximumoutput |
VDD = 5.0 V ± 10% |
— |
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2 |
MHz |
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VDD = 3.3 V ± 10% |
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Fmax_W |
CC |
T |
frequency for |
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CL = 50 pF |
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Weak type PADs |
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VDD = 5.0 V ± 10% |
— |
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1 |
MHz |
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VDD = 3.3 V ± 10% |
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CL = 25 pF |
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Transition time |
VDD = 5.0 V + 10% |
25 |
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120 |
ns |
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output pin |
VDD = 3.3 V + 10% |
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tTR_W |
CC |
T |
weak |
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CL = 50 pF |
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configuration, |
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10%-90% |
VDD = 5.0 V ± 10 % |
50 |
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— |
240 |
ns |
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VDD = 3.3 V ± 10 % |
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Difference |
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|tSKEW_W| |
CC |
T |
between rise |
— |
— |
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25 |
% |
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and fall time, |
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90%-10% |
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IDCMAX_W |
CC |
D |
Maximum DC |
VDD = 5.0 V ± 10% |
— |
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0.5 |
mA |
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current |
VDD = 3.3 V ± 10% |
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Table 14. MEDIUM I/O output characteristics |
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Symbol |
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C |
Parameter |
Conditions |
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Value |
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Unit |
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Min |
Typ |
Max |
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Output low |
Iol = 2.0 mA |
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voltage for |
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Vol_M |
CC |
D |
VDD =5.0 V ± 10 % |
— |
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— |
0.1*VDD |
V |
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Medium type |
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PADs |
VDD =3.3 V ± 10 % |
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Output high |
Ioh=2.0 mA |
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V |
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CC |
D |
voltage for |
0.9*V |
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— |
— |
V |
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oh_M |
Medium type |
VDD = 5.0 V ± 10% |
DD |
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VDD = 3.3 V ± 10% |
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PADs |
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30/153 |
DS11620 Rev 7 |