Dual step-down controller with adjustable voltages, adjustable LDO
and auxiliary charge pump controller for notebook
Features
■ 5.5 V to 28 V input voltage range
■ Dual fixed OUT1 = 1.5 V/5 V and OUT2 =
1.05 V / 3.3 V outputs or adjustable OUT1 = 0.7
V to 5.5 V and OUT2 = 0.7 V to 2.5 V outputs,
± 1.5% accuracy over valley regulation
■ Low-side MOSFETs' R
current sensing
DS(on)
and programmable current limit
■ Constant ON-time control
■ Frequency selectable
■ Soft-start internally fixed at 2 ms and soft-stop
■ Selectable pulse skipping at light loads
■ Selectable minimum frequency (33 kHz) in
pulse skip mode
■ Independent Power Good and EN signals
■ Latched OVP and UVP
■ Charge pump feedback
■ Fixed 3.3 V/5.0 V, or adjustable output 0.7 V to
4.5 V, ± 1.5% (LDO): 200 mA
■ 3.3 V reference voltage ± 2.0%: 5 mA
■ 2.0 V reference voltage ± 1.0%: 50 µA
Applications
■ Notebook computers
■ Main (3.3 V/5 V), chipset (1.5 V/1.05 V),
DDR1/2/3, graphic cards power supply
■ PDAs, mobile devices, tablet PC or slates
■ 3-4 cells Li+ battery powered devices
Description
PM6686 is a dual step-down controller specifically
designed to provide extremely high efficiency
conversion, with lossless current sensing
technique. The constant on-time architecture
assures fast load transient response and the
embedded voltage feed-forward provides nearly
constant switching frequency operation. Pulse
skipping technique increases efficiency at very
light load. Moreover a minimum switching
frequency of 33 kHz is selectable to avoid audio
noise issues. The PM6686 provides a selectable
switching frequency, allowing three different
values of switching frequencies for the two
switching sections. The output voltages OUT1
and OUT2 can be programmed to regulate
1.5 V/5 V and 1.05 V/3.3 V outputs respectively or
can deliver two adjustable output voltages. An
optional external charge pump can be monitored.
This device embeds a linear regulator that can
provide 3.3 V/5 V or an adjustable voltage from
0.7 V to 4.5 V output. The linear regulator
provides up to 100 mA output current. LDO can
be bypassed with the switching regulator outputs
or with an external power supply (switchover
function).
VFQFPN-32 5 x 5 mm
When in switchover, the LDO output can source
up to 200 mA.
3VCCController supply voltage input. Bypass to GND with a 1 μF capacitor.
4EN_LDO
5VREF3
6VIN
!-V
Internal 2 V high accuracy voltage reference. It can deliver 50 μA. Loading
VREF2 can affect FB and output accuracy. Bypass to GND with a 100 nF
capacitor.
Frequency selection pin. It provides a selectable switching frequency,
allowing three different values of switching frequencies for the switching
sections.
Enable input for the linear regulator. The LDO is enabled if
EN_LDO is > 1.6 V and is disabled if EN_LDO < 1 V.
Internal 3.3 V high accuracy voltage reference. It can deliver 5 mA if
bypassed to GND with a 10 nF capacitor. If not used, it can be left floating.
Device supply voltage pin. VIN is used in the on-time generators of the two
switching controllers. VIN is also used to power the linear regulator when the
switchover function is not active. Connect VIN to the battery input and
bypass with a 1 µF capacitor.
Doc ID 15281 Rev 47/50
Pin settingsPM6686
Table 2.Pin descriptions (continued)
N°PinFunction
Linear regulator output. It can provide up to 100 mA peak current. The LDO
regulates at 5 V If LDOREFIN is connected to GND. When the LDO is set at
5 V and LDO_SW is within 5 V switchover threshold, the internal regulator
shuts down and the LDO output pin is connected to LDO_SW through a
7LDO
8LDOREFIN
9LDO_SW
10OUT1
0.8 Ω switch. The LDO regulates at 3.3 V if LDOREFIN is connected to
VCC. When the LDO is set at 3.3 V and LDO_SW is within 3.3 V switchover
threshold, the internal regulator shuts down and the LDO output pin is
connected to LDO_SW through a 1.1 Ω switch. Bypass LDO output to GND
with a minimum of 4.7 µF ceramic capacitor.
Feedback of the adjustable linear regulator. Connect LDOREFIN to GND for
fixed 5 V operation. Connect LDOREFIN to VCC for fixed 3.3 V operation.
LDOREFIN can be used to program LDO output voltage from 0.7 V to 4.5 V:
LDO output is two times the voltage of LDOREFIN. The switchover function
is disabled in adjustable mode.
Source of the switchover connection. LDO_SW is the switchover source
voltage for the LDO when LDOREFIN is connected to GND or VCC.
Connect LDO_SW to 5 V if LDOREFIN is tied to GND. Connect LDO_SW to
3.3 V if LDOREFIN is tied to VCC.
Output voltage sense for the switching section 1.This pin must be directly
connected to the output voltage of the switching section. It provides also the
feedback for the switching section 1 when FB1 is tied to GND/VCC.
Feedback input for the switching section 1:
– If this pin is connected to GND, OUT1 operates at 5 V
11FB1
– If this pin is connected to VCC, OUT1 operates at 1.5 V
– This pin is connected to a resistive voltage-divider from OUT1 to GND to
adjust the output voltage from 0.7 V to 5.5 V.
12ILIM1
Positive current sense input for the switching section 1. It is possible to set a
threshold voltage that is compared with 1/10
th
of the GND-PHASE1 drop
during the off time.
Power Good output signal for the section 1. This pin is an open drain output
13PG1
and It is pulled down when the output of the switching section 1 is out of
+/- 10% of its nominal value.
Enable input for the switching section 1.
– If EN1 < 0.8 V the switching section OUT1 is turned off and all faults are
14EN1
cleared.
– If EN1 > 2.4 V the switching section OUT1 is turned on.
– If EN1 is connected to VREF2, the switching section OUT1 turns on after
the switching section OUT2 reaches regulation.
15HGATE1High-side gate driver output for section 1.
16PHASE1
17BOOT1
Switch node connection and return path for the high-side driver for the
section 1.It is also used as positive and negative current sense input.
Bootstrap capacitor connection for the switching section 1. It supplies the
high-side gate driver.
18LGATE1Low-side gate driver output for the section 1.
19PVCC
5 V low-side gate drivers supply voltage input. Bypass to PGND with a 1 μF
capacitor.
8/50 Doc ID 15281 Rev 4
PM6686Pin settings
Table 2.Pin descriptions (continued)
N°PinFunction
The CP_FB is used to monitor the optional external 14 V charge pump.
Connect a resistive voltage-divider from 14 V charge pump output to GND. If
20CP_FB
21GND
22PGND
23LGATE2Low-side gate driver output for the section 2.
24BOOT2
25PHASE2
26HGATE2High-side gate driver output for section 2.
27EN2
28PG2
29SKIP
30OUT2
31ILIM2
32REFIN2
CP_FB drops below the threshold voltage, the device performs a no audible
skip cycle. This charges the charge pump output (driven by LGATE1). Leave
CP_FB floating if the charge pump feedback is not needed.
Signal ground reference for internal logic circuitry and LDO. It must be
connected to the signal ground plan of the power supply and to the exposed
pad. The signal ground plan and the power ground plan must be connected
together in one point near the PGND pin.
Power ground. This pin must be connected to the power ground plan of the
power supply.
Bootstrap capacitor connection for the switching section 2. It supplies the
high-side gate driver.
Switch node connection and return path for the high-side driver for the
section 2. It is also used as positive and negative current sense input.
Enable input for the switching section 2.
– If EN2 < 0.8 V the switching section OUT2 is turned off and all faults are
cleared.
– If EN2 > 2.4 V the switching section OUT2 is turned on.
If EN2 is connected to VREF2, the switching section OUT2 turns on after
the switching section OUT1 reaches regulation.
Power Good output signal for the section 2. This pin is an open drain output
and It is pulled down when the output of the switching section 2 is out of
+ 14% / - 10% of its nominal value.
Pulse skipping mode control input.
– If the pin is connected to VCC the PWM mode is enabled.
– If the pin is connected to GND, the pulse skip mode is enabled.
– If the pin is connected to VREF2 (or floating) the pulse skip mode is
enabled but and the switching frequency is kept higher than 33 kHz (No-
audible pulse skip mode).
Output voltage sense for the switching section 2.This pin must be directly
connected to the output voltage of the switching section. It provides also the
feedback for the switching section 2 when REFIN2 is tied to VREF3/VCC.
Positive current sense input for the switching section 2. It is possible to set a
threshold voltage that is compared with 1/10
th
of the GND-PHASE2 drop
during the off time.
Feedback input for the switching section 2:
– If this pin is connected to VCC, OUT2 operates at 3.3 V
– If this pin is connected to VREF3, OUT2 operates at 1.05 V
– If this pin is connected to an external reference from 0.7 V to 2.5 V, OUT2
works in tracking with this reference. Bypass REFIN2 to GND with a 100
nF capacitor.
Doc ID 15281 Rev 49/50
Electrical dataPM6686
3 Electrical data
3.1 Maximum rating
Table 3.Absolute maximum ratings
ParameterValueUnit
VIN to PGND-0.3 to 38V
PHASEx to PGND-0.3 to 38V
BOOTx to PHASEx-0.3 to 6V
PVCC to PGND-0.3 to 6V
HGATEx to PHASEx-0.3 to BOOTx +0.3V
LGATEx, CP_FB to PGND-0.3 to PVCC +0.3V
VCC, ENx, SKIP, PGx, LDO, REFIN2, OUTx, VREF3,
LDOREFIN, LDO_SW, TON to GND
FB1, ILIMx to GND-0.3 to VCC+0.3V
EN_LDO to GND-0.3 to 7V
-0.3 to 6V
VREF2 to GND-0.3 to VREF3+0.3V
PGND to GND-0.3 to +0.3V
Power dissipation at T
Maximum withstanding voltage range test condition: CDF-AECQ100-002- “human body model” acceptance criteria: “normal
performance”
3.2 Thermal data
Table 4.Thermal data
SymbolParameterValueUnit
R
thJA
T
J
T
STG
Operating ambient temperature range-40 to 85 °C
T
A
Thermal resistance junction to ambient 35°C/W
Junction operating temperature range-40 to 125°C
Storage temperature range-50 to 150°C
= 25 °C2W
A
±1250V
10/50 Doc ID 15281 Rev 4
PM6686Recommended operating conditions
4 Recommended operating conditions
Table 5.Recommended operating conditions
Val ue
SymbolParameter
MinTypMax
VINInput voltage range, LDO = 5 V in regulation5.5-28V
VCCVCC operative voltage range4.5-5.5V
REFIN2
REFIN2 voltage range with OUT2 in
adjustable mode, VIN = 5.5 V to 28 V
0.7-2.5V
OUT1OUT1 output voltage range0.70-5.50V
ILIMILIM voltage range0.2-2V
Unit
LDOREFIN
LDO DC output current
(switchover function
enabled)
LDO DC output current
(switchover function
disabled)
LDOREFIN setting with LDO = 2 x LDOREFIN
(adjustable mode)
VIN = 5.5 V to 28 V, LDO_SW = 5 V,
LDOREFIN = GND
VIN = 5.5 V to 28 V, LDO_SW = 3.3 V,
LDOREFIN = VCC
VIN = 5.5 V to 28 V, LDO_SW = 0 V,
LDOREFIN = GND, VCC
0.35-2.25V
-200mA
-100mA
-100mA
Doc ID 15281 Rev 411/50
Electrical characteristicsPM6686
5 Electrical characteristics
VIN = 12 V, no load on LDO, OUT1, OUT2, VREF3, and VREF2. EN2 = EN1 = VCC,
LDO_SW = 5 V, PVCC = 5 V, EN_LDO = 5 V, T
Table 6.Electrical characteristics
SymbolParameterTest conditionMinTypMaxUnit
Switching controller output accuracy
= 25 °C unless otherwise specified)
J
OUT2Output voltage
OUT1Output voltage
FB1
Feedback accuracy with
OUT1 in adjustable mode
REFIN2Accuracy referred to REFIN2
Current limit and zero crossing comparator
ILIMILIM bias currentT
Positive current limit threshold
Zero crossing current
threshold
VIN = 5.5 V to 28 V, REFIN2 = VCC,
SKIP = VCC
VIN = 5.5 V to 28 V,
REFIN2 = VREF3, SKIP = VCC
VIN = 5.5 V to 28 V, FB1 = VCC,
SKIP = VCC
VIN = 5.5 V to 28 V, FB1 = GND,
SKIP = VCC
3.25 3.330 3.397V
1.038 1.05 1.062V
1.482 1.500 1.518V
4.975 5.050 5.125V
VIN = 5.5 V to 28 V, SKIP = VCC0.693 0.700 0.707V
REFIN2 = 0.7 V to 2.5 V,
SKIP = VCC
= +25 °C.4.555.5µA
A
-11%
Adjustable, VILIM = 0.5 V, GND-PHASE355065mV
Adjustable, VILIM = 1 V or VCC, GNDPHASE
85100115mV
Adjustable, VILIM = 2 V, GND-PHASE180200220mV
SKIP = GND, VREF2, or OPEN, GNDPHASE
-1+11mV
Switching frequency
OUT1 = 5.125 V
On-time pulse width
OUT2 = 3.368 VTON = GND0.477 0.561 0.655
Minimum Off-time350472
No-audible skip mode
operating frequency
SKIP = VREF2(or OPEN)2533kHz
Soft-start and soft-end
Soft-start ramp time24ms
12/50 Doc ID 15281 Rev 4
TON = GND or
VREF2
0.908 1.068 1.228
TON = VCC 1.815 2.135 2.455
TON = VCC or
VREF2
0.796 0.936 1.076
µs
PM6686Electrical characteristics
Table 6.Electrical characteristics (continued)
SymbolParameterTest conditionMinTypMaxUnit
Linear regulator and reference
LDOLDO output voltage
LDO_SW = GND, 5.5 V < VIN < 28 V,
LDOREFIN < 0.3 V, 0 < ILDO < 100 mA
Figure 26. OUT1 soft-start no loadFigure 27. OUT2 soft-start no load
Doc ID 15281 Rev 419/50
Typical operating characteristicsPM6686
Figure 28. OUT1 soft-start 8 A constant
Figure 30. OUT1 soft-end, no loadFigure 31. OUT2 soft-end, no load
current load
Figure 29. OUT2 soft-start loaded 8 A
constant current load
Figure 32. OUT1 soft-start, EN2 = VREF2
20/50 Doc ID 15281 Rev 4
no loads applied
Figure 33. OUT2 soft-start, EN1=VREF2
no loads applied
PM6686Typical operating characteristics
Figure 34. Soft-end, EN2 = VREF2 no
loads applied
Figure 36. Load transient 0-5 A 2 A/µs
OUT1 = 5 V PWM mode
Figure 35. Soft-end, EN1=VREF2 no
loads applied
Figure 37. Load transient 0-5 A 2 A/µs
OUT1 = 5 V SKIP mode
Figure 38. Load transient 0-5 A 2 A/ µs
OUT1 = 1.5 V PWM mode
Figure 39. Load transient 0-5 A 2 A/ µs
OUT1 = 1.5 V SKIP mode
Doc ID 15281 Rev 421/50
Typical operating characteristicsPM6686
Figure 40. Load transient 0-5 A 2 A/µs
OUT2 = 3.3 V PWM mode
Figure 42. Load transient 0-5 A 2 A/ µs
OUT2 = 1.05 V PWM mode
Figure 41. Load transient 0-5 A 2 A/µs
OUT2 = 3.3 V SKIP mode
Figure 43. Load transient 0-5 A 2 A/ µs
OUT2 = 1.05 V SKIP mode
22/50 Doc ID 15281 Rev 4
PM6686Block diagram
7 Block diagram
Figure 44. Functional block diagram
LD OR EFI N
LDO
LD O_ SW
CP_FB
BOOT1
HGAT E1
PHASE1
OU T1
UVLO
VREF3
+
-
VREF3VREF2
VIN
VREF2
ADJ.
LIN EAR
REGUL ATOR
LDO EN INT
SWITCHOVER
+
THRE SH OLD
-
PVC CPVCC
LEVEL
SHIFTER
SM PS1
CONTROLLER
SMPS2
CONTROLLER
PVCC
LEV EL
SHIFTE R
PVCC
PVCC
VCC
ILIM1
ILIM2
BOOT2
HSIDE2
PHASE2
OU T2
LGA TE2
LGATE1
FB1
PG1
EN1
EN2
STARTUP
CONTROLLER
LDO EN INT
THER MAL
CONTROLLER
REFIN2
PG2
EN _LDO
TONSKIP
Doc ID 15281 Rev 423/50
Device descriptionPM6686
8 Device description
The PM6686 is a dual step down controller dedicated to provide logic voltages for notebook
computers. It offers several operating configurations: it combines two synchronous buck
controllers, an internal linear regulator (LDO), two voltage references and a charge pump
controller.
Each buck controller is based on constant on time (COT) architecture. This type of control
offers a very fast load transient response with a minimum external components count.
The two switching sections (SMPS) generate two output voltages OUT1 and OUT2 that
regulate adjustable voltages. A fixed output voltage configuration can also be selected,
reducing further the external components count because no external resistor divider is
needed.
In fixed mode, OUT1 provides 5 V or 1.5 V; in adjustable mode OUT1 can regulate an output
voltage between 0.7 V and 5.5 V. In fixed mode, OUT2 provides 3.3 V or 1.05 V, in
adjustable mode OUT2 can regulate an output between 0.7 V to 2.5 V by tracking an
external reference.
The switching frequencies of both switching controllers can be adjusted to 200 kHz/300 kHz,
400 kHz/300 kHz or 400 kHz/500 kHz respectively. To maximize the efficiency at light loads
a pulse skipping mode can be selected. Moreover a pulse skipping mode with a minimum
switching frequency of 33 kHz (non audible skip operation mode) can be selected to avoid
audible noise issue. The linear regulator can provide a fixed (5 V or 3.3 V) or an adjustable
output voltage. In order to reduce the power consumption the internal LDO can be turned off
and the LDO output can be supplied with an external voltage applied at LDO_SW pin
(switch-over function).
The PM6686 supplies two voltage references: 3.3 V and 2 V. The charge pump controller
can be programmed to regulate a 14 V output. The switching sections and the LDO have
independent enable signals. Moreover the switching sections have a selectable power up
sequence and a turn off management.
The device is protected against overvoltage, undervoltage and over temperature. Two
independent Power Good signals monitor the output voltage range of each switching
sections.
8.1 Switching sections
8.1.1 Output voltage set up
The switching sections can be configured in several ways.
OUT1 output voltage is configured with FB1 pin. If FB1 pin is tied to GND the PM6686
regulates 5 V while if FB1 is connected to VCC the controller set OUT1 at 1.5 V. Using an
external resistor divider the output can be adjusted following this equation:
Equation 1
1R
⎛
V7,0V
1OUT
⎜
⎝
⎞
+⋅=1
⎟
2R
⎠
24/50 Doc ID 15281 Rev 4
PM6686Device description
Figure 45. Resistor divider to configure the output voltage
VOUT
CO UT
L
R1
PHASE
FB1
R2
Where R1, R2 are the resistors of the FB1 pin divider, as shown in Figure 2.
OUT2 output voltage is programmed with REFIN2 pin. Fixed output voltage is selected
connecting REFIN2 to VREF3 (OUT2 = 1.05 V) or to VCC (OUT2 = 3.3 V).
When the REFIN2 voltage is between 0.7 V and 2.5 V, OUT2 output voltage tracks REFIN2
voltage. When REFIN2 is lower than 0.5 V the section is turned OFF.
Table 7.Switching output voltages configuration
Outputcontrol pin
Control pin
connected to
Operation modeOutput voltage
GNDFixed5 V
VCCFixed1.5 V
OUT1FB1
Resistor dividerAdj
1R
⎛
V7.0V
1OUT
⎜
⎝
⎞
+⋅=1
⎟
2R
⎠
VCCFixed3.3 V
OUT2REFIN2
VREF3Fixed1.05 V
Ext sourceTracking=REFIN2
Doc ID 15281 Rev 425/50
Device descriptionPM6686
8.1.2 Constant on time control (COT)
PM6686 implements a pseudo-fixed frequency algorithm using the COT architecture. The
two sections are completely independent with separated switching controllers (SMPS).
The COT architecture bases its algorithm on the output ripple derived across the output
capacitor's ESR. The controller has an internal on time (T
output voltage valley: when VOUT reaches the regulation value a new T
duration is given by the following equation:
Equation 2
V
OUT
KT⋅=
ON
V
IN
) generator triggered on the
ON
starts. The TON
ON
Where TON is the on time duration, K is a constant, V
is the sensed output voltage and
OUT
VIN is the input voltage.
The duty cycle in a buck converter is:
Equation 3
T
ON
T
SW
V
OUT
D
==
V
IN
The switching frequency in continuous current mode (CCM) is:
Equation 4
V
OUT
f
SW
D
T
ON
V
IN
==
V
OUT
⋅
K
V
1
=
K
IN
The switching frequency is theoretically constant, but in a real application it depends on
parasitic voltage drops that occur during the charging path (high-side switch resistance,
inductor resistance (DCR)) and discharging path (low-side switch resistance, DCR). As a
result the switching frequency increases as a function of the load current. The following
table shows the switching frequencies that can be selected through TON pin:
Table 8.Frequency configurations
SMPS 1SMPS 2
TON
FrequencyKFrequencyK
VCC200 kHz5 µs300 kHz3.33 µs
VREF2 or open400 kHz2.5 µs300 kHz3.33 µs
26/50 Doc ID 15281 Rev 4
GND400 kHz2.5 µs500 kHz2 µs
PM6686Device description
The COT architecture uses a minimum off-time (T
OFFMIN
) to allow inductor valley current
sense on the synchronous switch and to allow the charge of the bootstrap capacitor. A
minimum on-time is also introduced to assure the start-up sequence.
An adaptive anti-cross conduction algorithm avoids current paths between V
and GND
IN
during switching transition.
The PM6686 has three different operation modes selectable with SKIP pin: forced PWM
(PWM), pulse SKIP (SKIP) and non audible pulse SKIP (NA SKIP). The following
paragraphs explain in details the different features of these operation modes.
Table 9.Operative mode configurations
Control pin
SKIP
Control pin
connected to
Operation mode
VCCPWM
GNDSKIP
VREF2 or floatingNA SKIP
Figure 46. Constant on time block diagram
Toff min
BOOT
ILIM
OU T
VIN
1/10
PHA SE
Vol tag e
Reference
+
-
0,8V
-
+
PWM
Comparator
+
-
Z.C.
Comparator
-
SE T
Q
S
Q
R
CLR
Ton
ge ne ra tor
Level
Shifter
SE T
Q
S
Q
R
CLR
-
+
HS Driver
0,25V
-
-
+
-
PVCC
LS Driver
HGATE
PH ASE
0,5V
LGATE
PG ND
Doc ID 15281 Rev 427/50
Device descriptionPM6686
f
t
8.1.3 PWM
PWM implements the continuous current mode (CCM). During TON, the high-side MOSFET
is turned on and the inductor current starts increasing. When the Ton is elapsed the highside MOSFET is turned off and after a dead time during which neither MOSFET conducts,
the low-side MOSFET turns on. The inductor current decreases until these three conditions
are verified:
●Output voltage reaches the regulation voltage
●Inductor current is below the current limit
●T
OFFMIN
When these conditions are satisfied a new T
PWM operation mode has a quasi-constant switching frequency, avoiding any audible noise
issue and the continuous current mode assures better load transitions despite of a lower
efficiency at light loads.
Figure 47. Inductor current and output voltage in PWM mode
Inductor
current
is elapsed
ON
starts.
Output
voltage
Vreg
Ton Tof
28/50 Doc ID 15281 Rev 4
PM6686Device description
T
T
8.1.4 SKIP
To improve the efficiency at light load the PM6686 implements pulse skip operation mode.
When SKIP pin is tied to GND the inductor current is sensed and if it is equal to zero the
synchronous MOSFET is turned off. As a consequence the output capacitor is left floating
and the discharge depends only on the current sourced by the load. The new T
when the output reaches the voltage regulation. As a consequence at light load conditions
the switching frequency decreases improving the total efficiency of the converter. Working in
discontinuous current mode, the switching and the conduction losses are decreased
skipping some cycles.
If the output load is high enough to make the system work in CCM, skip mode is
automatically changed in PWM mode.
Figure 48. Inductor current and output voltage in SKIP mode
Inductor
current
Output
ON
starts
Vreg
ON
OFF
8.1.5 Non audible SKIP (NA SKIP)
To avoid audio noise the NA SKIP operation mode can be selected, connecting SKIP pin to
VREF2 or leaving it floating. In this condition if a new cycle doesn't start within 30
from the previous one the PM6686 turns on the low-side MOSFET to discharge the output
capacitor. The inductor current goes negative until the output reaches the voltage regulation
voltage allowing a new cycle to begin. If the switching frequency is above 33 kHz the device
works in SKIP mode.
This operation mode is useful to avoid audio noise but it lowers the efficiency at light loads if
it is compared to the SKIP mode.
μs typ.
Doc ID 15281 Rev 429/50
Device descriptionPM6686
T
T
T
⋅⋅=
Figure 49. Inductor current and output voltage in NA SKIP mode
Inductor
cu rren t
Ou tput
Vreg
MA X
TON
OFF
IDLE
8.1.6 Gate drivers and logic supply
The integrated high-current drivers allow the use of different power MOSFET.
high-side driver is supplied with a bootstrap circuit with an integrated bootstrap diode. The
BOOT and the PHASE pins work respectively as supply and return rails for the HS driver.
The PVCC pin is the input for the supply of the low-side driver and PGND is the pin used as
return rail.
The PM6686 implements an anti-cross conduction protection which prevents high-side and
low-side MOSFET from being on at the same time.
The power dissipation of each driver can be calculated as:
Equation 5
Where V
The power dissipated by the drivers can be reduced lowering the sections switching
frequencies and mounting MOSFET with smaller Q
VCC pin is the input voltage rail to supply the internal logic circuit. This pin is connected
internally with a resistor to PVCC. As usual analog supply should be divided by the power
supply with a low pass filter to reduce the noise for the analog supply of the logic. Being the
resistor integrated it is enough to put a decoupling capacitor near VCC pin to realize the
filter with a components count reduction.
is the voltage applied to PVCC pin (+5 V) and fSW is the switching frequency.
PVCC
t
fQVP
swGPVCCDISS
.
G
30/50 Doc ID 15281 Rev 4
PM6686Device description
Figure 50. Internal supply diagram
8.1.7 Current sensing and current limit
The PM6686 implements a positive valley current limit to protect the application from an
overcurrent fault. Each section has an independent current limit setting. A new switching
cycle can't start until the inductor current is under the positive current limit threshold. Note
that the peak current flowing in the inductor can reach a value greater than the current limit
threshold by an amount equal to the inductor ripple current.
Figure 51. Current waveforms in current limit conditions
The inductor current is sensed during the off time T
across the low-side MOSFET using the R
PGND voltage). The voltage drop is compared to the threshold set with ILIM pin. If ILIM is
connected to a voltage higher than VCC-1V the limit is 100mV. A current of 5 µA is sourced
from the pin ILIM; if a resistor is connected between ILIM and ground the current limit is
given by the voltage at the ILIM pin. The device sets the PHASE voltage threshold at 1/10 of
the ILIM voltage.
by measuring the voltage drop
OFF
as a lossless sensing element (PHASE to
DS(on)
Doc ID 15281 Rev 431/50
Device descriptionPM6686
Figure 52. Current limit circuit block diagram
5uA
ILIM
RILIM
+
-
HGATE
9R
R
+-
Ton
Generator
PHASE
LGATE
Table 10.Current limit configuration
Control pinControl pin voltageThreshold SET
= VCC-1 V100 mV
V
ILIM1
ILIM2
ILIM
0.2 V = V
V
= 5µA * R
ILIM
ILIM
= 2 V
ILIM
V
/10
ILIM
A negative current control is also implemented: the low-side MOSFET is forced off when the
current exceeds the negative limit. This function prevents the excessive negative inductor
current during the PWM operating mode. The threshold is set approximately at the 120% of
the positive current limit.
8.1.8 Soft-start and soft-end
The two sections have independent enable pins, EN1 and EN2. A not programmable softstart procedure takes place when EN pin rises above 2.4 V typ.
To prevent high input inrush currents, the current limit is increased from 25% to 100% with
steps of 25%.
The procedure is not programmable and ends typically in 2.8 ms. The overvoltage protection
is always active while the undervoltage protection is enabled typically 20 ms after the
beginning of the soft-start procedure.
Driving one EN pin below 0.8 V makes the section perform a soft-end: gate driving signals
32/50 Doc ID 15281 Rev 4
are pulled low and the output is discharged through an internal MOSFET with R
28
Ω typ.
A power up sequence for the switching sections can be selected connecting one EN pin to
VREF2.
DS(on)
of
PM6686Device description
The section with the EN pin connected to VREF2 begins the soft-start only when the other
section is in regulation (its PGOOD is high) and makes a soft-end suddenly when the other
section is turned off.
Figure 53. VOUT2 behavior if EN2 is connected to VREF2
EN1
VOUT 1
PGO OD1
OUT 2
To protect the EN1, EN2, EN_LDO and SKIP pin of the PM6686 an external divider or a
series resistor is required, in order to prevent a large inrush current flowing into the device in
case the voltage spike is exceeding the recommended operating conditions.
Doc ID 15281 Rev 433/50
Monitoring and protectionsPM6686
9 Monitoring and protections
The PM6686 controls its switching output to prevent any damage or uncontrolled working
condition.
The device offers also PGOOD signals to monitor the state of each switching output voltage.
PGOOD is an open drain output: it is pulled low if the output voltage is below the 90% or
above the OVP threshold. of the nominal value.
9.1 Overvoltage protection
PM6686 provides a latched overvoltage protection (OVP). If the output voltage rises above
the +111% typ. for section 1 and above the +116% typ. for the section 2, a latched OVP
protection is activated. The controller tries to pull down the output voltage down to 0 V,
working in PWM. The current is limited by the negative current limit. The low-side MOSFET
is kept on when the output voltage is about 0 V. This management avoids high negative
undervoltage of the output rail that may damage the load.
The protection is latched and this fault is cleared toggling cleared by toggling EN or by
driving PVCC<3.979V and then PVCC>4.025V (PVCC Power On Reset).
9.2 Undervoltage protection
If during regulation the output voltage droops under the 70% of the nominal value, an
undervoltage latched fault is detected. The controller performs a soft-end procedure (see
“soft-start and soft-end” paragraph). The undervoltage fault is cleared by toggling EN or by
driving PVCC<3.979V and then PVCC>4.025V (PVCC power on reset).
9.3 PVCC monitor
The device monitors the driver supply voltage at PVCC pin. The switching sections can start
operating only if the voltage at PVCC pin is above 4,025 V typ. If PVCC falls below 3,979 V
typ., both the switching sections are turned off until the PVCC voltage goes over 4,025 V typ.
Table 11.Faults management summary
FaultConditionDevice reaction
Overvoltage
section1
Overvoltage
section 2
UndervoltageV
PVCC
undervoltage
>+111%
V
OUT
>+116%
V
OUT
OUT
PVCC<3,979 V
<70%
Negative current limit protection activated. Low-side MOSFET is turned on when
the output voltage is about 0 V. Latched fault, cleared by toggling EN or by driving
PVCC<3.979V and then PVCC>4.025V (PVCC POR).
Negative current limit protection activated. Low-side MOSFET is turned on when
the output voltage is about 0 V. Latched fault, cleared by toggling EN or by driving
PVCC<3.979V and then PVCC>4.025V (PVCC POR).
The controller performs a soft-end. Latched fault cleared by toggling EN or by
driving PVCC<3.979V and then PVCC>4.025V (PVCC POR).
The controller turns off the switching sections. All faults of switching sections are
cleared. Not latched fault
34/50 Doc ID 15281 Rev 4
PM6686Monitoring and protections
9.4 Linear regulator section
The PM6686 has an integrated linear regulator (LDO) that can provide an average of
100 mA typ. with a peak current of 270 mA typ. The LDO can be enabled using EN_LDO
pin. If VIN is applied the linear regulator is active even if PVCC is low.
The output voltage can be programmed by LDOREFIN pin. If LDOREFIN pin is tied to
ground (GND) the LDO provides a +5 V output voltage. If it is connected to VREF3 pin the
LDO regulates 3.3 V. If the voltage at the LDOREFIN pin is between 0.35 V and 2.25 V the
LDO generates an output voltage equals to 2xV
LDOREFIN
Table 12.LDO output voltage configuration
LDOREFIN voltageLDO voltage
GND+5 V
VREF3+3,3 V
0,35 V < V
LDOREFIN
< 2,25 V2x V
The controller provides a switchover function when LDOREFIN pin is connected to VCC or
GND. If the voltage at LDO_SW pin is high enough, the internal linear regulator is turned off
and the LDO pin is connected with an internal MOSFET to the LDO_SW pin. This feature
decreases the power dissipation of the device.
.
LDOREFIN
When the switchover function is used the maximum current capability is 200 mA if LDO
output is +5 V and 100 mA if the LDO output is +3.3 V.
Table 13.LDO switchover management
V
LDOREFIN
V
BYPLDO_SW
V
LDO
Internal LDO
< 0,35 V> 4,75 V+5 VDisabled0.81 Ω
< 0,35 V< 4,55 V+5 VEnabled-
> 2.43 V> 3.18 V+3,3 VDisabled1.12 Ω
> 2.43 V< 3.05 V +3,3 VEnabled-
0,35 V < V
LDOREFIN
< 2,25 V2x V
LDOREFIN
Enabled-
Switchover
resistance
Doc ID 15281 Rev 435/50
Monitoring and protectionsPM6686
−+=
9.5 Charge pump
The PM6686 can drive an external charge pump circuit whose typical application schematic
is shown in the next figure.
Figure 54. Charge pump application circuit
COU T
Vout
L
D1
D2
D3
C2
CP
C4
D4
C1
C3
PHASE
LGAT E
R1
CP_F B
R2
The charge pump works in 4 phases:
1. LGATE is low. C1 is charged through the D1a diode at OUT1 voltage minus the diode
drop.
2. LGATE is driven high and C1 transfers the charge to C2. C2 voltage is OUT1 voltage
plus the LGATE voltage minus the voltage drops on D1 and D2.
3. LGATE is turned low and C2 shares its charge with C3 thought D3.
4. LGATE becomes high and C3 can charge C4 thought diode D4.
Every diode used to transfer charge introduces a voltage drop that decreases the charge
pump output voltage.
Repeating this cycle several times makes the charge pump output voltage equals to:
Equation 6
V4V2VV
DIODE1LGATE1OUTCP
Where VCP is the charge pump output voltage, V
section 1, V
LGATE1
is the low-side MOSFET gate driving voltage and V
is the output voltage of the switching
OUT1
is the forward
DIODE
voltage droop of the diodes used in the application.
CP_FB pin must be connected to the output of the charge pump with a resistor divider;
when CP_FB pin droops below 2 V typ., OUT1 controller starts a NA SKIP cycle to boost the
voltage of the charge pump.
36/50 Doc ID 15281 Rev 4
PM6686Monitoring and protections
The minimum voltage of the charge pump is:
Equation 7
FB_CPMIN_CP
Where V
is the minimum voltage of CP_FB pin(2V typ.).
CP_FB
In case the charge pump feedback is not used, leave the CP_FB pin floating or connect the
pin to VCC.
9.6 Voltage references
The PM6686 provides two voltage references.
The device regulates a 3,3 V voltage reference (VREF3) with ±2% accuracy over
temperature. VREF3 can source up to 5 mA. VREF3 voltage is always available if V
applied. The device allows the enabling of the outputs if VREF3 is above 2,8V typ. and turns
off when VREF3 falls under 2,7 V typ.
VREF2 is a + 2 V reference with an accuracy of ±1% over temperature. It can source up to
50 µA typ. and sink up to 10 µA. VREF2is adopted as internal reference; this voltage can be
used as voltage threshold to set configuration pins (e.g. TON, SKIP pins). VREF2 is enabled
when one enable pin (EN1, EN2 or EN_LDO) is pulled high.
9.7 General device fault management
⎛
⎜
⎜
⎝
⎞
R
1
⎟
1VV
+⋅=
⎟
R
2
⎠
is
IN
9.7.1 Thermal protection
If the internal temperature of the device exceeds typically +150 °C, the controller shuts down
immediately all the internal circuitry. Switching sections performs the soft-end management.
Toggling EN, EN LDO or cycling VIN resets the latched fault.
Doc ID 15281 Rev 437/50
Application informationPM6686
10 Application information
10.1 External components selection
10.1.1 Inductor
Once that switching frequency is defined, inductor selection depends on the desired
inductor ripple current and load transient performance.
Low inductance means great ripple current and could generate great output noise. On the
other hand, low inductor values involve fast load transient response.
A good compromise between the transient response time, the efficiency, the cost and the
size is to choose the inductor value in order to maintain the inductor ripple current
between 20% and 50% of the maximum output current ILOAD (max). The maximum
occurs at the maximum input voltage. With these considerations, the inductor value can be
calculated with the following relationship:
Equation 8
ΔI
L
ΔI
L
VV
L
−
=
Δ×
Where fSW is the switching frequency, VIN is the input voltage, V
and
ΔI
is the selected inductor ripple current.
L
V
OUTIN
OUT
×
V
If
Lsw
IN
is the output voltage
OUT
In order to prevent overtemperature working conditions, inductor must be able to provide an
RMS current greater than the maximum RMS inductor current I
LRMS
:
Equation 9
(max))I(I
LOADLRMS
L
+=
12
2
(max))I(
Δ
2
Where ΔIL(max) is the maximum ripple current:
Equation 10
VV
−
sw
OUTmaxIN
Lf
×
(max)I×
L
=Δ
V
OUT
V
maxIN
If hard saturation inductors are used, the inductor saturation current should be much greater
than the maximum inductor peak current Ipeak:
Equation 11
Using soft-saturation inductors it’s possible to choose inductors with saturation current limit
nearly to Ipeak.
Below there is a list of some inductor manufacturers.
38/50 Doc ID 15281 Rev 4
LOAD
(max)I
Δ
(max)IIpeak
L
+=
2
PM6686Application information
Δ×=
Table 14.Inductor manufacturer
ManufacturerSeriesInductor value (µH)RMS current (A)Saturation current (A)
COILCRAFTMSS-10483,37,227,6
COILCRAFTMSS-12603,39,77
COILCRAFTMLC-15502,516,511,4
10.1.2 Input capacitor
In a buck topology converter the current that flows into the input capacitor is a pulsed current
with zero average value. The input RMS current of the two switching sections can be roughly
estimated as follows:
Equation 12
Where D1, D2 are the duty cycles and I1, I2 are the maximum load currents of the two
sections.
Input capacitor should be chosen with an RMS rated current higher than the maximum RMS
current given by both sections.
Tantalum capacitors are good in term of low ESR and small size, but they occasionally can
burn out if subjected to very high current during the charge. Ceramic capacitors have
usually a higher RMS current rating with smaller size and they remain the best choice.
Below there is a list of some ceramic capacitor manufacturers.
Table 15.Input capacitor manufacturer
ManufacturerSeriesCapacitor value (µF)Rated voltage (V)
TAYIO YUDENUMK325BJ106 KM-T1050
TAYIO YUDENGMK325BJ106MN1035
10.1.3 Output capacitor
The selection of the output capacitor is based on the ESR value and on the voltage rating
rather than on the capacitor value Cout.
2
11CinRMS
2
221
)D1(ID)D1(IDI
−××+−××=
2
The output capacitor has to satisfy the output voltage ripple requirements. Lower inductor
value can reduce the size of the choke but increases the inductor current ripp
Since the voltage ripple V
RIPPLEout
is given by:
le ΔIL.
Equation 13
IRV
LoutRIPPLEout
A low ESR capacitor is required to reduce the output voltage ripple. Switching sections can
work correctly even with 15mV output ripple.
Doc ID 15281 Rev 439/50
Application informationPM6686
Δ
Finally the output capacitor choice deeply impacts on the load transient response. Below
there is a list of some capacitor manufacturers.
Output capacitor manufacturer
Table 16.Input capacitor manufacturer
ManufacturerSeriesCapacitor value (µF)Rated voltage (V)ESR max (mΩ)
SANYOPOSCAP TPB150 to 3302.5 to 6.335 to 65
SANYOPOSCAP TPF150 to 4702.5 to 6.37 to 15
10.1.4 MOSFET
Logic-level MOSFETs are recommended, since low-side and high-side gate drivers are
powered by PVCC. Their breakdown voltage (VBRDSS) must be higher than the maximum
input voltage.
In notebook applications, power management efficiency is a high level requirement. The
power dissipation on the power switches becomes an important factor in switching
selections. Losses of high-side and low-side MOSFETs depend on their working conditions.
The power dissipation of the high-side MOSFET is given by:
Equation 14
PPP+=
switchingconductionDHighSide
Maximum conduction losses are approximately:
Equation 15
Where R
V
RP××=
DSonconduction
is the drain-source on resistance of the high-side MOSFET.
DS(on)
OUT
V
LOAD
minIN
2
(max)I
Switching losses are approximately:
Equation 16
Δ
I
L
+×
2
××
ft)
swoff
2
P
switching
Where ton and t
I
=
LOADIN
are the switching times of the turn off and turn off phases of the
off
2
2
L
−×
(max)I(V
××
ft)
(max)I(V
LOADINswon
+
MOSFETs.
As general rule, high-side MOSFETs with low gate charge are recommended, in order to
minimize driver losses.
Below there is a list of possible choices for the high-side MOSFETs.
40/50 Doc ID 15281 Rev 4
PM6686Application information
=
Table 17.High-side MOSFET manufacturer
ManufacturerTypeGate charge (nC)R
(mΩ) Rated reverse voltage (V)
DS(on)
STSTS12NH3LL10830
STSTS17NH3LL18430
The power dissipation of the low-side MOSFET is given by:
Equation 17
PP
conductionDLowSide
Maximum conduction losses occur at the maximum input voltage:
Equation 18
DSonconduction
Choose a synchronous rectifier with low R
⎛
⎜
1RP×
−×=
⎜
V
⎝
DS(on)
⎞
V
OUT
maxIN
⎟
LOAD
⎟
⎠
2
(max)I
. When high-side MOSFET turns on, the
fast variation of the phase node voltage can bring up even the low-side gate through its
gate-drain capacitance CRSS, causing cross-conduction problems. Choose a low-side
MOSFETs that minimizes the ratio CRSS/CGS (CGS = CISS - CRSS).
Below there is a list of some possible low-side MOSFETs.
Table 18.Low-side MOSFET manufacturer
C
ManufacturerTypeR
DS(on)
(mΩ)
C
RSS
GS
STSTS17NF3LL5.50.04730
STSTS25NH3LL3.50.01130
Rated reverse voltage
(V)
Dual N-channel MOSFETs can be used in applications with a maximum output current of
about 3 A. Below there is a list of some MOSFETs manufacturers.
Table 19.Dual MOSFET manufacturer
ManufacturerTypeR
DS(on)
(mΩ)
Gate charge
(nC)
STSTS8DNH3LL251030
STSTS4DNF60L653260
Rated reverse voltage
(V)
Doc ID 15281 Rev 441/50
Diode selectionPM6686
11 Diode selection
11.1 Freewheeling diode
A rectifier across the low-side MOSFET is recommended. The rectifier works as a voltage
clamp across the synchronous rectifier and reduces the negative inductor swing during the
dead time between turning the high-side MOSFET off and the synchronous rectifier on. It
can increase the efficiency of the switching section, since it reduces the low-side switch
losses. A Schottky diode is suitable for its low forward voltage drop (0.3 V). The diode
reverse voltage must be greater than the maximum input voltage. A minimum recovery
reverse charge is preferable. Below there is a list of some Schottky diode manufacturers.
Table 20.Schottky diode manufacturer
ManufacturerSeries
STSTPS1L30M0.34300.00039
STSTPS1L20M0.37200.000075
11.2 Charge pump diode
The charge pump capacitors are fed by the current supplied by LGATE1 (output of the lowside driver for the section 1). Dual in package diodes, in series configuration, could be used
to reduce the area occupation.
Table 21.Schottky diode manufacturer
ManufacturerSeries
STBAT54S0.24400.3
STBAR43A0.35300.1
STBAS69-040.35150.01
Forward voltage
(V)
Forward voltage
(V)
Rated reverse
voltage (V)
Rated reverse
voltage (V)
Reverse current
(μA)
Max forward
current (A)
42/50 Doc ID 15281 Rev 4
PM6686Diode selection
11.3 Other important components
11.3.1 VIN filter
A VIN pin low pass filter is suggested to reduce switching noise. The low pass filter is shown
in the next figure:
Figure 55. VIN pin filter
Typical component value is: C = 1 µF.
11.3.2 PVCC and VCC
PVCC and VCC are connected with an internal resistor (about 10 Ω); this allows reducing
the external components. Connect the +5 V supply rail only to PVCC.
Use a bypass capacitor on PVCC pin. A VCC low pass filter helps to reject switching
commutations noise, this filter can be implemented simply adding a bypass capacitor on
VCC pin.
A 10 nF to 100 nF ceramic capacitor on VREF2 pin must be added to ensure noise
rejection. If VREF3 voltage is not used the pin can be left floating, otherwise a 10 nF to 100
nF bypass ceramic capacitor should be mounted.
11.3.4 LDO output capacitors
Bypass the output of the linear regulator with 4,7 µF ceramic capacitor closer to the LDO
pin. In most applicative conditions the ceramic output capacitor can be enough to ensure
stability.
11.3.5 Bootstrap circuit
The external bootstrap circuit is represented in the next figure:
Figure 57. Bootstrap circuit
RBOOT
RBOOT
CBOOT
PHASE
L
The bootstrap circuit capacitor value CBOOT must provide the total gate charge to the highside MOSFET during turn on phase. A typical value is 100 nF.
A resistor RBOOT on the BOOT pin could be added in order to reduce noise when the
phase node rises up, working like a gate resistor for the turn on phase of the high-side
MOSFET. A typical value is R
BOOT
= 1 Ω.
44/50 Doc ID 15281 Rev 4
PM6686PCB design guidelines
12 PCB design guidelines
The layout is very important in terms of efficiency, stability and noise of the system. It is
possible to refer to the PM6686 demonstration board for a complete layout example.
For good PC board layout follows these guidelines:
●Place on the top side all the power components (inductors, input and output capacitors,
MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve
a layer to PGND plan. The PGND plan is the same for both the switching sections.
●AC current paths layout is very critical (see Figure 58). The first priority is to minimize
their length. Trace the LS MOSFET connection to PGND plan as short as possible.
Place the synchronous diode D near the LS MOSFET. Connect the LS MOSFET drain
to the switching node with a short trace.
●Place input capacitors near HS MOSFET drain. It is recommended to use the same
input voltage plan for both the switching sections, in order to put together all input
capacitors.
●Place all the sensitive analog signals (feedbacks, voltage references, current sense
paths) on the bottom side of the board or in an inner layer. Isolate them from the power
top side with a signal ground layer, SGND. Connect the SGND and PGND plans only in
one point (a multiple vias connection is preferable to a 0 Ω resistor connection) near the
PGND device pin. Place the device on the top or on the bottom size and connect the
exposed pad and the SGND pins to the SGND plan (see
●As general rule, make the high-side and low-side drivers traces wide and short.
●The high-side driver is powered by the bootstrap circuit. It’s very important to place
capacitor CBOOT as near as possible to the BOOT pin (for example on the layer
opposite to the device). Route HGATE and PHASE traces as near as possible in order
to minimize the area between them.
●The low-side gate driver is powered by PVCC pin. Placing PGND and LGATE pins near
the low-side MOSFETs reduces the length of the traces and the crosstalk noise
between the two sections.
●The linear regulator outputs are referred to SGND as long as the reference voltages
VREF2 and VREF3. Place their output filtering capacitors as near as possible to the
device.
●Place input filtering capacitors near PVCC, VCC and VIN pins.
Figure 58).
Doc ID 15281 Rev 445/50
PCB design guidelinesPM6686
Figure 58. Current paths, ground connection and driver traces layout
46/50 Doc ID 15281 Rev 4
PM6686Package mechanical data
13 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 22.VFQFPN 5x5x1.0 mm 32 L pitch 0.50 mechanical data
Databook (mm)
Dim.
MinTypMax
A0.80.91
A100.020.05
A30.2
b0.180.250.3
D4.8555.15
D2 See exposed pad variations
E4.8555.15
E2 See exposed pad variations
e0.5
L0.30.40.5
ddd0.05
(2)
(2)
Table 23.Exposed pad variations
(1)(2)
D2
E2
MinTyp Max MinTyp Max
2.903.103.202.903.103.20
1. VFQFPN stands for thermally enhanced very thin fine pitch quad flat package no lead.Very thin:
A = 1.00 mm max.
2. Dimensions D2 and E2 are not in accordance with JEDEC.
Doc ID 15281 Rev 447/50
Package mechanical dataPM6686
Figure 59. Package dimensions
48/50 Doc ID 15281 Rev 4
PM6686Revision history
14 Revision history
Table 24.Document revision history
DateRevisionChanges
09-Jan-20091Initial release
26-Feb-20092Updated input voltage range in coverpage
07-May-20093Updated pin 29 description in Table 2 on page 7
23-Jul-20094
Updated Table 3 on page 10, Section 8.1.8 on page 32, Section 9.1
on page 34, Section 9.2 on page 34 and Table 11 on page 34
Doc ID 15281 Rev 449/50
PM6686
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.