STMicroelectronics M93S66, M93S56, M93S46 User Manual

M93S66, M93S56

M93S46

4Kbit, 2Kbit and 1Kbit (16-bit wide) MICROWIRE Serial Access EEPROM with Block Protection

FEATURES SUMMARY

■Industry Standard MICROWIRE Bus

■Single Supply Voltage:

–4.5 to 5.5V for M93Sx6

–2.5 to 5.5V for M93Sx6-W

–1.8 to 5.5V for M93Sx6-R

■Single Organization: by Word (x16)

■Programming Instructions that work on: Word or Entire Memory

■Self-timed Programming Cycle with AutoErase

■User Defined Write Protected Area

■Page Write Mode (4 words)

■Ready/Busy Signal During Programming

■Speed:

–1MHz Clock Rate, 10ms Write Time (Current product, identified by process identification letter F or M)

–2MHz Clock Rate, 5ms Write Time (New Product, identified by process identification letter W or G)

■Sequential Read Operation

■Enhanced ESD/Latch-Up Behavior

■More than 1 Million Erase/Write Cycles

■More than 40 Year Data Retention

Figure 1. Packages

8

1

PDIP8 (BN)

8

1

SO8 (MN) 150 mil width

TSSOP8 (DS) 3x3mm body size

TSSOP8 (DW) 169 mil width

April 2004

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TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

POWER-ON DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Instruction Set for the M93S46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Instruction Set for the M93S66, M93S56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. READ, WRITE, WEN and WDS Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. PAWRITE and WRAL Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. PREAD, PRWRITE and PREN Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. PRCLEAR and PRDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

WRITE PROTECTION AND THE PROTECTION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Protection Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Protection Register Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Protection Register Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Protection Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Protection Register Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Operating Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 6. Operating Conditions (M93Sx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 7. Operating Conditions (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 8. AC Measurement Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. AC Measurement Conditions (M93Sx6-W and M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . 17

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Figure 9. AC Testing Input Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. DC Characteristics (M93Sx6, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 12. DC Characteristics (M93Sx6, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 13. DC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 14. DC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15. DC Characteristics (M93Sx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 17. AC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 18. AC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 19. AC Characteristics (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 10.Synchronous Timing (Start and Op-Code Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 12.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 13.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 28 Table 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 28 Figure 14.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 29 Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data 29

Figure 15.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline 30

Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data 30

Figure 16.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 31 Table 23. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 31

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 25. How to Identify Current and New Products by the Process Identification Letter . . . . . . . 32

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 26. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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SUMMARY DESCRIPTION

This specification covers a range of 4K, 2K, 1K bit serial Electrically Erasable Programmable Memory (EEPROM) products (respectively for M93S66, M93S56, M93S46). In this text, these products are collectively referred to as M93Sx6.

Figure 2. Logic Diagram

VCC

D

C		Q

S M93Sx6

PRE

W

VSS

AI02020

Table 1. Signal Names

S	Chip Select Input
D	Serial Data Input
Q	Serial Data Output
C	Serial Clock
PRE	Protection Register Enable
W	Write Enable
VCC	Supply Voltage
VSS	Ground

The M93Sx6 is accessed through a serial input (D) and output (Q) using the MICROWIRE bus protocol. The memory is divided into 256, 128, 64 x16 bit words (respectively for M93S66, M93S56, M93S46).

The M93Sx6 is accessed by a set of instructions which includes Read, Write, Page Write, Write All

and instructions used to set the memory protection. These are summarized in Table 2. and Table 3.).

A Read Data from Memory (READ) instruction loads the address of the first word to be read into an internal address pointer. The data contained at this address is then clocked out serially. The address pointer is automatically incremented after the data is output and, if the Chip Select Input (S) is held High, the M93Sx6 can output a sequential stream of data words. In this way, the memory can be read as a data stream from 16 to 4096 bits (for the M93S66), or continuously as the address counter automatically rolls over to 00h when the highest address is reached.

Within the time required by a programming cycle (tW), up to 4 words may be written with help of the Page Write instruction. the whole memory may also be erased, or set to a predetermined pattern, by using the Write All instruction.

Within the memory, a user defined area may be protected against further Write instructions. The size of this area is defined by the content of a Protection Register, located outside of the memory array. As a final protection step, data may be permanently protected by programming a One Time Programming bit (OTP bit) which locks the Protection Register content.

Programming is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle) and does not require an erase cycle prior to the Write instruction. The Write instruction writes 16 bits at a time into one of the word locations of the M93Sx6, the Page Write instruction writes up to 4 words of 16 bits to sequential locations, assuming in both cases that all addresses are outside the Write Protected area. After the start of the programming cycle, a Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is driven High.

Figure 3. DIP, SO and TSSOP Connections

	M93Sx6
S	1	8	VCC
C	2	7	PRE
D	3	6	W
Q	4	5	VSS
		AI02021

Note: See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.

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An internal Power-on Data Protection mechanism in the M93Sx6 inhibits the device when the supply is too low.

POWER-ON DATA PROTECTION

To prevent data corruption and inadvertent write operations during power-up, a Power-On Reset (POR) circuit resets all internal programming circuitry, and sets the device in the Write Disable mode.

–At Power-up and Power-down, the device must not be selected (that is, Chip Select Input

(S) must be driven Low) until the supply

voltage reaches the operating value VCC specified in Table 5. to Table 6..

–When VCC reaches its valid level, the device is properly reset (in the Write Disable mode) and is ready to decode and execute incoming instructions.

For the M93Sx6 devices (5V range) the POR threshold voltage is around 3V. For the M93Sx6- W (3V range) and M93Sx6-R (2V range) the POR threshold voltage is around 1.5V.

INSTRUCTIONS

The instruction set of the M93Sx6 devices contains seven instructions, as summarized in Table 2. to Table 3.. Each instruction consists of the following parts, as shown in Figure 4.:

■Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock (C) being held Low.

■A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of Serial Clock (C).

■Two op-code bits, read on Serial Data Input

(D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code).

■The address bits of the byte or word that is to be accessed. For the M93S46, the address is made up of 6 bits (see Table 2.). For the M93S56 and M93S66, the address is made up of 8 bits (see Table 3.).

The M93Sx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table 16. to Table 19..

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Table 2. Instruction Set for the M93S46

					Start	Op-	Address1		Required	Additional
	Instruction	Description	W	PRE				Data	Clock
					bit	Code				Comments
									Cycles
	READ	Read Data	X	0	1	10	A5-A0	Q15-Q0
		from Memory
										Write is executed if
	WRITE	Write Data to	1	0	1	01	A5-A0	D15-D0	25	the address is not
		Memory								inside the Protected
										area
										Write is executed if
	PAWRITE	Page Write to	1	0	1	11	A5-A0	N x	9 + N x 16	all the N addresses
		Memory						D15-D0		are not inside the
										Protected area
		Write All								Write all data if the
		Memory
	WRAL		1	0	1	00	01 XXXX	D15-D0	25	Protection Register
		with same
										is cleared
		Data
	WEN	Write Enable	1	0	1	00	11 XXXX		9
	WDS	Write Disable	X	0	1	00	00 XXXX		9
										Data Output =
	PRREAD	Protection	X	1	1	10	XXXXXX	Q5-Q0		Protection Register
		Register Read						+ Flag		content + Protection
										Flag bit
		Protection								Data above specified
	PRWRITE		1	1	1	01	A5-A0		9	address A5-A0 are
		Register Write
										protected
		Protection								Protect Flag is also
	PRCLEAR		1	1	1	11	111111		9	cleared (cleared
		Register Clear
										Flag = 1)
		Protection
	PREN	Register	1	1	1	00	11XXXX		9
		Enable
		Protection								OTP bit is set
	PRDS	Register	1	1	1	00	000000		9
										permanently
		Disable

Note: 1. X = Don’t Care bit.

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Table 3. Instruction Set for the M93S66, M93S56
				Start	Op-	Address1,2			Required	Additional
Instruction	Description	W	PRE				Data		Clock
				bit	Code					Comments
									Cycles
READ	Read Data	X	0	1	10	A7-A0	Q15-Q0
	from Memory
										Write is executed if
WRITE	Write Data to	1	0	1	01	A7-A0	D15-D0		27	the address is not
	Memory									inside the
										Protected area
										Write is executed if
	Page Write to						N x			all the N
PAWRITE		1	0	1	11	A7-A0			11 + N x 16	addresses are not
	Memory						D15-D0
										inside the
										Protected area
	Write All									Write all data if the
	Memory
WRAL		1	0	1	00	01XXXXXX	D15-D0		27	Protection
	with same
										Register is cleared
	Data
WEN	Write Enable	1	0	1	00	11XXXXXX			11
WDS	Write Disable	X	0	1	00	00XXXXXX			11
										Data Output =
PRREAD	Protection	X	1	1	10	XXXXXXXX	Q7-Q0			Protection
	Register Read						+ Flag			Register content +
										Protection Flag bit
										Data above
PRWRITE	Protection	1	1	1	01	A7-A0			11	specified address
	Register Write									A7-A0 are
										protected
	Protection									Protect Flag is also
PRCLEAR		1	1	1	11	11111111			11	cleared (cleared
	Register Clear
										Flag = 1)
	Protection
PREN	Register	1	1	1	00	11XXXXXX			11
	Enable
	Protection									OTP bit is set
PRDS	Register	1	1	1	00	00000000			11
										permanently
	Disable

Note: 1. X = Don’t Care bit.

2. Address bit A7 is not decoded by the M93S56.

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Figure 4. READ, WRITE, WEN and WDS Sequences

READ

PRE

S

D

1 1 0 An

A0

Q

Qn

Q0

ADDR

DATA OUT

OP

CODE

WRITE

PRE

W

S

CHECK

D

STATUS

1 0 1 An

A0

Dn

D0

Q

ADDR

DATA IN

BUSY

READY

OP

CODE

WRITE

PRE

WRITE

PRE

ENABLE

W

DISABLE

S

S

D

1 0 0 0 0 Xn X0

D

1 0 0 1 1 Xn X0

OP

CODE

OP

CODE

AI00889D

Note: For the meanings of An, Xn, Qn and Dn, see Table 2. and Table 3..

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Read

The Read Data from Memory (READ) instruction outputs serial data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Sx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read.

Write Enable and Write Disable

The Write Enable (WEN) instruction enables the future execution of write instructions, and the Write Disable (WDS) instruction disables it. When power is first applied, the M93Sx6 initializes itself so that write instructions are disabled. After an Write Enable (WEN) instruction has been executed, writing remains enabled until an Write Disable (WDS) instruction is executed, or until VCC falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write Disable (WDS) instructions.

Write

The Write Data to Memory (WRITE) instruction is composed of the Start bit plus the op-code followed by the address and the 16 data bits to be written.

Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).

After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input

(S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed.

While the M93Sx6 is performing a write cycle, but after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low.

Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle.

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Figure 5. PAWRITE and WRAL Sequence

PAGE

PRE

WRITE

W

S

CHECK

D

STATUS

1 1 1

An

A0

Dn

D0

Q

ADDR

DATA IN

BUSY

READY

OP

CODE

WRITE

PRE

ALL

W

S

CHECK

D

1 0 0 0 1 Xn X0

STATUS

Dn

D0

Q

ADDR

DATA IN

BUSY

READY

OP

CODE

AI00890C

Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..

Page Write

A Page Write to Memory (PAWRITE) instruction contains the first address to be written, followed by up to 4 data words.

After the receipt of each data word, bits A1-A0 of the internal address register are incremented, the high order bits remaining unchanged (A7-A2 for M93S66, M93S56; A5-A2 for M93S46). Users must take care, in the software, to ensure that the last word address has the same upper order address bits as the initial address transmitted to avoid address roll-over.

The Page Write to Memory (PAWRITE) instruction will not be executed if any of the 4 words addresses the protected area.

Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).

After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input

(S) is brought Low before or after this specific time frame, the self-timed programming cycle will not

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be started, and the addressed location will not be programmed.

While the M93Sx6 is performing a write cycle, but after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low.

Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle.

Write All

The Write All Memory with same Data (WRAL) instruction is valid only after the Protection Register has been cleared by executing a Protection Register Clear (PRCLEAR) instruction. The Write All Memory with same Data (WRAL) instruction simultaneously writes the whole memory with the same data word given in the instruction.

Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).

After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input

(S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed.

While the M93Sx6 is performing a write cycle, but after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low.

Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle.

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