4Kbit, 2K bi t and 1Kb i t (16-bit wide)
MICROWIRE Serial Access EEPROM with Block Protection
FEAT URES SUM MARY
■ Industry Standard MICROWIRE Bus
■ Single Supply Voltage:
– 4.5 to 5.5V for M93Sx6
– 2.5 to 5.5V for M93Sx6-W
– 1.8 to 5.5V for M93Sx6-R
■ Single Organization: by Word (x16)
■ Programming Instructions that work on: Word
or Entire Memory
■ Self-timed Programming Cycle with Auto-
Erase
■ User Defined Write Protected Area
■ Page Write Mode (4 words)
■ Ready/Busy Signal During Programming
■ Speed:
– 1MHz Clock Rate, 10ms Write Time
(Current product, identified by process
identification letter F or M)
– 2MHz Clock Rate, 5ms Write Time (New
Product, identified by process
identification letter W or G)
■ Sequential Read Operation
■ Enhanced ESD/Latch-Up Behavior
■ More than 1 Million Erase/Write Cycles
■ More than 40 Year Data Retention
M93S66, M93S56
M93S46
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DS)
3x3mm body size
TSSOP8 (DW)
169 mil width
1/34April 2004
M93S66, M93S56, M93S46
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
POWER-ON DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Instruction Set for the M93S46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 3. Instruction Set for the M93S66, M93S56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. READ, WRITE, WEN and WDS Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. PAWRITE and WRAL Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. PREAD, PRWRITE and PREN Sequenc es. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. PRCLEAR and PRDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WRITE PROTECTION AND THE PROTECTION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
Protection Register Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
Protection Register Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Operating Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Operating Conditions (M93Sx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Operating Conditions (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. A C Measurem ent Condition s (M93Sx6 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. A C Measurem ent Condition s (M93Sx6-W and M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . 17
2/34
M93S66, M93S56, M93S46
Figure 9. AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. DC Characteristics (M93Sx6, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. DC Characteristics (M93Sx6, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. DC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. DC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. DC Characteristics (M93Sx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. AC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. AC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 19. AC Characteristics (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10.Synchronous Timing (Start and Op-Code Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . .28
Table 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mec hanical Data . . . . . . . . . . 28
Figure 14.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 29
Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
29
Figure 15.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm ² body size, Package Outline
30
Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
30
Figure 16.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 31
Table 23. TSSOP8 – 8 lead Thin Shrink Sma ll Outline, Packag e Mechani cal Data . . . . . . . . . . . . 31
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 24.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 25. How to Identify Current and New Products by the Process Identification Letter . . . . . . . 32
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 26. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3/34
M93S66, M93S56, M93S46
SUMMARY DESCRIPTION
This specification covers a range of 4K, 2K, 1K bit
serial Electrically Erasable Programmable Memory (EEPROM) products (respectively for M93S66,
M93S56, M93S46). In this text, these products are
collectively referred to as M93Sx6.
Figure 2. Logic Diagram
V
CC
D
C Q
S
PRE
W
Table 1. Signal Names
S Chip Select Input
D Serial Data Input
Q Serial Data Output
C Ser ial Clock
M93Sx6
V
SS
AI02020
and instructions used to set the memory protection. These are summarized in Table 2. and Table
3.).
A Read Data from Memory (READ) instruction
loads the address of the first word to be read into
an internal address pointer. The data contained at
this address is then clocked out serially. The address pointer is automatically incremented after
the data is output and, if the Chi p S elect In put (S)
is held High, the M93Sx6 can output a sequential
stream of data words. In this way, the memory can
be read as a data stream from 16 to 4096 bits (for
the M93S66), or continuously as the address
counter automatically rolls over to 0 0h when the
highest address is reached.
Within the time required by a programming cycle
), up to 4 words may be written with help of the
(t
W
Page Write instruction. the whole memory may
also be erased, or set to a predetermined pattern,
by using the Write All instruction.
Within the memory, a user defined area may be
protected against further Write instructions. The
size of this area is defined by the content of a Protection Register, located outside of the memory array. As a final protection step, data may be
permanently protected by programming a One
Time Programming bit (OTP bit) which lo cks the
Protection Register content.
Programming is internally s elf-timed (the external
clock signal on Serial Clock (C) may be stopped or
left running after the start of a Write cycle) and
does not require an erase cycle prior to the Write
instruction. The Write instruction writes 16 bits at a
time into one of the word locations of the M93Sx6,
the Page Write instruction writes up to 4 words of
16 bits to sequential locations, assum ing in both
cases that all addresses are outside the Write Protected area. After the start of the programming cycle, a Busy/Ready signal is available on Serial
Data Output (Q) when Chip Select Input (S) is driven High.
PRE Protection Register Enable
W Write Enable
V
CC
V
SS
Supply Voltage
Ground
The M93Sx6 is accessed through a serial input (D)
and output (Q) us in g t he M ICR OWI RE b us protocol. The memory is divided into 256, 128, 64 x16
bit words (respectively for M93S66, M93S56,
M93S46).
The M93Sx6 is accessed by a set of instructions
which includes Read, W rite, Page Write, Write A ll
4/34
Figure 3. DIP, SO and TSSOP Connections
M93Sx6
SV
1
2
D
3
Q
4
Note: See PACKAGE MECHANICAL section for package dimen-
sions, and how to ident i fy pi n-1.
8
7
6
5
AI02021
PREC
W
V
CC
SS
M93S66, M93S56, M93S46
An internal Power-on Data Protec tion m echani sm
in the M93Sx6 inhibits the device when the supply
is too low.
POWER-ON DATA PROTECTION
To prevent data corruption and inadvertent write
operations during power-up, a Power-On Reset
(POR) circuit resets all internal programming circuitry, and sets the device in the Write Disable
mode.
– At Power-up and Power-down, the device
must not be selected (that is, Chip Select Input
(S) must be driven Low) until the supply
voltage reaches the operating value V
specified in Table 5. to Table 6..
– When V
reaches its valid level, the device is
CC
properly reset (in the Write Disable mode) and
is ready to decode and execute incoming
instructions.
For the M93Sx6 devices (5V range) the POR
threshold voltage is around 3 V. For the M93S x6W (3V range) and M93Sx6-R (2V range) the POR
threshold voltage is around 1.5V.
CC
INSTRUCTIONS
The instruction set of the M93Sx6 devices contains seven instructions, as summarized in Table
2. to Table 3.. Each instruction co nsists of t he fol-
lowing parts, as shown in Figure 4.:
■ Each instruction is preceded by a rising edge
on Chip Select Input (S) with Serial Clock (C)
being held Low.
■ A start bit, which is the first ‘1’ read on Serial
Data Input (D) during the rising edge of Serial
Clock (C).
■ Two op-code bits, read on Serial Data Input
(D) during the rising edge of Serial Clock (C).
(Some instructions also use the first two bits of
the address to define the op-code).
■ The address bits of the byte or word that is to
be accessed. For the M93S46, the address is
made up of 6 bits (see Table 2.). Fo r t h e
M93S56 and M93S66, the address is made up
of 8 bits (see Table 3.).
The M93Sx6 devices are fabricated in CMOS
technology and are therefore able to run as slow
as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table 16. to Table 19..
5/34
M93S66, M93S56, M93S46
Table 2. Instruction Set for the M93S46
Instruction Description W PRE
Start
bit
Op-
Code
Address
1
Data
Required
Clock
Cycles
Additional
Comments
READ
WRITE
PAWRITE
WRAL
WEN Write Enable 1 0 1 00 11 XXXX 9
WDS Write Disable X 0 1 00 00 XXXX 9
PRREAD
PRWRITE
PRCLEAR
Read Data
from Memory
Write Data to
Memory
Page Write to
Memory
Write All
Memory
with same
Data
Protection
Register Read
Protection
Register Write
Protection
Register Clear
X 0 1 10 A5-A0 Q15-Q0
1 0 1 01 A5-A0 D15-D0 25
10 1 11 A5-A0
10 1 0001 XXXXD15-D0 25
X 1 1 10 XXXXXX
11 1 01 A5-A0 9
1 1 1 11 111111 9
N x
D15-D0
Q5-Q0
+ Flag
9 + N x 16
Write is executed if
the address is not
inside the Protected
area
Write is executed if
all the N addresses
are not inside the
Protected area
Write all data if the
Protection Register
is cleared
Data Output =
Protection Register
content + Protection
Flag bit
Data above specified
address A5-A0 are
protected
Protect Flag is also
cleared (cleared
Flag = 1)
PREN
PRDS
Note: 1. X = Don’t Care bit.
6/34
Protection
Register
Enable
Protection
Register
Disable
1 1 1 00 11XXXX 9
1 1 1 00 000000 9
OTP bit is set
permanently
Table 3. Instruction Set for the M93S66, M93S56
Instruction Description W PRE
Start
bit
Op-
Code
Address
1,2
M93S66, M93S56, M93S46
Data
Required
Clock
Cycles
Additional
Comments
READ
WRITE
PAWRITE
Read Data
from Memory
Write Data to
Memory
Page Write to
Memory
X 0 1 10 A7-A0 Q15-Q0
1 0 1 01 A7-A0 D15-D0 27
10 1 11 A7-A0
N x
D15-D0
11 + N x 16
Write All
WRAL
Memory
with same
1 0 1 00 01XXXXXX D15-D0 27
Data
WEN Write Enable 1 0 1 00 11XXXXXX 11
WDS Write Disable X 0 1 00 00XXXXXX 11
PRREAD
PRWRITE
PRCLEAR
Protection
Register Read
Protection
Register Write
Protection
Register Clear
X 1 1 10 XXXXXXXX
11 1 01 A7-A0 11
1 1 1 11 11111111 11
Q7-Q0
+ Flag
Protection
PREN
Register
1 1 1 00 11XXXXXX 11
Enable
Write is executed if
the address is not
inside the
Protected area
Write is executed if
all the N
addresses are not
inside the
Protected area
Write all data if the
Protection
Register is cleared
Data Output =
Protection
Register content +
Protection Flag bit
Data above
specified address
A7-A0 are
protected
Prot ect Flag i s als o
cleared (cleared
Flag = 1)
PRDS
Register
1 1 1 00 00000000 11
Disable
Note: 1. X = Don’t Care bit.
2. Address bit A7 is not decoded by t he M 93S56.
Protection
OTP bit is set
permanently
7/34
M93S66, M93S56, M93S46
Figure 4. READ, WRITE, WEN and WDS Sequences
PREREAD
S
WRITE
D
Q
PRE
W
S
D
Q
1 1 0 An A0
ADDR
OP
CODE
1 0An A0
ADDR
OP
CODE
Qn Q0
DATA OUT
Dn D01
DATA IN
CHECK
STATUS
BUSY READY
WRITE
ENABLE
Note: For the meanings of An, Xn, Qn and Dn, see Table 2. and Table 3..
PRE
W
S
D
1
0XnX0
101
OP
CODE
8/34
WRITE
DISABLE
PRE
S
D
1
0XnX0
0 00
OP
CODE
AI00889D
M93S66, M93S56, M93S46
Read
The Read Data from Memory (READ) instruction
outputs serial data on Serial Data Output (Q).
When the instruction is received, the op-code and
address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 16-bit word,
with the most significant bit first. Output data
changes are triggered b y the rising edge of Se rial
Clock (C). The M93Sx6 automatically incremen ts
the internal address register and clocks out the
next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit
is not output between bytes (or words) and a continuous stream of data can be read.
Write Enable and Write Disable
The Write Enable (WEN) instruction enables the
future execution of write instructions, and the Write
Disable (WDS) instruction disables it. When power
is first app lied, the M93 S x 6 in i tializes itse lf so that
write instructions are disabled. After an Write Enable (WEN) instruction has been executed, writing
remains enabled until an Write Disable (WDS) instruction is executed, or until V
falls below the
CC
power-on reset threshold voltage . To protect the
memory contents from accidental corruption, it is
advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read Data
from Memory (READ) instruction is not affected by
the Write Enable (WEN) or Write Disable (WDS)
instructions.
Write
The Write Data to Memory (WRITE) instruction is
composed of the Start bit plus the op-code followed by the address and the 16 data bits to be
written.
Write Enable (W) must be held High before and
during the instruction. Input addres s and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has been sampled, the C hip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started, and the addressed location will not be
programmed.
While the M93Sx6 is performing a write cycle, but
after a delay (t
) before the status information
SLSH
becomes available, Chip S elect Input (S) can be
driven High to monitor the status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx6 ignores any data on
the bus while it is busy on a wri te cycle. O nce t he
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state until a new start bit
is decoded or the Chip Select I nput (S) is brought
Low.
Programming is internally self-timed, so the external Serial Clock (C) may be disconnected o r left
running after the start of a write cycle.
9/34
M93S66, M93S56, M93S46
Figure 5. PA WR I TE and W R AL Sequen ce
PAGE WRITE
WRITE
ALL
PRE
W
S
D
Q
PRE
W
1 1An A0
ADDR
OP
CODE
CHECK
STATUS
Dn D01
DATA IN
BUSY READY
S
D
Q
Note: F or the mea ni ngs of An, Xn and Dn, please see Tabl e 2. and Table 3..
Page Write
A Page Write to Memory (PAWRITE) instruction
contains the first address to be written, followed by
up to 4 data words.
After the receipt of each data w ord, bits A1-A 0 of
the internal address regist er are increm ent ed, the
high order bits remaining unchanged (A7-A2 for
M93S66, M93S56; A5-A2 for M93S46). Users
must take care, in the software, to ensure that the
last word address has the same upper order address bits as the initial address transmitted to
avoid address roll-over.
01
1 0XnX0
ADDR
OP
CODE
Dn D00
DATA IN
The Page Write to Memory (PAWRITE) instruction
will not be executed if any of the 4 words addresses the protected area.
Write Enable (W) must be held High before and
during the instruction. Input addres s and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has been sampled, the C hip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
CHECK
STATUS
BUSY READY
AI00890C
10/34
M93S66, M93S56, M93S46
be started, and the addressed location will not be
programmed.
While the M93Sx6 is performing a write cycle, but
after a delay (t
) before the status information
SLSH
becomes available, Chip S elect Input (S) can be
driven High to monitor the status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 i s ready to receive a
new instruction. The M93Sx6 ignores any data on
the bus while it is busy on a wri te cycle. O nce t he
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state until a new start bit
is decoded or the Chip Select I nput (S) is brought
Low.
Programming is internally self-timed, so the external Serial Clock (C) may be disconnected o r left
running after the start of a write cycle.
Writ e All
The Write All Memory with same Data (WRAL) instruction is valid only after the Protection Register
has been cleared by executing a Protection Register Clear (PRCLEAR) instruction. The Write All
Memor y with same Data (WRAL) instructi on simultaneously writes the whole memory with the same
data word given in the instruction.
Write Enable (W) must be held High before and
during the instruction. Input addres s and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has been sampled, the C hip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started, and the addressed location will not be
programmed.
While the M93Sx6 is performing a write cycle, but
after a delay (t
) before the status information
SLSH
becomes available, Chip S elect Input (S) can be
driven High to monitor the status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx6 ignores any data on
the bus while it is busy on a wri te cycle. O nce t he
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state until a new start bit
is decoded or the Chip Select I nput (S) is brought
Low.
Programming is internally self-timed, so the external Serial Clock (C) may be disconnected o r left
running after the start of a write cycle.
11/34
M93S66, M93S56, M93S46
Figure 6. PREAD, PRWRITE and PREN Sequences
Register
READ
Protect
Register
WRITE
PREProtect
S
D
Q
PRE
W
S
1 1 0 Xn X0
ADDR
OP
CODE
1 0An A0D
1
An A0 F
DATA
OUT
CHECK
STATUS
F = Protect Flag
Q
ADDR
OP
CODE
Protect
Register
ENABLE
Note: F or the mea ni ngs of An, Xn and Dn, please see Tabl e 2. and Table 3..
PRE
W
S
D
1
0XnX0
101
OP
CODE
BUSY READY
AI00891D
12/34
Figure 7. PRCLEAR and PRDS Sequences
M93S66, M93S56, M93S46
Protect
Register
CLEAR
Protect
Register
DISABLE
PRE
W
S
Q
PRE
W
S
1 1D
1
OP
CODE
1 0D
0
ADDR
CHECK
STATUS
111
BUSY READY
CHECK
STATUS
000
Q
ADDR
OP
CODE
Note: F or the mea ni ngs of An, Xn and Dn, please see Tabl e 2. and Table 3..
BUSY READY
AI00892C
13/34
M93S66, M93S56, M93S46
WRITE PROTECTION AND THE PROTECTION REGISTER
The Protection Register on the M93Sx6 is used to
adjust the amount of memory t hat is to be write
protected. The write protected area extends from
the address given in the Protection Register, up to
the top address in the M93Sx6 device.
Two flag bits are used t o indicate the Protection
Register status:
– Protection Flag: this is used to enable/disable
protection of the write-protected area of the
M93Sx 6 memory
– OTP bit: when set, this disables access to the
Protection Register, and thus prevents any
further modifications to the value in the
Protection Register.
The lower-bound memory address is written to the
Protection Register using the Protection Register
Write (PRWRITE) instruction. It can be read using
the Protection Register Read (PRREAD) instruction.
The Protection Register Enable (PREN) instruction must be executed before any PRCLEAR,
PRWRITE or PRDS instruction, and with appropriate levels applied to the Protection Enable (PRE)
and Write Enable (W) signals.
Write-access to the Protection Register is
achieved by executing the following sequence:
– Execute the Write Enable (WEN) instruction
– Execute the Protection Register Enable
(PREN) instruction
– Execute one PRWRITE, PRC L EAR or PRDS
instructions, to set a new boundary address in
the Protection Register, to clear the protection
address (to all 1s), or permanently to freeze
the value held in the Protection Register.
Protection Register Read
The Protection Register Read (PRREAD) instruction outputs, on Serial Data Output (Q), the content of the Protection Register, followed by the
Protection Flag bit. The Protection Enable (PRE)
signal must be driven High before and during the
instruction.
As with the Read Data from Memory (READ) instruction, a dummy 0 bit is output first. Since it is
not possible to distinguish between the Protection
Register being cleared (all 1s) or having been written with all 1s, the user must check the Protection
Flag status (and no t the Protection Register c ontent) to ascertain the setting of the memory protection.
Protection Register Enable
The Protection Register Enable (PREN) instruction is used to authorize the use of instructions that
modify the Protection Register (PRWRITE,
PRCLEAR, PRDS). The Protection Register En-
able (PREN) instruction does not modify the Protection Flag bit value.
Note: A Write Enable (WEN) instruction must be
executed before the Protection Register Enable
(PREN) instruction. Both the Protection Enable
(PRE) and Write Enable (W) signals must be driven High during the instruction execution.
Protection Register Clear
The Protection Register Clear (PRCLEAR) instruction clears the address stored in the Protection Register to all 1s, so that none of the memory
is write-protected by the Protection Register. However, it should be noted that all the memory remains protected, in the normal way, using the
Write Enable (WEN) and Write Disable (WDS) instructions.
The Protection Register Clear (PRCLEAR) instruction clears the Protec tion Flag to 1. Both t he
Protection Enable (PRE) and Write Enable (W)
signals must be driven High during the instruction
execution.
Note: A Protection Register Enable (PREN) instruction must immediately precede the Protection
Register Clear (PRCLEAR) instruction.
Prot e ction Re gister Write
The Protection Register Write (PRWRITE) instruction is used to write an address into the Protection
Register. This is the address of t he first word to be
protected. After the Protection Register Write
(PRWRITE) instruction has been executed, all
memory locations equal to and above the specified address are protected from writing.
The Protection Flag bit is set to 0, and can be read
with Protection Register Read (PRREAD) instruction. Both the Protection Enable (PRE) and Write
Enable (W) signals must be driven High during the
instruction execution.
Note: A Protection Register Enable (PREN) instruction must immediately precede the Protection
Register Write (PRWRITE) instruction, but it is not
necessary to execute first a Protection Register
Clear (PRCLEAR).
Protection Register Disable
The Protection Register Disable (PRDS) instruction sets the One T ime Programmable (OTP) bit.
This inst ruction is a ON E TIME ONLY instr uction
which latches the Protection Register content, this
content is therefore unalterable in the future. Both
the Protection Enable (PRE) and Write Enable (W)
signals must be driven High during the instruction
execution. The OTP bit can not be di rectly read, it
can be checked by reading the content of the Protection Register, using the Protection Register
Read (PRREAD) instruction, then by writing this
same value back into the Protection Register, us-
14/34
M93S66, M93S56, M93S46
ing the Protection Register Write (PRWRITE) instruction. When the OTP bit is set, the Ready/Busy
status cannot appear on Serial Data Outp ut (Q).
When the OTP bit is not set, the Busy status appears on Serial Data Output (Q).
Note: A Protection Register Enable (PREN) instruction must immediately precede the Protection
Register Disable (PRDS) instruction.
Figure 8. Write Sequence with One Clock Glitch
S
C
D
An
START
WRITE
COMMON I/O OPERATION
Serial Data Output (Q) and Serial Da ta Input (D)
can be connected together, thro ugh a current limiting resistor, to form a common, single-wire data
bus. Some precautions must be taken when operating the memory in this way, mostly to prevent a
short circuit current from flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output (Q). Please see the application
note AN394 for details.
An-1
Glitch
An-2
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
D0"1""0"
AI01395
CLOCK PU LSE COUNTER
In a noisy environment, the number of p ulses received on Serial Clock (C) may be greater than the
number delivered by the Bus Master (the microcontroller). This can lead to a misalignm ent of t he
instruction of one or more bits (as shown in Figure
8.) and may lead to the writing of erroneous data
at an erroneous address.
To combat this problem, the M93Sx 6 has an on-
chip counter that counts the clock pulses from the
start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses received is
not the number expected, th e WRITE , P AW RITE,
WRALL, PRWRITE or PRCLEAR instruction is
aborted, and the contents of the memory are not
modified.
The number of clock cycles expected for each instruction, and for each member of the M93Sx6
family, are summarized in Table 2. to Table 3.. For
example, a Write Data to Memory (WRITE) instruction on the M93S56 (or M93S66) expects 27
clock cycles from the start bit to the falling edge of
Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 8 Address bits
+ 16 Data bits
15/34
M93S66, M93S56, M93S46
MAXIMUM RA T ING
Stressing the device above the rating l isted in t he
Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress
ratings only and operation of the device at t hese or
any other conditions ab ove those i ndicated in t he
Operating sections of this specificat ion is not im-
Table 4. Absolute Maximum Ratings
Symbol Parameter Min. Max. Unit
T
T
STG
LEAD
Storage Temperature –65 150 °C
Lead Temperature during Soldering
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevan t quality documents.
See note
1
°C
V
OUT
V
IN
V
CC
V
ESD Electrostatic Discharge Voltage (Human Body model)
Note: 1. Compliant wit h JED EC Std J- STD- 020 B (for small bod y, Sn-Pb or Pb asse mbl y), the ST ECOP ACK® 71913 95 specification, and
the European directive on Restri ct i ons on Hazardous Sub st ances (RoH S ) 2002/95/EU
2. JEDEC Std J E SD 22-A114A (C1=100 pF, R1=1500
Output range (Q = VOH or Hi-Z)
–0.50 V
+0.5 V
CC
Input range –0.50 VCC+1 V
Supply Voltage –0.50 6.5 V
2
Ω, R2=500 Ω)
–4000 4000 V
16/34
M93S66, M93S56, M93S46
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC Characteristic tables that follow are derived from tests performed under the Measure-
Table 5. Operating Conditions (M93Sx6)
Symbol Parameter Min. Max. Unit
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match t he measurem ent
conditions when relying on the quoted parameters.
V
CC
Supply Voltage 4.5 5.5 V
Ambient Operating Temperature (Device Grade 6) –40 85 °C
T
A
Ambient Operating Temperature (Device Grade 3) –40 125 °C
Table 6. Operating Conditions (M93Sx6-W)
Symbol Parameter Min. Max. Unit
V
CC
T
A
Supply Voltage 2.5 5.5 V
Ambient Operating Temperature (Device Grade 6) –40 85 °C
Table 7. Operating Conditions (M93Sx6-R)
Symbol Parameter Min. Max. Unit
V
CC
T
A
Supply Voltage 1.8 5.5 V
Ambient Operating Temperature (Device Grade 6) –40 85 °C
Table 8. AC Measurement Conditions (M93Sx6)
Symbol Parameter Min. Max. Unit
C
L
Load Capacitance 100 pF
Input Rise and Fall Times 50 ns
Input Pulse Voltages 0.4 V to 2.4 V V
Input Timing Reference Voltages 1.0 V and 2.0 V V
Output Timing Reference Voltages 0.8 V and 2.0 V V
Note: Output Hi-Z is defined as the point where dat a out is no long er driven.
Table 9. AC Measurement Conditions (M93Sx6-W and M93Sx6 -R)
Symbol Parameter Min. Max. Unit
C
L
Note: Output Hi-Z is defined as the point where dat a out is no long er driven.
Load Capacitance 100 pF
Input Rise and Fall Times 50 ns
0.2V
0.3V
0.3V
to 0.8V
CC
to 0.7V
CC
to 0.7V
CC
CC
CC
CC
Input Pulse Voltages
Input Timing Reference Voltages
Output Timing Reference Voltages
V
V
V
17/34
M93S66, M93S56, M93S46
Figure 9. AC Testing Input Output Waveforms
M93SXX
2V
1V
M93SXX-W & M93SXX-R
2.0V
0.8V
0.7V
0.3V
AI02791
CC
CC
0.8V
0.2V
2.4V
0.4V
INPUT OUTPUT
CC
CC
Table 10. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
OUT
C
IN
Note: Sampled only, not 10 0% tested, at TA=25°C an d a frequency of 1 M Hz .
Output
Capacitance
Input
Capacitance
V
OUT
V
IN
= 0V
= 0V
5pF
5pF
18/34
M93S66, M93S56, M93S46
Table 11. DC Characteristics (M93Sx6, Device Grade 6)
Symbol Parameter Test Condition Min. Max. Unit
0V
≤ V
I
I
I
LO
CC
Input Leakage Curren t
LI
Output Leakage Current
Supply Current
0V
≤ V
OUT
V
= 5V, S = VIH, f = 1 MHz, Current
CC
V
= 5V, S = VIH, f = 2 MHz, New
CC
V
= 5V, S = VSS, C = VSS,
CC
Current Product
I
CC1
Supply Current (Stand-by)
V
= 5V, S = VSS, C = VSS,
CC
New Product
V
V
V
V
Note: 1. Current product: identified by Process Identification letter F or M.
Input Low Voltage
IL
Input High Voltage
IH
Output Low Voltage
OL
Output High Voltage
OH
2. New product: id entified by Pr ocess Identification l etter W or G .
V
V
V
= 5V, IOL = 2.1mA
CC
V
= 5V, IOH = –400µA
CC
≤ V
IN
CC
≤ VCC, Q in Hi-Z
1
Product
2
Product
2
= 5V ± 10%
CC
= 5V ± 10%
CC
±2.5 µA
±2.5 µA
1.5 mA
2 mA
1
50 µA
15 µA
–0.45 0.8 V
2
VCC + 1
0.4 V
2.4 V
V
Table 12. DC Characteristics (M93Sx6, Device Grade 3)
Symbol Parameter Test Condition Min. Max. Unit
0V
≤ V
I
I
I
LO
CC
Input Leakage Curren t
LI
Output Leakage Current
Supply Current
0V
≤ V
OUT
= 5V, S = VIH, f = 1 MHz, Current
V
CC
V
= 5V, S = VIH, f = 2 MHz, New
CC
V
= 5V, S = VSS, C = VSS,
CC
Current Product
I
CC1
Supply Current (Stand-by)
V
= 5V, S = VSS, C = VSS,
CC
New Product
V
V
V
V
Note: 1. Current product: identified by Process Identification letter F or M.
Input Low Voltage
IL
Input High Voltage
IH
Output Low Voltage
OL
Output High Voltage
OH
2. New product: id entified by Pr ocess Identification l etter W or G .
V
V
V
= 5V, IOL = 2.1mA
CC
V
= 5V, IOH = –400µA
CC
≤ V
IN
CC
≤ VCC, Q in Hi-Z
1
Product
2
Product
2
= 5V ± 10%
CC
= 5V ± 10%
CC
±2.5 µA
±2.5 µA
1.5 mA
2 mA
1
50 µA
15 µA
–0.45 0.8 V
2
VCC + 1
0.4 V
2.4 V
V
19/34
M93S66, M93S56, M93S46
Table 13. DC Characteristics (M93Sx6-W, Device Grade 6)
Symbol Parameter Test Condition Min. Max. Unit
0V
≤ V
I
I
I
LO
CC
Input Leakage Current
LI
Output Leakage Current
Supply Current (CMOS
Inputs)
0V
≤ V
OUT
= 5V, S = VIH, f = 1 MHz, Current
V
CC
V
= 2.5V, S = VIH, f = 1 MHz, Current
CC
V
= 5V, S = VIH, f = 2 MHz, New
CC
V
= 2.5V, S = VIH, f = 2 MHz, New
CC
V
= 2.5V, S = VSS, C = VSS,
CC
Current Product
I
CC1
Supply Current (Stand-by)
V
= 2.5V, S = VSS, C = VSS,
CC
New Product
V
V
V
V
Note: 1. Current product: identified by Process Identification letter F or M.
Input Low Voltage (D, C, S) –0.45
IL
Input High Voltage (D, C, S)
IH
V
= 5V, IOL = 2.1mA
Output Low Voltage (Q)
OL
Output High Voltage (Q)
OH
2. New product: id entified by Pr ocess Identification l etter W or G .
CC
= 2.5V, IOL = 100µA
V
CC
V
= 5V, IOH = –400µA
CC
V
= 2.5V, IOH = –100µA VCC–0.2
CC
≤ V
IN
CC
≤ VCC, Q in Hi-Z
1
Product
1
Product
2
Product
2
Product
1
2
±2.5 µA
±2.5 µA
1.5 mA
1 mA
2 mA
1 mA
10 µA
5 µA
0.2 V
CC
0.7 V
CC
VCC + 1
0.4 V
0.2 V
2.4 V
V
V
V
20/34
M93S66, M93S56, M93S46
Table 14. DC Characteristics (M93Sx6-W, Device Grade 3)
Symbol Parameter Test Condition
0V
≤ V
I
I
I
I
CC1
V
V
V
V
Note: 1. New product: id entified by Pr ocess Iden t ifi cation letter W or G.
LO
CC
Input Leakage Current
LI
0V
Output Leakage Current
Supply Current (CMOS
Inputs)
Supply Current (Stand-by)
Input Low Voltage (D, C, S) –0.45
IL
Input High Voltage (D, C, S)
IH
Output Low Voltage (Q)
OL
Output High Voltage (Q)
OH
≤ V
OUT
V
= 5V, S = VIH, f = 2 MHz
CC
V
= 2.5V, S = VIH, f = 2 MHz
CC
V
= 2.5V, S = VSS, C = V
CC
V
= 5V, IOL = 2.1mA
CC
V
= 2.5V, IOL = 100µA
CC
V
= 5V, IOH = –400µA
CC
= 2.5V, IOH = –100µA VCC–0.2
V
CC
≤ V
IN
CC
≤ VCC, Q in Hi-Z
SS
Table 15. DC Characteristics (M93Sx6-R)
Symbol Parameter Test Condition
0V
≤ V
I
I
I
I
CC1
V
V
V
V
Note: 1. Preliminary Data: this pr oduct is under developm ent. For mo re infomat i on, pl ease conta ct your nearest ST sales off i ce.
LO
CC
Input Leakage Current
LI
0V
Output Leakage Current
Supply Current (CMOS
Inputs)
Supply Current (Stand-by)
Input Low Voltage (D, C, S) –0.45
IL
Input High Voltage (D, C, S)
IH
Output Low Voltage (Q)
OL
Output High Voltage (Q)
OH
≤ V
OUT
V
= 5V, S = VIH, f = 2 MHz
CC
V
= 1.8V, S = VIH, f = 1 MHz
CC
V
= 1.8V, S = VSS, C = V
CC
V
= 1.8V, IOL = 100µA
CC
V
= 1.8V, IOH = –100µA VCC–0.2
CC
≤ V
IN
CC
≤ VCC, Q in Hi-Z
SS
1
Min
.Max.
±2.5 µA
±2.5 µA
2 mA
1 mA
5 µA
0.2 V
CC
0.7 V
CC
VCC + 1
0.4 V
0.2 V
2.4 V
V
1
Min.
Max.
±2.5 µA
±2.5 µA
2 mA
1 mA
2 µA
0.2 V
CC
0.8 V
CC
VCC + 1
0.2 V
V
1
Unit
V
V
1
Unit
V
V
21/34
M93S66, M93S56, M93S46
Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3)
Test conditions specified in Table 8. and Table 5.
Symbol Alt. Parameter
f
C
t
PRVCH
t
WVCH
t
CLPRX
t
SLWX
f
SK
t
PRES
t
PES
t
PREH
t
PEH
Clock Frequency D.C. 1 D.C. 2 MHz
Protect Enable Valid to Clock High 50 50 ns
Write Enable Valid to Clock High 50 50 ns
Clock Low to Protect Enable Transition 0 0 ns
Chip Select Low to Write Enable
Transition
Min.
250 250 ns
3
Max.
3
Min.
4
Max.
4
Unit
t
SLCH
t
SHCH
2
t
SLSH
1
t
CHCL
1
t
CLCH
t
DVCH
t
CHDX
t
CLSH
t
CLSL
t
SHQV
t
SLQZ
t
CHQL
t
CHQV
t
W
Note: 1. t
CHCL
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between co nsecutive in st ruction cy cl es.
3. Current product: identified by Process Identification letter F or M.
4. New product: id entified by Pr ocess Identification l etter W or G .
Chip Select Low to Clock High 250 50 ns
+ t
t
CSS
t
t
SKH
t
SKL
t
DIS
t
DIH
t
SKS
t
CSH
t
t
t
PD0
t
PD1
t
WP
Chip Select Set-up Time
M93C46, M93C56, M93C66
Chip Select Set-up time
M93C76, M93C86
Chip Select Low to Chip Select High 250 200 ns
CS
Clock High Time 250 200 ns
Clock Low Time 250 200 ns
Data In Set-up Time 100 50 ns
Data In Hold Time 100 50 ns
Clock Set-up Time (relative to S) 100 50 ns
Chip Select Hold Time 0 0 ns
Chip Select to Ready/Busy Status 400 200 ns
SV
Chip Select Low to Output Hi-Z 200 100 ns
DF
Delay to Output Low 400 200 ns
Delay to Output Valid 400 200 ns
Erase/Write Cycle time 10 5 ms
≥ 1 / fC.
CLCH
50 50 ns
100 50 ns
22/34
Table 17. AC Characteristics (M93Sx6-W, Device Grade 6)
Test conditions specified in Table 9. and Table 6.
Symbol Alt. Parameter
f
C
t
PRVCH
t
WVCH
t
CLPRX
t
SLWX
f
SK
t
PRES
t
PES
t
PREH
t
PEH
Clock Frequency D.C. 1 D.C. 2 MHz
Protect Enable Valid to Clock High 50 50 ns
Write Enable Valid to Clock High 50 50 ns
Clock Low to Protect Enable Transition 0 0 ns
Chip Select Low to Write Enable
Transition
Min.
250 250 ns
M93S66, M93S56, M93S46
3
Max.
3
Min.
4
Max.
4
Unit
t
SLCH
t
SHCH
2
t
SLSH
1
t
CHCL
1
t
CLCH
t
DVCH
t
CHDX
t
CLSH
t
CLSL
t
SHQV
t
SLQZ
t
CHQL
t
CHQV
t
W
Note: 1. t
CHCL
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between co nsecutive in st ruction cy cl es.
3. Current product: identified by Process Identification letter F or M.
4. New product: id entified by Pr ocess Identification l etter W or G .
Chip Select Low to Clock High 250 50 ns
+ t
t
CSS
t
t
SKH
t
SKL
t
DIS
t
DIH
t
SKS
t
CSH
t
t
t
PD0
t
PD1
t
WP
Chip Select Set-up Time 100 50 ns
Chip Select Low to Chip Select High 1000 200 ns
CS
Clock High Time 350 200 ns
Clock Low Time 250 200 ns
Data In Set-up Time 100 50 ns
Data In Hold Time 100 50 ns
Clock Set-up Time (relative to S) 100 50 ns
Chip Select Hold Time 0 0 ns
Chip Select to Ready/Busy Status 400 200 ns
SV
Chip Select Low to Output Hi-Z 200 100 ns
DF
Delay to Output Low 400 200 ns
Delay to Output Valid 400 200 ns
Erase/Write Cycle time 10 5 ms
≥ 1 / fC.
CLCH
23/34
M93S66, M93S56, M93S46
Table 18. AC Characteristics (M93Sx6-W, Device Grade 3)
Test conditions specified in Table 9. and Table 6.
Symbol Alt. Parameter
f
C
t
PRVCH
t
WVCH
t
CLPRX
t
SLWX
t
SLCH
t
SHCH
2
t
SLSH
1
t
CHCL
1
t
CLCH
t
DVCH
t
CHDX
t
CLSH
t
CLSL
t
SHQV
t
SLQZ
t
CHQL
t
CHQV
t
W
Note: 1. t
CHCL
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between co nsecutive in st ruction cy cl es.
3. New product: id entified by Pr ocess Identification l etter W or G .
f
SK
t
PRES
t
PES
t
PREH
t
PEH
Clock Frequency D.C. 2 MHz
Protect Enable Valid to Clock High 50 ns
Write Enable V a lid to Clock High 50 ns
Clock Low to Protect Enable Transition 0 ns
Chip Select Low to Write Enable Transition 250 ns
Chip Select Low to Clock High 50 ns
+ t
CLCH
t
CSS
t
CS
t
SKH
t
SKL
t
DIS
t
DIH
t
SKS
t
CSH
t
SV
t
DF
t
PD0
t
PD1
t
WP
≥ 1 / fC.
Chip Select Set-up Time 50 ns
Chip Select Low to Chip Select High 200 ns
Clock High Time 200 ns
Clock Low Time 200 ns
Data In Set-up Time 50 ns
Data In Hold Time 50 ns
Clock Set-up Time (relative to S) 50 ns
Chip Select Hold Time 0 ns
Chip Select to Ready/Busy Status 200 ns
Chip Select Low to Output Hi-Z 100 ns
Delay to Output Low 200 ns
Delay to Output Valid 200 ns
Erase/Write Cycle time 5 ms
Min.
3
Max.
3
Unit
24/34
M93S66, M93S56, M93S46
Table 19. AC Characteristics (M93Sx6-R)
Test conditions specified in Table 9. and Table 7.
Symbol Alt. Parameter
f
C
t
PRVCH
t
WVCH
t
CLPRX
t
SLWX
t
SLCH
t
SHCH
2
t
SLSH
1
t
CHCL
1
t
CLCH
t
DVCH
t
CHDX
t
CLSH
t
CLSL
t
SHQV
t
SLQZ
t
CHQL
t
CHQV
t
W
Note: 1. t
CHCL
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between co nsecutive in st ruction cy cl es.
3. Prel i m i nary Data: th i s product is un der develo pm ent. For mo re infomati on, please contact your nearest ST sales office .
f
SK
t
PRES
t
PES
t
PREH
t
PEH
Clock Frequency D.C. 1 MHz
Protect Enable Valid to Clock High 50 ns
Write Enable V a lid to Clock High 50 ns
Clock Low to Protect Enable Transition 0 ns
Chip Select Low to Write Enable Transition 250 ns
Chip Select Low to Clock High 250 ns
+ t
CLCH
t
CSS
t
CS
t
SKH
t
SKL
t
DIS
t
DIH
t
SKS
t
CSH
t
SV
t
DF
t
PD0
t
PD1
t
WP
≥ 1 / fC.
Chip Select Set-up Time 50 ns
Chip Select Low to Chip Select High 250 ns
Clock High Time 250 ns
Clock Low Time 250 ns
Data In Set-up Time 100 ns
Data In Hold Time 100 ns
Clock Set-up Time (relative to S) 100 ns
Chip Select Hold Time 0 ns
Chip Select to Ready/Busy Status 400 ns
Chip Select Low to Output Hi-Z 200 ns
Delay to Output Low 400 ns
Delay to Output Valid 400 ns
Erase/Write Cycle time 10 ms
Min.
3
Max.
3
Unit
25/34
M93S66, M93S56, M93S46
Figure 10. Sy nch r o nous Timin g (Sta r t an d Op-Code Inp ut )
PRE
tPRVCH
W
C
tCLSH tCLCH
S
tSHCH
tCHCLtWVCH
tCHDXtDVCH
D
START
Figure 11. Sy nchronou s Ti m in g ( Re ad or Write)
C
S
tDVCH
A0
Hi-Z
An
tCHQL
ADDRESS INPUT
D
Q
OP CODE OP CODESTART
OP CODE INPUT
AI02025
tCHQVtCHDX
tSLQZ
Q15 Q0
DATA OUTPUT
tCLSL
tSLSH
AI002026
26/34
Figure 12. Sy nchronou s Ti m in g ( Re ad or Write)
PRE
W
C
S
M93S66, M93S56, M93S46
tCLPRX
tSLWX
tSLCH
tCLSL
tSLSH
tDVCH
D
Q
An A0/D0
Hi-Z
tCHDX
tSHQV
BUSY
tW
WRITE CYCLEADDRESS/DATA INPUT
tSLQZ
READY
AI02027
27/34
M93S66, M93S56, M93S46
PACKAG E MECHANICA L
Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outlin e
b2
A2
A1AL
be
D
8
E1
1
Note: Drawing is not to scale.
E
c
eA
eB
PDIP-B
Table 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
Symb.
Typ. Min. Max. Typ. Min. Max.
A 5.33 0.210
mm inches
28/34
A1 0.38 0.015
A2 3.30 2.92 4.95 0.130 0.115 0.195
b 0.46 0.36 0.56 0.018 0.014 0.022
b2 1.52 1.14 1.78 0.060 0.045 0.070
c 0.25 0.20 0.36 0.010 0.008 0.014
D 9.27 9.02 10.16 0.365 0.355 0.400
E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7.11 0.250 0.240 0.280
e2.54––0.100––
eA 7.62 – – 0.300 – –
eB 10.92 0.430
L 3.30 2.92 3.81 0.130 0.115 0.150
M93S66, M93S56, M93S46
Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width , Packag e Outline
h x 45˚
Note: Drawing is not to scale.
B
SO-a
A
e
D
N
1
CP
E
H
C
LA1 α
Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
mm inches
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e1.27––0.050––
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N8 8
CP 0.10 0.004
29/34
M93S66, M93S56, M93S46
Figure 15. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
D
8
1
CP
Note: Drawing is not to scale.
5
EE1
4
A2A
A1
eb
L
L1
TSSOP8BM
c
α
Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
Symbol
Typ. Min. Max. Typ. Min. Max.
A 1.100 0.0433
A1 0.050 0.150 0.0020 0.0059
A2 0.850 0.750 0.950 0.0335 0.0295 0.0374
mm inches
30/34
b 0.250 0.400 0.0098 0.0157
c 0.130 0.230 0.0051 0.0091
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
E 4.900 4.650 5.150 0.1929 0.1831 0.2028
E1 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
CP 0.100 0.0039
L 0.550 0.400 0.700 0.0217 0.0157 0.0276
L1 0.950 0.0374
α 0° 6° 0° 6°
M93S66, M93S56, M93S46
Figure 16. TSSOP8 – 8 lead Thin Shrink S mall Outlin e, Packa ge Ou tline
D
8
1
CP
Note: Drawing is not to scale.
5
EE1
4
α
A2A
A1
eb
L
L1
TSSOP8AM
Table 23. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
Symbol
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
mm inches
c
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α 0° 8° 0° 8°
31/34
M93S66, M93S56, M93S46
PART NUMBERING
Table 24. Ordering Information Scheme
Example: M93S66 – W MN 6 T P
Device Type
M93 = MICROWIRE serial access EEPROM (x16) with
Block Protection
Device Function
66 = 4 Kbit (256 x 16)
56 = 2 Kbit (128 x 16)
46 = 1 Kbit (64 x 16)
Operating Voltage
blank = V
W = V
R = V
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
2
DS
= TSSOP8 (3x3mm body size)
= 4.5 to 5.5V
CC
= 2.5 to 5.5V
CC
= 1.8 to 5.5V
CC
Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
1
3 = Automotive: device tested with High Reliability Certified Flow
over –40 to 125 °C
Option
blank = Standard Packing
T = Tape & Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-
tified Flow (HRCF) is described in the quality note QNEE9801 . Please ask your nearest ST sales office for a co py.
2. Available only on new products: identified by the Process Identificati on letter W or G.
Devices are shipped from the factory with the
memory content set at all 1s (FFh).
-free and TBBA-free
2O3
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.
Table 25. How to Identify Current and New Products by the Process Identification Letter
Markings on Current Products
M93S46W6
AYWWF (or AYWWM)
Note: 1. This example co m es from the S0 8 package. Other package s have similar i nformati on. For furth er informati on, please ask your ST
Sales Office for Proces s Change Not i ce PCN MPG/ E E/0059 (PCE E0059).
1
Markings on New Products
M93S46W6
AYWWW (or AYWWG)
1
32/34
REVISION HISTORY
Table 26. Document Revision History
Date Rev. Description of Revision
Document reformatted, and reworded, using the new template. Temperature range 1 removed.
07-Mar-2002 2.0
26-Mar-2003 2.1
14-Apr-2003 2.2
23-May-2003 2.3
24-Nov-2003 3.0
19-Apr-2004 4.0
TSSOP8 (3x3mm) package added. New products, identified by the process letter W, added,
with fc(max) increased to 1MHz for -R voltage range, and to 2MHz for all other ranges (and
corresponding parame ters adjuste d).
Value of standby current (max) corrected in DC characteristics tables for -W and -R ranges
V
and VIN separated from VIO in the Absolute Maximum Ratings table
OUT
Values corrected in AC characteristics tables for -W range (tSLSH, tDVCH, tCLSL) for devices
with Process Identification Letter W.
Standby current corrected for -R range. Four missing parameters restored to all AC
Characteristics tables
Table of contents, and Pb-free options added. V
Absolute Maximum Ratings for V
information clarified for RoHS compliant devices. Device Grade 3 clarified, with reference to
HRCF and automotive environments. Process identification letter “G” information added
(min) and VCC(min) changed. Soldering temperature
IO
M93S66, M93S56, M93S46
(min) improved to -0.45V.
IL
33/34
M93S66, M93S56, M93S46
Information furnished is believed to be accurate and reliable. However, STMicroelectronics a ssumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are sub j ect
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authori zed for use as critical com ponents in lif e support devices or systems with out express written approval of ST M i croelectro nics.
The ST logo is a registered trademark of STMicroelectronics.
All other na m es are the property of their respective owners.
© 2004 STMi croelectronics - All ri ghts reser ved
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34/34
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