STMicroelectronics M5450, M5451 User Manual

M5450

M5451

LED DISPLAY DRIVERS

FEATURES SUMMARY

■M5450 34 OUTPUTS/15mA SINK

■M5451 35 OUTPUTS/15mA SINK

■CURRENT GENERATOR OUTPUTS (NO EXTERNAL RESISTORS REQUIRED)

■CONTINUOUS BRIGHTNESS CONTROL

■SERIAL DATA INPUT

■ENABLE (ON M5450)

■WIDE SUPPLY VOLTAGE OPERATION

■TTL COMPATIBILITY

Application Examples:

■MICROPROCESSOR DISPLAYS

■INDUSTRIAL CONTROL INDICATOR

■RELAY DRIVER

■INSTRUMENTATION READOUTS

DESCRIPTION

The M5450 and M5451 are monolithic MOS integrated circuits produced with an N-channel silicon gate technology. They are available in 40-pin dual in-line plastic packages.

A single pin controls the LED display brightness by setting a reference current through a variable resistor connected to VDD or to a separate supply of 13.2V maximum.

Figure 1. Packages

40

1

PDIP40

(Plastic Package)

PLCC44

(Plastic Chip Carrier)

	REV. 2
April 2004	1/12

M5450, M5451

Figure 2. Pin Connection

VSS		1	40		OUTPUT BIT 18
OUTPUT BIT 17		2	39		OUTPUT BIT 19
OUTPUT BIT 16		3	38		OUTPUT BIT 20
OUTPUT BIT 15		4	37		OUTPUT BIT 21
OUTPUT BIT 14		5	36		OUTPUT BIT 22
OUTPUT BIT 13		6	35		OUTPUT BIT 23
OUTPUT BIT 12		7	34		OUTPUT BIT 24
OUTPUT BIT 11		8	33		OUTPUT BIT 25
OUTPUT BIT 10		9	32		OUTPUT BIT 26
OUTPUT BIT 9		10	31		OUTPUT BIT 27
OUTPUT BIT 8		11	30		OUTPUT BIT 28
OUTPUT BIT 7		12	29		OUTPUT BIT 29
OUTPUT BIT 6		13	28		OUTPUT BIT 30
OUTPUT BIT 5		14	27		OUTPUT BIT 31
OUTPUT BIT 4		15	26		OUTPUT BIT 32
OUTPUT BIT 3		16	25		OUTPUT BIT 33
OUTPUT BIT 2		17	24		OUTPUT BIT 34
OUTPUT BIT 1		18	23		DATA ENABLE FOR M5450
					OUTPUT BIT 35 FOR M5451
BRIGHTNESS CONTROL		19	22		DATA IN
VDD		20	21		CLOCK IN

	BIT 14	BIT 15	BIT 16	BIT 17			BIT 18	BIT 19	BIT 20	BIT 21	BIT 22
	OUTPUT	OUTPUT	OUTPUT	OUTPUT	V	N.C	OUTPUT	OUTPUT	OUTPUT	OUTPUT	OUTPUT
					SS
	6	5	4	3	2	1	44	43	42	41	40
OUTPUT BIT 13												OUTPUT BIT 23
	7										39
OUTPUT BIT 12	8										38	OUTPUT BIT 24
OUTPUT BIT 11	9										37	OUTPUT BIT 25
OUTPUT BIT 10	10										36	OUTPUT BIT 26
OUTPUT BIT 9	11										35	OUTPUT BIT 27
N.C.	12										34	N.C.
OUTPUT BIT 8	13										33	OUTPUT BIT 28
OUTPUT BIT 7	14										32	OUTPUT BIT 29
OUTPUT BIT 6	15										31	OUTPUT BIT 30
OUTPUT BIT 5	16										30	OUTPUT BIT 31
OUTPUT BIT 4	17										29	OUTPUT BIT 32
	18	19	20	21	22	23	24	25	26	27	28
	OUTPUTBIT 3	OUTPUTBIT 2	OUTPUTBIT 1	BRIGHTNESSCONTROL	V	N.C	CLOCK IN	DATA IN	OUTPUTBIT 35	OUTPUTBIT 34	OUTPUTBIT 33
					DD

Figure 3. Block Diagram

		VDD
			OUTPUT	OUTPUT
	BRIGTHNESS		BIT 34	BIT 1
	CONTROL	20	24	18
	100kΩ
		19	35 OUTPUT BUFFERS
				LOAD
	DATA ENABLE (M5450)		35 LATCHES
		23
	OUTPUT35 (5451)
	SERIAL	22	35-BIT SHIFT REGISTER
	DATA
	CLOCK	21		RESET
				1

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M5450, M5451

Table 1. Absolute Maximum Ratings

	Symbol	Parameter	Value	Unit
	VDD	Supply Voltage	– 0.3 to 15	V
	VI	Input Voltage	– 0.3 to 15	V
	VO(off)	Off State Output Voltage	15	V
	IO	Output Sink Current	40	mA
	PTOT	Total Package Power Dissipation at 25°C	1	W
		Total Package Power Dissipation at 85°C	560	mW
	Tj	Junction Temperature	150	°C
	TOP	Operating Temperature Range	– 25 to 85	°C
	TSTG	Storage Temperature Range	– 65 to 150	°C

Note: Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

FUNCTIONAL DESCRIPTION

Both the M5450 and the M5451 are specially designed to operate 4 or 5-digit alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data source to the display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading "1" followed by the 35 data bits allows data transfer without an additional load signal. The 35 data bits are latched after the 36th bit is complete, thus providing non-multiplexed, direct drive to the display.

Outputs change only if the serial data bits differ from the previous time.

Display brightness is determined by control of the output current LED displays.

A 1nF capacitor should be connected to brightness control, pin 19, to prevent possible oscillations.

A block diagram is shown in Figure 3. For the M5450 a DATA ENABLE is used instead of the 35th output. The DATA ENABLE input is a metal option for the M5450.

The output current is typically 20 times greater than the current into pin 19, which is set by an external variable resistor. There is an internal limiting resistor of 400W nominal value.

Figure 4 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th clock a LOAD signal is generated synchronously with the high state of the clock, which loads the 35 bits of the shift registers into the latches.

At the low state of the clock a RESET signal is generated which clears all the shift registers for the next set of data. The shift registers are static

master-slave configurations. There is no clear for the master portion of the first shift register, thus allowing continuous operation.

There must be a complete set of 36 clocks or the shift registers will not clear.

When power is first applied to the chip an internal power ON reset signal is generated which resets all registers and all latches. The START bit and the first clock return the chip to its normal operation.

Bit 1 is the first bit following the start bit and it will appear on Pin 18. A logical "1" at the input will turn on the appropriate LED.

Figure 5 shows the timing relationship between Data, Clock and DATA ENABLE.

A max clock frequency of 0.5MHz is assumed. For applications where a lesser number of outputs are used, it is possible to either increase the current per output or operate the part at higher than 1V VOUT.

The following equation can be used for calculations.

Tj = [(VOUT) (ILED) (No. of segments) + (VDD × 7mA)] (124°C/W) + Tamb

where :

Tj = junction temperature (150°C max) VOUT = the voltage at the LED driver outputs ILED = the LED current

124°C/W = thermal coefficient of the package Tamb = ambient temperature

The above equation was used to plot Figure 6, Figure 7 and Figure 8.

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M5450, M5451

Table 2. Static Electrical Characteristics

(Tamb within operating range, VDD = 4.75V to 13.2V, VSS = 0V, unless otherwise specified)

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
VDD	Supply Voltage		4.75		13.2	V
IDD	Supply Current	VDD = 13.2V			7	mA
VI	Input Voltage Logical "0" Level	± 10µA Input Bias	- 0.3		0.8	V
	Logical "1" Level	4.75 ≤ VDD ≤ 5.25	2.2		VDD	V
		VDD > 5.25	VDD - 2		VDD	V
IB	Brightness Input Current (note 2)		0		0.75	mA
VB	Brightness Input Voltage (pin 19)	Input Current = 750µA, Tamb = 25°C	3		4.3	V
VO(off)	Off State Out. Voltage				13.2	V
IO	Out. Sink Current (note 3)
	Segment OFF	VO = 3V			10	µA
	Segment ON	VO = 1V (note 4)
		Brightness In. = 0µA	0		10	µA
		Brightness In. = 100µ	2	27	4	mA
		Brightness In. = 750µA	12	15	25	mA
fclock	Input Clock Frequency		0		0.5	MHz
IO	Output Matching (note 1)				± 20	%

Note: 1. Output matching is calculated as the percent variation from I MAX + IMIN/2.

2.With a fixed resistor on the brightness input some variation in brightness will occur from one device to another.

3.Absolute maximum for each output should be limited to 40mA.

4.The VO voltage should be regulated by the user. See Figure 7 and Figure 8 for allowable VO versus IO operation.

Figure 4. Input Data Format

1	36
CLOCK
START BIT 1	BIT 34 BIT 35
DATA

LOAD (INTERNAL)

RESET (INTERNAL)

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