STMicroelectronics M48Z58, M48Z58Y User Manual
FEAT URES SUMMARY
M48Z58
M48Z58Y
5V, 64 Kbit (8 Kbit x8) ZEROPOWER® SRAM
■ INTEGRATED, ULT RA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, AND
BATTERY
■ READ CYCLE TI ME EQUALS WR ITE CYCLE
TIME
■ AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECT ION
■ WRITE PROTECT VOLTAGES :
= Power-fail Deselect Voltage)
(V
PFD
– M48Z58: V
4.5V ≤ V
– M48Z58Y: V
4.2V ≤ V
■ SELF-CONTAINED BATTERY IN THE
= 4.75 to 5.5V
CC
≤ 4.75V
PFD
= 4.5 to 5.5V
CC
≤ 4.5V
PFD
CAPHAT™ DIP PACKAGE
■ PACKAGING INCLUDES A 28-LEAD SOIC
and SNAPHAT
®
TOP (to be ordered
separately)
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY
■ PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 8K x8 SRAMs
Figure 1. CAPHAT™ DIP Solution
28
1
PCDIP28 (PC)
Battery CAPHAT
Figure 2. SOIC Solution
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
Rev 6
1/20June 2005
M48Z58, M48Z58Y
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. CAPHAT™ DIP Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. SOIC Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. RE A D Mode AC Charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
V
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
Figure 10.Supply Voltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 10.Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Outline . . . . . . . . . . . . . . 14
Table 11. PMD IP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mec hanical Data. . . . . . . 14
Figure 14.SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline . . . . . . . . 15
Table 12. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 15
Figure 15.SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline. . . . . . . . . . . . . . . 16
Table 13. SH – 4-pin SNAPHA T Housing for 48mAh Battery, Packag e Mechanic al Data . . . . . . . 16
2/20
M48Z58, M48Z58Y
Figure 16.SH –4-pin SNAPHAT Housing for 120mAh Battery, Package Outline . . . . . . . . . . . . . . 17
Table 14. SH – 4-pin SNAPHA T Housing for 120mAh Battery, Packa ge Mechan ical Data . . . . . . 17
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 15.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 16.SNAPHAT Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 17.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20
M48Z58, M48Z58Y
DESCRIPTION
The M48Z58/Y ZEROPOWER® RAM is an 8K x 8
non-volatile static RAM that integrates power-fail
deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated
battery backed-up memory solution.
The M48Z58/Y is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
The 28-pin, 600mil DIP CAPHAT™ houses the
M48Z58/Y silicon with a long life lithium button cell
in a single package.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at bot h ends for direct connection to a separate SNAPHAT
taining the battery. The unique design allows the
SNAPHAT battery pac kage t o be mounted on top
of the SOIC package after the com pletion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery
damage due to the high temperatures required for
device surface-mounting. The SNAPHA T ho using
is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel
form.
For the 28-lead SOIC, the battery package (e. g.,
SNAPHAT) part number is “M4Z28-BR00SH” (see
Table 16., page 18).
Figure 3. Logic Diagram Table 1. Signal Names
A0-A12 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E
G
Chip Enable Input
Output Enable Input
A0-A12
13
V
CC
8
DQ0-DQ7
®
housing con-
W
M48Z58
M48Z58Y
E
G
V
SS
AI01176B
W
V
CC
V
SS
NC Not Connected Internally
WRITE Enable Input
Supply Voltage
Ground
4/20
M48Z58, M48Z58Y
Figure 4. DIP C on ne ctions Figure 5. SOI C Co nn e ct io ns
1
NC V
2
A12
A7
3
A6
4
A5
5
A4
6
A3
7
M48Z58
8
A2
A1
A0
DQ0
M48Z58Y
9
10
11
12
DQ2
13
14
SS
Figure 6. Block Diagram
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI01177B
CC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
NC V
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
1
2
3
4
5
6
7
M48Z58Y
8
9
10
11
12
DQ2
SS
13
14
AI01178B
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
CC
POWER
V
PFD
8K x 8
SRAM ARRAY
V
SS
A0-A12
DQ0-DQ7
E
W
G
AI01394
5/20
M48Z58, M48Z58Y
OPERAT IN G MODES
The M48Z58/Y also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condition. When V
is out of tolerance, the circuit write
CC
protects the SRAM, providing a high degree of
Table 2. Operating Modes
Mode
Deselect
WRITE
READ
READ
Deselect
Deselect
Note: X = VIH or VIL; VSO = Battery B ack-up Switchover Voltage.
Note: 1. See Table 10. , page 13 for details.
V
V
4.75 to 5.5V
4.5 to 5.5V
to V
SO
PFD
≤ V
or
SO
CC
(min)
(1)
(1)
E G W DQ0-DQ7 Power
V
IH
V
IL
V
IL
V
IL
X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode
READ Mode
The M48Z58/Y is in the READ Mode whenever W
(WRITE Enable) is high, E (Chip Enable) is low.
Thus, the unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes
of data is to be acces sed . Vali d data w ill be av ailable at the Data I/O pi ns within Address Access
time (t
stable, providing that the E
are also satisfied. If the E
) after the last address input signal is
AVQV
and G access times
and G access times are
not met, valid data will be available after the latter
data security in the midst of unpredictable system
operation brought on by low V
low battery switchover voltage (V
. As VCC falls be-
CC
), the control
SO
circuitry connects the battery which maintains data
until valid power returns.
X X High Z Standby
X
V
IL
V
IH
V
IL
V
IH
V
IH
of the Chip Enable Access time (t
Enable Access time (t
D
IN
D
OUT
High Z Active
).
GLQV
Active
Active
ELQV
) or Output
The state of the eight t hree-state Da ta I/O si gnals
is controlled by E
ed before t
indeterminate state until t
puts are changed while E
and G. If the outputs are activat-
, the data lines will be driven to an
AVQV
. If the Ad dres s In-
AVQV
and G remain active,
output dat a will re main valid for Ou tput D ata H old
time (t
) but will go indeterminate until the next
AXQX
Addr e ss Access.
Figure 7. READ Mode AC Waveforms
A0-A12
tAVQV tAXQX
E
tELQX
G
DQ0-DQ7
Note: W RITE Enable (W) = High.
6/20
tELQV
tGLQV
tGLQX
tAVAV
VALID
tEHQZ
tGHQZ
VALID
AI01385
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