STMicroelectronics M48Z58, M48Z58Y User Manual
M48Z58
M48Z58Y
5V, 64 Kbit (8 Kbit x8) ZEROPOWER® SRAM
FEATURES SUMMARY
■INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY
■READ CYCLE TIME EQUALS WRITE CYCLE TIME
■AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION
■WRITE PROTECT VOLTAGES: (VPFD = Power-fail Deselect Voltage)
–M48Z58: VCC = 4.75 to 5.5V 4.5V ≤ VPFD ≤ 4.75V
–M48Z58Y: VCC = 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V
■SELF-CONTAINED BATTERY IN THE CAPHAT™ DIP PACKAGE
■PACKAGING INCLUDES A 28-LEAD SOIC and SNAPHAT® TOP (to be ordered separately)
■SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY
■PIN AND FUNCTION COMPATIBLE WITH JEDEC STANDARD 8K x8 SRAMs
Figure 1. CAPHAT™ DIP Solution
28
1
PCDIP28 (PC)
Battery CAPHAT
Figure 2. SOIC Solution
SNAPHAT (SH)
Battery
28 
1
SOH28 (MH)
Rev 6
June 2005 |
1/20 |
M48Z58, M48Z58Y
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. CAPHAT™ DIP Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. SOIC Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 12.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Outline . . . . . . . . . . . . . . 14 Table 11. PMDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mechanical Data. . . . . . . 14 Figure 14.SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline . . . . . . . . 15 Table 12. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 15 Figure 15.SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline . . . . . . . . . . . . . . . 16 Table 13. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data . . . . . . . 16
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M48Z58, M48Z58Y
Figure 16.SH –4-pin SNAPHAT Housing for 120mAh Battery, Package Outline . . . . . . . . . . . . . . 17 Table 14. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data . . . . . . 17
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 16. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 17. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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M48Z58, M48Z58Y
DESCRIPTION
The M48Z58/Y ZEROPOWER® RAM is an 8K x 8 non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution.
The M48Z58/Y is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
The 28-pin, 600mil DIP CAPHAT™ houses the M48Z58/Y silicon with a long life lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT® housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form.
For the 28-lead SOIC, the battery package (e.g., SNAPHAT) part number is “M4Z28-BR00SH” (see Table 16., page 18).
Figure 3. Logic Diagram |
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Table 1. Signal Names |
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VCC |
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A0-A12 |
Address Inputs |
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DQ0-DQ7 |
Data Inputs / Outputs |
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13 |
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8 |
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Chip Enable Input |
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E |
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A0-A12 |
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DQ0-DQ7 |
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Output Enable Input |
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G |
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WRITE Enable Input |
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W |
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W |
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M48Z58 |
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M48Z58Y |
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VCC |
Supply Voltage |
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E |
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VSS |
Ground |
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G |
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NC |
Not Connected Internally |
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VSS |
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AI01176B |
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4/20
M48Z58, M48Z58Y
Figure 4. DIP Connections |
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Figure 5. SOIC Connections |
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NC |
1 |
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28 |
VCC |
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NC |
1 |
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28 |
VCC |
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A12 |
2 |
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27 |
W |
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A12 |
2 |
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27 |
W |
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A7 |
3 |
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26 |
NC |
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A7 |
3 |
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26 |
NC |
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A6 |
4 |
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25 |
A8 |
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A6 |
4 |
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25 |
A8 |
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A5 |
5 |
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24 |
A9 |
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A5 |
5 |
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24 |
A9 |
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A4 |
6 |
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23 |
A11 |
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A4 |
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23 |
A11 |
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A3 |
7 |
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22 |
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A3 |
7 |
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22 |
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M48Z58 |
G |
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M48Z58Y |
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G |
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A2 |
8 |
M48Z58Y |
21 |
A10 |
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A2 |
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21 |
A10 |
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A1 |
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20 |
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A1 |
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E |
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E |
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A0 |
10 |
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19 |
DQ7 |
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A0 |
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19 |
DQ7 |
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DQ0 |
11 |
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DQ6 |
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DQ0 |
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DQ6 |
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DQ1 |
12 |
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DQ5 |
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DQ1 |
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DQ5 |
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DQ2 |
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DQ4 |
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DQ2 |
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DQ4 |
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VSS |
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DQ3 |
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VSS |
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15 |
DQ3 |
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AI01177B |
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AI01178B |
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Figure 6. Block Diagram
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A0-A12 |
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LITHIUM |
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DQ0-DQ7 |
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CELL |
POWER |
8K x 8 |
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VOLTAGE SENSE |
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SRAM ARRAY |
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AND |
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E |
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SWITCHING |
VPFD |
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CIRCUITRY |
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W |
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G |
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VCC |
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VSS |
AI01394 |
5/20
M48Z58, M48Z58Y
OPERATING MODES
The M48Z58/Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of
Table 2. Operating Modes
data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below battery switchover voltage (VSO), the control circuitry connects the battery which maintains data until valid power returns.
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VCC |
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Mode |
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E |
G |
W |
DQ0-DQ7 |
Power |
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Deselect |
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VIH |
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X |
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X |
High Z |
Standby |
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4.75 to 5.5V |
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WRITE |
VIL |
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X |
VIL |
DIN |
Active |
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READ |
VIL |
VIL |
VIH |
DOUT |
Active |
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4.5 to 5.5V |
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READ |
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VIL |
VIH |
VIH |
High Z |
Active |
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Deselect |
VSO to VPFD (min)(1) |
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X |
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High Z |
CMOS Standby |
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Deselect |
≤ VSO(1) |
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High Z |
Battery Back-up Mode |
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Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Note: 1. See Table 10., page 13 for details.
READ Mode
The M48Z58/Y is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable) is low. Thus, the unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is
stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter
of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active, output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next Address Access.
Figure 7. READ Mode AC Waveforms
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tAVAV |
A0-A12 |
VALID |
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tAVQV |
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tELQV |
E |
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tELQX |
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tGLQV |
G |
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tGLQX |
DQ0-DQ7 |
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tAXQX tEHQZ
tGHQZ
VALID
AI01385
Note: WRITE Enable (W) = High.
6/20
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