256 Kbit (32 Kbit x8) ZEROPOWER® SRAM
FEAT URES SUMMARY
■ INTEGRATED, ULT RA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, AND
BATTERY
■ READ CYCLE TI ME EQUALS WR ITE CYCLE
TIME
■ AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECT ION
■ WRITE PROTECT VOLTAGES :
= Power-fail Deselect Voltage)
(V
PFD
– M48Z35: V
4.5V ≤ V
– M48Z35Y: 4.5 to 5.5V
4.2V ≤ V
■ SELF-CONTAINED BATTERY IN THE
CAPHAT™ DIP PACKAGE
■ PACKAGING INCLUDES A 28-LEAD SOIC
AND SNAPHAT
separately)
■ PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 32K x 8 SRAMs
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY
= 4.75 to 5.5V
CC
≤ 4.75V
PFD
≤ 4.5V
PFD
®
TOP (to be ordered
M48Z35
M48Z35Y
Figure 1. 28-pin CAPHAT™ DIP Package
28
1
PCDIP28 (PC)
Battery CAPHAT
Figure 2. 28-pi n S O I C Package
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
Rev 6
1/20June 2005
M48Z35, M48Z35Y
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 28-pin CAPHAT™ DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. RE A D Mode AC Charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. WRITE Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
V
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
Figure 11.Supply Voltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 9. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 10.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Outline . . . . . . . . . . . . . . 14
Table 11. PMD IP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mec hanical Data. . . . . . . 14
Figure 14.SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline . . . . . . . . 15
Table 12. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 15
Figure 15.SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline. . . . . . . . . . . . . . . 16
Table 13. SH – 4-pin SNAPHA T Housing for 48mAh Battery, Packag e Mechanic al Data . . . . . . . 16
2/20
M48Z35, M48Z35Y
Figure 16.SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline. . . . . . . . . . . . . . 17
Table 14. SH – 4-pin SNAPHA T Housing for 120mAh Battery, Packa ge Mechan ical Data . . . . . . 17
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 15.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 16.SNAPHAT Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 17.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20
M48Z35, M48Z35Y
DESCRIPTION
The M48Z35/Y ZEROPOWE R® RAM is a 32 Kbit
x 8, non-volatile static RAM that integrates powerfail deselect circuitry and battery control logic on a
single die. The monolithic chip is a vailable in two
special packages to provide a highly integrated
battery backed-up memory solution.
The M48Z35/Y is a non-volatile pin and function
equivalent to any JEDEC standard 32K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed. The 28-pin 600mil
DIP CAPHAT™ houses the M48Z35/Y silicon with
a long life lithium button cell in a single package.
Figure 3. Logic Diagram Table 1. Signal Names
V
CC
15
A0-A14
8
DQ0-DQ7
The 28-pin 330mil SOIC provides sockets with
gold plated contacts at bot h ends for direct connection to a separate SNAPHAT housing containing the battery. The unique design allows the
SNAPHAT battery pac kage t o be mounted on top
of the SOIC package after the com pletion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery
damage due to the high temperatures required for
device surface-mounting. The SNAPHA T ho using
is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel
form.
For the 28-lead SOIC, the battery package (i.e.
SNAPHAT) part number is “M4Z28-BR00SH1.”
A0-A14 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E
G
Chip Enable Input
Output Enable Input
W
M48Z35
E
G
M48Z35Y
V
SS
AI01616D
W
V
CC
V
SS
WRITE Enable Input
Supply Voltage
Ground
4/20
M48Z35, M48Z35Y
Figure 4. DIP C on ne ctions Figure 5. SOI C Co nn e ct io ns
1
A14 V
2
A12
3
A7
4
A6
5
A5
A4
6
A3
7
M48Z35
8
A2
A1
A0
DQ0
M48Z35Y
9
10
11
12
DQ2
13
14
SS
Figure 6. Block Diagram
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI01617D
CC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
A14 V
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
1
2
3
4
5
6
7
M48Z35Y
8
9
10
11
12
DQ2
SS
13
14
AI02303C
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
CC
POWER
V
PFD
32K x 8
SRAM ARRAY
V
SS
A0-A14
DQ0-DQ7
E
W
G
AI01619B
5/20
M48Z35, M48Z35Y
OPERAT IN G MODES
The M48Z35/Y also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condition. When V
protects the SRAM, providing a high degree of
Table 2. Operating Modes
Mode
Deselect
WRITE
READ
READ
Deselect
Deselect
Note: X = VIH or VIL; VSO = Battery B ack-up Switchover Voltage.
Note: 1. See Table 6. , page 10 for detai l s.
READ Mode
The M48Z35/Y is in the READ Mode whenever W
(WRITE Enable) is high, E (Chip Enable) is low.
The device architecture allows ripple-through access of data from eight of 264,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
access times are not met, valid data will be
G
is out of tolerance, the circuit write
CC
V
CC
4.75 to 5.5V
or
4.5 to 5.5V
to V
V
SO
PFD
≤ V
SO
(min)
(1)
AVQV
(1)
) after the last
E G W DQ0-DQ7 Power
V
IH
V
IL
V
IL
V
IL
X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode
data security in the midst of unpredictable system
operation brought on by low V
. As VCC falls be-
CC
low approximately 3V, the control circuitry connects the battery which maintains data until valid
power returns.
X X High Z Standby
X
V
IL
V
IH
V
IL
V
IH
V
IH
D
IN
D
OUT
High Z Active
Active
Active
available after the latter of the Chip Enable Access
time (t
(t
GLQV
) or Output Enable Access time
ELQV
).
The state of the eight t hree-state Da ta I/O si gnals
is controlled by E
ed before t
indeterminate state until t
puts are changed while E
and G. If the outputs are activat-
, the data lines will be driven to an
AVQV
. If the Ad dres s In-
AVQV
and G remain active,
output dat a will re main valid for Ou tput D ata H old
time (t
) but will go indeterminate until the next
AXQX
Addr e ss Access.
Figure 7. READ Mode AC Waveforms
A0-A14
tAVQV tAXQX
E
tELQX
G
DQ0-DQ7
Note: W RITE Enable (W) = High.
6/20
tELQV
tGLQV
tGLQX
tAVAV
VALID
tEHQZ
tGHQZ
VALID
AI00925
M48Z35, M48Z35Y
Table 3. READ Mode AC Characteristics
M48Z35/Y
or E. A
WHAX
(1)
from
Min Max
READ or WRITE cycle. Data-in must be valid t
prior to the end of WRITE and remain valid for
VWH
afterward. G should be kept high during
t
WHDX
WRITE cycles to avoid bus contention; although, if
the output bus has b een activated by a low on E
and G, a low on W will disa ble the output s t
after W falls.
Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. Valid for Ambient Op erating Temp erature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2. C
3. C
READ Cycle Time 70 ns
(2)
Address Valid to Output Valid 70 ns
(2)
Chip Enable Low to Output Valid 70 ns
(2)
Output Enable Low to Output Valid 35 ns
(3)
Chip Enable Low to Output Transition 5 ns
(3)
Output Enable Low to Output Transition 5 ns
(3)
Chip Enable High to Output Hi-Z 25 ns
(3)
Output Enable High to Output Hi-Z 25 ns
(2)
Address Transition to Output Transition 10 ns
= 100pF.
L
= 5pF.
L
Parameter
WRITE Mode
The M48Z35/Y is in the WRITE Mode whenever W
and E are low. The start of a WRITE is referenced
from the latter occurri ng fallin g edge of W
WRITE is terminated by the earlier rising edge of
or E. The addresses must be held valid through-
W
out the cycle. E
mum of t
or W must return high for a mini-
from Chip Enable or t
EHAX
WRITE Enable prior to the initiation of another
Unit–70
D-
WLQZ
Figure 8. WRITE Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A14
tAVEL
E
tAVWL
W
tWLQZ
DQ0-DQ7
VALID
tAVWH
tWLWH
tDVWH
tWHAX
tWHQX
tWHDX
DATA INPUT
AI00926
7/20
M48Z35, M48Z35Y
Figure 9. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A14
tAVEL
E
tAVWL
W
DQ0-DQ7
VALID
tAVEH
tELEH
DATA INPUT
tDVEH
tEHAX
tEHDX
AI00927
Table 4. WRITE Mode AC Characteristics
M48Z35/Y
Symbol
t
AVAV
t
AVWL
t
AVEL
t
WLWH
t
ELEH
t
WHAX
t
EHAX
t
DVWH
t
DVEH
t
WHDX
t
EHDX
(2,3)
t
WLQZ
t
AVWH
t
AVEH
(2,3)
t
WHQX
Note: 1. Valid for Ambient Op erating Temp erature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
= 5pF (see Figure 12., page 12).
2. C
L
3. If E
WRITE Cycle Time 70 ns
Address Valid to WRITE Enable Low 0 ns
Address Valid to Chip Enable Low 0 ns
WRITE Enable Pulse Width 50 ns
Chip Enable Low to Chip Enable High 55 ns
WRITE Enable High to Address Transition 0 ns
Chip Enable High to Address Transition 0 ns
Input Valid to WRITE Enable High 30 ns
Input Valid to Chip Enable High 30 ns
WRITE Enable High to Input Transition 5 ns
Chip Enable High to Input Transition 5 ns
WRITE Enable Low to Output Hi-Z 25 ns
Address Valid to WRITE Enable High 60 ns
Address Valid to Chip Enable High 60 ns
WRITE Enable High to Output Transition 5 ns
goes low simultaneously with W going low, the outp uts remain in the high impeda nce state.
Parameter
(1)
Min Max
Unit–70
8/20
Data Retention Mode
With valid V
applied, the M48Z35/Y operates as
CC
a conventional BYTEWIDE™ static RAM. Should
the supply volt age decay, the RA M will a utomatically power-fail deselect, write protecting itself
when V
falls within the V
CC
PFD
(max), V
PFD
(min)
window. All outputs become high impedance, and
all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently a ddressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
(min), the user can be
PFD
assured the memory will be i n a write protected
state, provided the V
fall time is not less than tF.
CC
The M48Z35/Y may respond to transient noise
spikes on V
during the time the device is sampling V
that reach into the deselect window
CC
. There-
CC
Figure 10. Power Down/Up Mode AC Waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSO
M48Z35, M48Z35Y
fore, decoupling of the power supply lines is recommended.
When V
switches power to the internal battery which preserves data. The internal button cell will maintain
data in the M48Z35/Y for an accumulated period of
at least 10 years (at 25°C) when V
.
V
SO
As system power returns and V
, the battery is disconnected, and the power
V
SO
supply is switched to external V
tion continues until V
t
REC
t
REC
For more information on Battery Storage Life refer
to the Application Note AN1012.
drops below VSO, the control circuit
CC
is less t han
CC
rises above
CC
. Write protec-
reaches V
CC
CC
(min) plus
PFD
(min). Normal RAM operation can resume
after VCC exceeds V
PFD
(max).
INPUTS
OUTPUTS
tF
tPD
VALID VALID
(PER CONTROL INPUT)
tFB
tDR
tRB
DON'T CARE
HIGH-Z
tR
trec
RECOGNIZEDRECOGNIZED
(PER CONTROL INPUT)
AI01168C
Table 5. Power Down/Up AC Characteristics
Symbol
t
PD
(2)
t
F
(3)
t
FB
t
R
t
RB
t
rec
Note: 1. Valid for Ambient Op erating Temp erature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2. V
3. V
E or W at VIH before Power Down
V
(max) to V
PFD
V
(min) to VSS VCC Fall Time
PFD
V
(min) to V
PFD
VSS to V
V
(max) to V
PFD
es V
(min).
PFD
(min) to VSS fall time of less than tFB may cause corruption of RAM data.
PFD
PFD
(max) to Inputs Recognized
PFD
PFD
Parameter
(min) VCC Fall Time
PFD
(max) VCC Rise Time
PFD
(min) V
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
CC
(1)
Rise Time
Min Max Unit
0µs
300 µs
10 µs
10 µs
1µs
40 200 ms
9/20
M48Z35, M48Z35Y
Table 6. Power Down/Up Trip Points DC Characteristics
Symbol
V
PFD
V
SO
t
DR
Note: All voltages referenced to VSS.
Note: 1. Valid for Ambient Op erating Temp erature: T
2. At 25°C, V
Power-fail Deselect Voltage
Battery Back-up Switchover Voltage M48Z35/Y 3.0 V
(2)
Expected Data Retention Time 10 YEARS
= 0V.
CC
Parameter
(1)
M48Z35 4.5 4.6 4.75 V
M48Z35Y 4.2 4.35 4.5 V
= 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
Min Typ Max Unit
VCC Noise And Negative Going Transients
transients, including those produced by output
I
CC
switching, can produce voltage fluctuations, resulting in spikes on the V
bus. These transients
CC
can be reduced if capacitors are used to store energy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (see Figure 11) is
recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on V
below V
by as much as one volt. These negative
SS
that drive it to values
CC
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, ST recommends connecting
a schottky diode from V
nected to V
, anode to VSS). (Schottky diode
CC
CC
to V
(cathode con-
SS
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount).
Figure 11. Supply Voltage Protection
V
CC
V
CC
0.1µF DEVICE
V
SS
AI02169
10/20
M48Z35, M48Z35Y
MAXIMUM RA T ING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
Table 7. Absolute Maximum Ratings
Symbol Parameter Value Unit
not implied. Exposure to Absol ute Max imum Ra ting conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.
T
T
A
STG
Ambient Operating Temperature 0 to 70 °C
Storage Temperature (VCC Off, Oscillator Off)
SNAPHAT
®
–40 to 85 °C
SOIC –55 to 125 °C
(1,2,3)
T
SLD
V
IO
V
CC
I
O
P
D
Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer
2. For S O package, standard (SnPb) lead finish: Reflow at peak t em perature of 2 25°C (total thermal budget not to excee d 180°C for
3. For S O package , Lead-free (Pb-free) lead finish: Reflow at peak tempera ture of 260°C (total therm al budget n ot to exceed 245°C
Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages –0.3 to 7.0 V
Supply Voltage –0.3 to 7.0 V
Output Current 20 mA
Power Dissipation 1 W
than 30 seconds).
between 90 to 15 0 s e c o nds).
for greater than 30 seconds).
CAUTION: Negative undershoots bel ow –0.3V are not allowed on any pin whi l e i n t he Battery B ack-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
11/20
M48Z35, M48Z35Y
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Meas ure-
Table 8. Operating and AC Measurement Conditions
Parameter M48Z35 M48Z35Y Unit
ment Conditions listed in t he relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Supply Voltage (V
Ambient Operating Temperature (T
Load Capacitance (C
CC
)
)
A
)
L
4.75 to 5.5V 4.5 to 5.5 V
0 to 70 0 to 70 °C
100 100 pF
Input Rise and Fall Times ≤ 5 ≤ 5ns
Input Pulse Voltages 0 to 3 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 1.5 V
Note: O utput Hi-Z is def i ned as the poin t where data is no l onger driven.
Figure 12. AC Measurement Lo a d Circuit
DEVICE
UNDER
TEST
645Ω
CL = 100pF or
5pF
1.75V
CL includes JIG capacitance
AI03211
Table 9. Capacitance
Symbol
C
IN
C
IO
Note: 1. Effec tive capacitance measure d wi t h power supp l y at 5V. Sampled on l y, not 100% tested.
2. Outputs deselect ed.
3. At 25°C.
Input Capacitance 10 pF
(3)
Input / Output Capacitance 10 pF
Parameter
12/20
(1,2)
Min Max Unit
Table 10. DC Characteristics
Symbol Parameter
(2)
Input Leakage Current
(2)
Output Leakage Current
Supply Current Outputs open 50 mA
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
I
I
LI
LO
I
I
CC1
I
CC2
CC
Test Condition
0V ≤ V
0V ≤ V
E
≤ V
IN
≤ V
OUT
E
= V
IH
= VCC – 0.2V
CC
CC
(1)
M48Z35, M48Z35Y
Min Max Unit
±1 µA
±5 µA
3mA
3mA
V
V
V
V
Note: 1. Valid for Ambient Op erating Temp erature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
Input Low Voltage –0.3 0.8 V
IL
Input High Voltage 2.2
IH
I
Output Low Voltage
OL
Output High Voltage
OH
2. Outputs deselect ed.
= 2.1mA
OL
I
= –1mA
OH
2.4 V
V
CC
+ 0.3
0.4 V
V
13/20
M48Z35, M48Z35Y
PACKAGE ME CHANICAL INFORMATION
Figure 13. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Outline
A2
B1 B
A1AL
e1
C
eA
e3
D
N
E
1
Note: D rawing is not to scale.
PCDIP
Table 11. PMDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350
mm inches
B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.31 0.008 0.012
D 39.37 39.88 1.550 1.570
E 17.83 18.34 0.702 0.722
e1 2.29 2.79 0.090 0.110
e3 29.72 36.32 1.170 1.430
eA 15.24 16.00 0.600 0.630
L 3.05 3.81 0.120 0.150
N 28 28
14/20
M48Z35, M48Z35Y
Figure 14. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2
A
C
Be
eB
CP
D
N
E
H
LA1 α
1
SOH-A
Note: D rawing is not to scale.
Table 12. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
mm inch
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e1.27– –0.050– –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N 28 28
CP 0.10 0.004
15/20
M48Z35, M48Z35Y
Figure 15. SH – 4-pin SNAPHAT Ho u sing for 48mAh Battery, Package Outline
A1
A
eA
D
B
eB
E
SHZP-A
Note: D rawing is not to scale.
Table 13. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 9.78 0.385
mm inches
A2
A3
L
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
16/20
Figure 16. SH – 4-pi n SNAP HAT Housing f or 120mAh Battery, Package Outline
M48Z35, M48Z35Y
A1
eA
D
A
B
eB
A3
L
E
SHZP-A
Note: D rawing is not to scale.
Table 14. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Packag e Mec hanica l Data
Symb
Typ Min Max Typ Min Max
A 10.54 0.415
mm inches
A2
A1 8.00 8.51 0.315 0.335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 0.710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
17/20
M48Z35, M48Z35Y
PART NUMBERING
Table 15. Ordering Information Scheme
Example: M48Z 35Y –70 MH 1 E
Device Type
M48Z
Supply Voltage and Write Protect Voltage
(1)
35
= VCC = 4.75 to 5.5V; V
35Y = V
= 4.5 to 5.5V; V
CC
Speed
–70 = 70ns
Package
PC = PCDIP28
(2)
= SOH28
MH
= 4.5 to 4.75V
PFD
= 4.2 to 4.5V
PFD
Temperature Range
1 = 0 to 70°C
Shipping Method
For SOH28:
blank = Tubes (Not for New Design - Use E)
E = Lead-free Package, Tubes
F = Lead-free Package, Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
For PCDIP28:
blank = Tubes
Note: 1. The M48Z35 part is of f ered with the PCDIP28 (CAP HA T ) package on l y.
2. The SOIC package (SOH28) requires the SNAPHAT
BR00SH” in plastic tube or “M4Zxx-BR00SHTR” in Tape & Reel form (see Table 16).
Note: Caution: Do not place the SNAPHAT battery package “M4Zxx-BR00SH” i n conductiv e foam as it will drai n the lithi um button-cel l batt ery.
®
battery package which is ordered separately under the part number “M4Zxx-
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
Table 16. SNAPHAT Battery Table
Part Number Description Package
M4Z28-BR00SH Lithium Battery (48mAh) SNAPHAT SH
M4Z32-BR00SH Lithium Battery (120mAh) SNAPHAT SH
18/20
REVISION HISTORY
Table 17. Revision History
Date Rev. # Revision Details
August 1999 1.0 First Issue
21-Apr-00 1.1 SH and SH28 packages for 2-pin and 2-socket removed
10-May-01 2.0 Reformatted; added temperature information (Table 9, 10, 3, 4, 5, 6)
29-May-02 2.1 Modified reflow time and temperature footnotes (Table 7)
02-Apr-03 3.0 v2.2 template applied; test condition updated (Table 6)
03-Mar-04 4.0 Reformatted; updated with Lead-free information (Table 7, 15)
20-Aug-04 5.0 Reformatted; remove references to ‘crystal’ (Figur e 2)
M48Z35, M48Z35Y
09-Jun-05 6
Removal of SNAPHAT, Industrial temperature sales types (Table 3, 4, 5, 6, 7, 8, 10,
15)
19/20
M48Z35, M48Z35Y
Information furnished is believed to be accurate and reliable. However, STMicroelectronics a ssumes no responsibility fo r the c onsequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authori zed for use as criti cal component s in life support devices or sys tems without express written approval of STMicroele ct ronics.
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20/20
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