STMicroelectronics M48Z35, M48Z35Y Technical data

256 Kbit (32 Kbit x8) ZEROPOWER® SRAM

FEAT URES SUMMARY

■ INTEGRATED, ULT RA LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT, AND
BATTERY

■ READ CYCLE TI ME EQUALS WR ITE CYCLE

TIME

■ AUTOMATIC POWER-FAIL CHIP

DESELECT AND WRITE PROTECT ION

■ WRITE PROTECT VOLTAGES :

= Power-fail Deselect Voltage)

(V

PFD

– M48Z35: V

4.5V ≤ V

– M48Z35Y: 4.5 to 5.5V

4.2V ≤ V

■ SELF-CONTAINED BATTERY IN THE

CAPHAT™ DIP PACKAGE

■ PACKAGING INCLUDES A 28-LEAD SOIC

AND SNAPHAT
separately)

■ PIN AND FUNCTION COMPATIBLE WITH

JEDEC STANDARD 32K x 8 SRAMs

■ SOIC PACKAGE PROVIDES DIRECT

CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY

= 4.75 to 5.5V

CC

≤ 4.75V

PFD

≤ 4.5V

PFD

®

TOP (to be ordered

M48Z35

M48Z35Y

Figure 1. 28-pin CAPHAT™ DIP Package

28

1

PCDIP28 (PC)

Battery CAPHAT

Figure 2. 28-pi n S O I C Package

SNAPHAT (SH)

Battery

28

1

SOH28 (MH)

Rev 6

1/20June 2005

M48Z35, M48Z35Y

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 28-pin CAPHAT™ DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. RE A D Mode AC Charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 8. WRITE Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 9. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 10.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

V

Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CC

Figure 11.Supply Voltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 8. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 12.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 9. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 10.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 13.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Outline . . . . . . . . . . . . . . 14

Table 11. PMD IP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mec hanical Data. . . . . . . 14

Figure 14.SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline . . . . . . . . 15

Table 12. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 15

Figure 15.SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline. . . . . . . . . . . . . . . 16

Table 13. SH – 4-pin SNAPHA T Housing for 48mAh Battery, Packag e Mechanic al Data . . . . . . . 16

2/20

M48Z35, M48Z35Y

Figure 16.SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline. . . . . . . . . . . . . . 17

Table 14. SH – 4-pin SNAPHA T Housing for 120mAh Battery, Packa ge Mechan ical Data . . . . . . 17

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 15.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 16.SNAPHAT Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 17.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3/20

M48Z35, M48Z35Y

DESCRIPTION

The M48Z35/Y ZEROPOWE R® RAM is a 32 Kbit
x 8, non-volatile static RAM that integrates power­fail deselect circuitry and battery control logic on a
single die. The monolithic chip is a vailable in two
special packages to provide a highly integrated
battery backed-up memory solution.

The M48Z35/Y is a non-volatile pin and function
equivalent to any JEDEC standard 32K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed. The 28-pin 600mil
DIP CAPHAT™ houses the M48Z35/Y silicon with
a long life lithium button cell in a single package.

Figure 3. Logic Diagram Table 1. Signal Names

V

CC

15

A0-A14

8

DQ0-DQ7

The 28-pin 330mil SOIC provides sockets with
gold plated contacts at bot h ends for direct con­nection to a separate SNAPHAT housing contain­ing the battery. The unique design allows the
SNAPHAT battery pac kage t o be mounted on top
of the SOIC package after the com pletion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery
damage due to the high temperatures required for
device surface-mounting. The SNAPHA T ho using
is keyed to prevent reverse insertion.

The SOIC and battery packages are shipped sep­arately in plastic anti-static tubes or in Tape & Reel
form.

For the 28-lead SOIC, the battery package (i.e.
SNAPHAT) part number is “M4Z28-BR00SH1.”

A0-A14 Address Inputs

DQ0-DQ7 Data Inputs / Outputs

E
G

Chip Enable Input
Output Enable Input

W

M48Z35

E

G

M48Z35Y

V

SS

AI01616D

W

V

CC

V

SS

WRITE Enable Input
Supply Voltage
Ground

4/20

M48Z35, M48Z35Y

Figure 4. DIP C on ne ctions Figure 5. SOI C Co nn e ct io ns

1

A14 V

2

A12

3

A7

4

A6

5

A5
A4

6

A3

7

M48Z35

8

A2
A1
A0

DQ0

M48Z35Y
9
10
11
12

DQ2

13
14

SS

Figure 6. Block Diagram

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI01617D

CC

W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

A14 V
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

1
2
3
4
5
6
7

M48Z35Y

8
9
10
11
12

DQ2

SS

13
14

AI02303C

28
27
26
25
24
23
22
21
20
19
18
17
16
15

CC

W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

V

CC

POWER

V

PFD

32K x 8

SRAM ARRAY

V

SS

A0-A14

DQ0-DQ7

E

W

G

AI01619B

5/20

M48Z35, M48Z35Y

OPERAT IN G MODES

The M48Z35/Y also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi­tion. When V
protects the SRAM, providing a high degree of

Table 2. Operating Modes

Mode

Deselect
WRITE
READ
READ

Deselect
Deselect

Note: X = VIH or VIL; VSO = Battery B ack-up Switchover Voltage.
Note: 1. See Table 6. , page 10 for detai l s.

READ Mode

The M48Z35/Y is in the READ Mode whenever W
(WRITE Enable) is high, E (Chip Enable) is low.
The device architecture allows ripple-through ac­cess of data from eight of 264,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and

access times are not met, valid data will be

G

is out of tolerance, the circuit write

CC

V

CC

4.75 to 5.5V
or

4.5 to 5.5V

to V

V

SO

PFD

≤ V

SO

(min)

(1)

AVQV

(1)

) after the last

E G W DQ0-DQ7 Power

V

IH

V

IL

V

IL

V

IL

X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode

data security in the midst of unpredictable system
operation brought on by low V

. As VCC falls be-

CC

low approximately 3V, the control circuitry con­nects the battery which maintains data until valid
power returns.

X X High Z Standby
X

V

IL

V

IH

V

IL

V

IH

V

IH

D

IN

D

OUT

High Z Active

Active
Active

available after the latter of the Chip Enable Access
time (t
(t

GLQV

) or Output Enable Access time

ELQV

).

The state of the eight t hree-state Da ta I/O si gnals
is controlled by E
ed before t
indeterminate state until t
puts are changed while E

and G. If the outputs are activat-

, the data lines will be driven to an

AVQV

. If the Ad dres s In-

AVQV

and G remain active,
output dat a will re main valid for Ou tput D ata H old
time (t

) but will go indeterminate until the next

AXQX

Addr e ss Access.

Figure 7. READ Mode AC Waveforms

A0-A14

tAVQV tAXQX

E

tELQX

G

DQ0-DQ7

Note: W RITE Enable (W) = High.

6/20

tELQV

tGLQV

tGLQX

tAVAV

VALID

tEHQZ

tGHQZ

VALID

AI00925