STMicroelectronics M48Z129Y, M48Z129V User Manual

M48Z129Y*

M48Z129V

5.0V OR 3.3V, 1 Mbit (128 Kb x 8) ZEROPOWER® SRAM

FEATURES SUMMARY

■INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY

■CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES

■10 YEARS OF DATA RETENTION IN THE ABSENCE OF POWER

■MICROPROCESSOR POWER-ON RESET (RESET VALID EVEN DURING BATTERY BACK-UP MODE)

■BATTERY LOW PIN - PROVIDES WARNING OF BATTERY END-OF-LIFE

■AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION

■WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage):

–M48Z129Y: VCC = 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V

–M48Z129V: VCC = 3.0 to 3.6V 2.7V ≤ VPFD ≤ 3.0V

■SELF-CONTAINED BATTERY IN THE CAPHAT™ DIP PACKAGE

■PIN AND FUNCTION COMPATIBLE WITH JEDEC STANDARD 128K x 8 SRAMs

Figure 1. 32-pin PMDIP Module

32

1

PMDIP32 (PM)

Module

* Contact local ST sales office for availability.

March 2005

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M48Z129Y*, M48Z129V

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 32-pin PMDIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. Address Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . 6 Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 9. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12.PMDIP32 – 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 11. PMDIP32 – 32-pin Plastic DIP, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . 13

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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M48Z129Y*, M48Z129V

SUMMARY DESCRIPTION

The M48Z129Y/V ZEROPOWER® SRAM is a 1,048,576 bit non-volatile static RAM organized as 131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic 32-pin DIP Module. The

M48Z129Y/V directly replaces industry standard 128K x 8 SRAM. It also provides the non-volatility of FLASH without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.

Figure 2. Logic Diagram

Table 1. Signal Names

VCC

A0-A16

Address Inputs

DQ0-DQ7

Data Inputs / Outputs

17

8

E

Chip Enable

A0-A16

DQ0-DQ7

Output Enable

G

M48Z129Y

W

RST

WRITE Enable

W

M48Z129V

E

BL

Reset Output (Open Drain)

RST

Battery Low Output (Open Drain)

G

BL

VCC

Supply Voltage

VSS

Ground

VSS

AI02309

Figure 3. DIP Connections

1

32

VCC

RST

A16

2

31

A15

A14

3

30

BL

A12

4

29

W

A7

5

28

A13

A6

6

27

A8

A5

7

26

A9

A4

8

M48Z129Y 25

A11

A3

9

M48Z129V 24

G

A2

10

23

A10

A1

11

22

E

A0

12

21

DQ7

DQ0

13

20

DQ6

DQ1

14

19

DQ5

DQ2

15

18

DQ4

VSS

16

17

DQ3

AI02310

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Figure 4. Block Diagram

	VCC		A0-A16
		POWER	DQ0-DQ7
	E		131,072 x 8
			SRAM ARRAY
	VOLTAGE SENSE
	AND
	SWITCHING	E
	CIRCUITRY		W
			G
	INTERNAL
	BATTERY

RST BL

VSS

AI03608

OPERATION MODES

The M48Z129Y/V also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing data security in

Table 2. Operating Modes

the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery, maintaining data until valid power is restored.

VCC

Mode

E

G

W

DQ0-DQ7

Power

Deselect

VIH

X

X

High Z

Standby

WRITE

4.5 to 5.5V

VIL

X

VIL

DIN

Active

or

READ

VIL

VIL

VIH

DOUT

Active

3.0to 3.6V

READ

VIL

VIH

VIH

High Z

Active

Deselect

VSO to VPFD (min)(1)

X

X

X

High Z

CMOS Standby

Deselect

≤ VSO(1)

X

X

X

High Z

Battery Back-up Mode

Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10., page 12 for details.

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