STMicroelectronics M48T86 User Manual

FEAT URES SUMMARY

■ DROP-IN REPLACEMENT FOR PC

COMPUTER CLOCK/CALENDAR

■ COUNTS SECONDS, MINUTES, HOURS,

DAYS, DAY OF THE WEE K, DA TE, MO NTH,
and YEAR WITH LEAP YEAR
COMPENSATION

■ INTERFACED WITH SOFTWARE AS 128

RAM LOCATIONS:
– 14 Bytes of Clock and Control Registers
– 114 Bytes of General Purpose RAM

■ SELECTABLE BUS TIMING (Intel/Motorola)

■ THREE INTERRUPTS ARE SEPARATELY

SOFTWARE-MASKABL E and TESTABLE
– Time-of-Day Alarm (Once/Second to

Once/Day)
– Periodic Rates from 122µs to 500ms
– End-of-Clock Update Cycle

■ PROGRAMMABLE SQUA RE WAVE

OUTPUT

■ 10 YEARS OF DATA RETENTION AND

CLOCK OPERATION IN THE ABSENCE O F
POWER

■ SELF-CONTAINED BATTERY AND

CRYSTAL IN THE CAPHAT DIP PACKAG E

■ PACKAGING INCLUDES A 28-LEAD SOIC

and SNAPHAT
separately)

■ SOIC PACKAGE PROVIDES DIRECT

CONNECTION FOR A SNAPHAT TOP
CONTAINS THE BATTERY AND CRYSTAL

■ PIN AND FUNCTION COMPATIBLE WITH

bq3285/7A and DS12887

®

TOP (to be ordered

M48T86

5.0V PC Real-Ti me Clock

Figure 1. 24-pin PCDIP, CAPHAT™ Package

24

1

PCDIP24 (PC)
Battery/Crystal

CAPHAT

Figure 2. 28-pi n S O I C Package

SNAPHAT (SH)

Battery/Crystal

28

1

SOH28 (MH)

1/29April 2004

M48T86

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 24-pin PCDIP, CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. 24-pin DIP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

V

, VSS.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

CC

SQW (Square Wave Output). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

AD0-AD7 (Multiplexed Bi-Directional Address/Data Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

AS (Address Strobe Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

MOT (Mode Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DS (Data Strobe Input).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

E

(Chip Enable Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

IRQ

(Interrupt Request Output). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

RST

(Reset Input).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

RCL

(RAM Clear). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

R/W

(READ/WRITE Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Non-Volatile RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 7. Intel Bus READ AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 8. Intel Bus WRITE Mode AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 9. M oto rola Bus READ/WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Time, Calendar, and Alarm Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 10.Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Ti me , Calendar, and Alarm Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Periodic Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Alarm Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Update Cycle Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Oscillator Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Update Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Square Wave Output Se lection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 4. S quare Wave Frequency/Periodic Interrupt Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2/29

M48T86

Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

UIP. Update in Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

OSC0, OSC1, OSC2. Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RS3, RS2, RS1, RS0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. REGISTER A MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11.Update Period Timing and UIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PIE: Periodic Interrupt Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

AIE: Alarm Interrupt Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

UIE: Update Ended Interrupt Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

SQWE: Square Wave Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DM: Data Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

24/12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DSE. Daylight Savings Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 6. REGISTER B MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.Update-ended/Periodic Interrupt Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Register C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

IRQF: Interrupt Request Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PF: Periodic Interrupt Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

AF: Alarm Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

UF: Update Ended Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

BIT 0 through 3: Unused Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Register D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

VRT: Valid Ram And Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

BIT 0 through 6: Unused Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Table 7. REGISTER C MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8. REGISTER D MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

V

Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CC

Figure 13.Supply Voltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10.Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 14.AC Testing Load Circuit (No IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 15.AC Testing Load Circuit (with IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12.DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 16.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13.Power Down/Up Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14. Power Down/Up Trip Points DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 17.PCDIP24 – 24-pin Plastic DIP, battery CAPHAT, Package Outline . . . . . . . . . . . . . . . . 23

3/29

M48T86

Table 15. PCDIP24 – 24-pin Plastic DIP, battery CAPHAT, Package Mechanical Data. . . . . . . . . 23

Figure 18.SOH28 – 28-lead Plastic Small Outline, 4-socket SNAPHAT, Package Outline. . . . . . . 24

Table 16. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Pack. Mech. Data24

Figure 19.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 25

Table 17. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 25

Figure 20.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 26

Table 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 26

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 20.SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 21.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4/29

SUMMARY DESCRIPTIO N

The M48T86 is an industry standard Real Time
Clock (RTC). The M48T86 is com posed of a lithi­um energy source, quartz crystal, write protection
circuitry, and a 128-byte RAM array. This provides
the user with a complete subsystem packaged in
either a 24-pin DIP CAPHAT™ or 28-pin
SNAPHAT

®

SOIC. Functions available to the user
include a non-volatile time-of-day clock, alarm in­terrupts, a one-hundred-year clock with program­mable interrupts, square wave output, and 128
bytes of non-volatile static RAM.

The 24-pin, 600mil DIP CAPHAT houses the
M48T86 silicon with a quartz crystal and a long-life
lithium button cell in a single package.

The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at bot h ends for direct con­nection to a separate SNAPHAT

®

housing con-

Figure 3. Logic Diagram Table 1. Signal Names

V

CC

taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.

Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur­face-mounting. The SNAPHAT ho using is keyed
to prevent reverse insertion.

The SOIC and battery packages are shipped sep­arately in plastic anti-static tubes or in Tape & Reel
form.

For the 28-lead SOIC, the battery/crystal package
part number is “M4T28-BR12SH” (see Table

20., page 27).

AD0-AD7 Multiplexed Address/Data Bus

E

Chip Enable Input

M48T86

AD0-AD7

R/W

DS

AS
RST
RCL

MOT

8

E

M48T86

V

SS

SQW
IRQ

AI01640

R/W

DS Data Strobe Input

AS Address Strobe Input
RST
RCL

MOT Bus Type Select Input

SQW Square Wave Output

IRQ

V

CC

V

SS

NC Not Connected Internally

WRITE Enable Input

Reset Input
RAM Clear Input

Interrupt Request Output
(Open Drain)

Supply Voltage
Ground

5/29

M48T86

Figure 4. 24-pi n D I P Connections Figure 5. 28-pi n S O I C C onnections

1

MOT V

2

NC

3

NC

4

AD0

5

AD1

6

AD2
AD3
AD4
AD5
AD6

7
8
9
10

M48T86

11
12 13

V

SS

Figure 6. Block Diagram

24
23
22
21
20
19
18
17
16
15
14

AI01641

CC

SQW
NC
RCL
NC
IRQ
RST
DS
NC
R/W
ASAD7
E

1

MOT V

NC

NC
AD0
AD1
AD2
AD3
AD4
AD5
AD6

2
3
4
5
6
7
8
9
10
11

M48T86

12

V

SS

V

SS

13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI01642

NCNC

CC

SQW
NC
RCL
NC
IRQ
RST
DS
NC
R/W
ASAD7
E
NC

V

CC

V

BAT

DS

R/W

AS

AD0-AD7

OSCILLATOR

E

POWER

SWITCH

AND

WRITE

PROTECT

BUS

INTERFACE

V

CC

POK

/ 8 / 64 / 64

PERIODIC INTERRUPT/SQUARE WAVE SELECTOR

SQUARE WAVE

OUTPUT

REGISTERS A,B,C,D

CLOCK/

CALENDAR

UPDATE

BCD/BINARY
INCREMENT

CLOCK CALENDAR,

AND ALARM RAM

STORAGE
REGISTERS
(114 BYTES)

SQW

IRQ

RST

DOUBLE
BUFFERED

RCL

6/29

AI01643

OPERATION

Automatic deselection of the device ensures the

CC

fall

CC

to sta-

data integrity is not compromised s hould V
below specified Power-fail Deselect Voltage

) levels (see Figure 16., page 22). The auto-

(V

PFD

matic deselection of the device remains in effect
upon power up for a period of 200ms (max ) after

rises above V

V

CC

, provided that the Real

PFD

Time Clock is running and the count-down chain is
not reset. This allows sufficient time for V
bilize and gives the s ystem clock a wake-up period
so that a valid system rese t can be established.

The block diagram in Figure 6., page 6 shows the
pin connections and the major internal functions of
the M48T86.

Signal Description

, VSS. DC power is provided to the device on

V

CC

these pins.The M48T86 uses a 5V V

CC

.

SQW (Square Wave Output). During normal op­eration (e.g., valid V

), the SQW pin can output a

CC

signal from one of 13 taps. The freque ncy of the
SQW pin can be changed by programming Regis­ter A as shown in Table 4., page 14. The SQW sig­nal can be turned on a nd off using the SQWE Bit
(Register B; Bit 3). The SQW signal is not avail­able when V

is less than V

CC

PFD

.

AD0-AD7 (Multiplexed Bi-Directional Address/ Data Bus). The M48T86 provides a multiplexed

bus in which address an d data information s hare
the same signal path. The bus cycle consists of
two stages; first the address is latched, followed by
the data. Address/Data multiplexing does not slow

M48T86

the access time of the M48T86, because the bus
change from address to data occurs during the in­ternal RAM access time. Addre sses must be valid
prior to the falling edge of AS (see Figure

7., page 8), at which time the M48T86 la tches the

address present on AD 0-AD7. Valid W RITE data
must be present and held stable during the l atter
portion of the R/W
a READ cycle, the M4 8T86 output s 8 bits of data
during the latter portion of the DS pulse. The
READ cycle is terminated and the bus returns to a
high impedance state upon a high transition on R/

.

W AS (Address Strobe Inpu t). A positive going

pulse on the Address Strobe (AS) input serves to
demultiplex the bus. The falling edge of AS causes
the address present on AD0-AD7 to be latched
within the M48T86.

MOT (Mode Select). The MOT pin offers the flex­ibility to choose between two bus types (s ee Fig-

ure 9., page 9). When connected to V

bus timing is selected. When conne cted to V
left disconnected, Intel bus timing is selected. The
pin has an internal pull-down resistance of approx­imately 20KΩ.

DS (Data Strobe Input). The DS pin is also re­ferred to as READ (RD). A f alling edge transition on the Data Strobe (DS) inpu t enables the ou tput during a a READ cycle. This is very similar to an Output Enable (G es.

pulse (see Figure 8., page 9). In

, Motorola

CC

SS

or

) signal on other memory devic-

7/29

M48T86

E (Chip Enable Input). The Chip Enable pin

must be asserted low for a bus cycle in the
M48T86 to be accessed. Bus cycles which take
place without asserting E

will latch the addresses

present, but no data access will occur.

(Interrupt Request Output) . The IRQ pin is

IRQ

an open drain output that can be used as an inter­rupt input to a processor. The IRQ

output remains
low as long as the status bi t causing the i nterrupt
is present and the corresponding interrupt-enable
bit is set. IRQ
whenever Register C is read. The RST

returns to a high impedance state

pin can
also be used to clear pending interrupts. The IRQ
bus is an open drain output so it requires an exter­nal pull-up resistor to V

RST

(Reset Input). The M48T86 is reset when

the R ST

input is p ulled low. Wit h a vali d VCC ap-

plied and a low on RST

.

CC

, the following event s oc-

cur:

1. Periodic Interrupt Enable (PIE) Bit is cleared to

a zero (Register B; Bit 6);

2. Alarm Interrupt Enable (AIE) Bit is cleared to a

zero (Register B; Bit 5);

3. Update Ended Interrupt Request (UF) Bit is

cleared to a zero (Register C; Bit 4);

4. Interrupt Request (IRQF) Bit is cleared to a

zero (Register C Bit 7);

5. Periodic Interrupt Flag (PF) Bit is cleared to a
zero (Register C; Bit 6);

6. The device is not accessible until RST

is re-

turned high;

7. Alarm Interrupt Flag (AF) Bit is cleared to a
zero (Register C; Bit 5);

8. The IRQ

pin is in the high impedance state

9. Square Wave Output Enable (SQWE) Bit is
cleared to zero (Register B; Bit 3); and

10. Update Ended Interrupt Enable (UIE) is
cleared to a zero (Register B; Bit 4).

(RAM Clear). The RCL pin is used to c lear

RCL

all 114 storage bytes, excluding clock and control
registers, of the array to FF (hex) value. T he array
will be cleared when the RCL

pin is held low for at
least 100ms with the osc illator running. Usage of
this pin does not affect battery load. This function
is applicable only when V

(READ/WRITE Input). T he R/W pin is us ed

R/W

is applie d.

CC

to latch data into the M 48T86 and provides f unc­tionality si mi lar to W

in other memory systems.

Non-Volatile RAM

The 114 general-purpose non-volatile RAM bytes
are not dedicated to any special function within the
M48T86. They can be used by t he proces sor pro­gram as non-volatile me mory a nd are fully acces­sible during the update cycle.

Figure 7. Intel Bus READ AC Waveform

AS

DS

R/W

tDAS tCS tOD tCH

E

AD0-AD7

tCYC

tASDtASW

tDSL tDSH

tAS tAH tDHR

AI01647

8/29

Figu r e 8 . Intel Bus WRIT E Mode AC Waveform

AS

M48T86

tCYC

tDAS

DS

tDSL tDSH

R/W

tCS

E

tAS tAH

AD0-AD7

Figure 9. Motorola Bus READ/WRITE Mode AC Waveforms

AS

tDAS

DS

tASDtASW

tCYC

tASDtASW

tCH

tDW

tDHW

AI01648

R/W

E

AD0-AD7
(Write)

AD0-AD7
(Read)

tDSL

tRWS

tCS

tAH

tAS tDHW

tAS tOD

tAH

tDSH

tRWH

tCH

tDW

tDHR

AI01649

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