STMicroelectronics M48T58, M48T58Y User Manual

M48T58

M48T58Y

5.0V, 64 Kbit (8 Kb x8) TIMEKEEPER® SRAM

FEATURES SUMMARY

■INTEGRATED, ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT AND BATTERY

■BYTEWIDE™ RAM-LIKE CLOCK ACCESS

■BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, AND SECONDS

■FREQUENCY TEST OUTPUT FOR REAL TIME CLOCK

■AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION

■WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage):

–M48T58: VCC = 4.75 to 5.5V 4.5V ≤ VPFD ≤ 4.75V

–M48T58Y: VCC = 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V

■SELF-CONTAINED BATTERY and CRYSTAL IN THE CAPHAT™ DIP PACKAGE

■PACKAGING INCLUDES A 28-LEAD SOIC AND SNAPHAT® TOP (to be ordered separately)

■SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT HOUSING CONTAINING THE BATTERY AND CRYSTAL

■PIN AND FUNCTION COMPATIBLE WITH JEDEC STANDARD 8 Kb x8 SRAMs

Figure 1. 28-pin PCDIP, CAPHAT™ Package

28

1

PCDIP28 (PC)

Battery/Crystal

CAPHAT

Figure 2. 28-pin SOIC Package

SNAPHAT (SH)

Battery/Crystal

28

1

SOH28 (MH)

April 2004

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M48T58, M48T58Y

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 28-pin PCDIP, CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 8. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Battery Low Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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M48T58, M48T58Y

Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 15.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline . . . . . . . . . . . . . . . . 21 Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data. . . . . . . . . 21 Figure 16.SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline. 22 Table 13. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Pack. Mech. Data 22 Figure 17.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 23 Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 23 Figure 18.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 24 Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 24

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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M48T58, M48T58Y

SUMMARY DESCRIPTION

The M48T58/Y TIMEKEEPER® RAM is a 8Kb x 8 non-volatile static RAM and real time clock. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution.

The M48T58/Y is a non-volatile pin and function equivalent to any JEDEC standard 8Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.

The 28-pin, 600mil DIP CAPHAT™ houses the M48T58/Y silicon with a quartz crystal and a long life lithium button cell in a single package.

The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT® housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic antistatic tubes or in Tape & Reel form.

For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4T28BR12SH” (see Table 17., page 25).

Figure 3. Logic Diagram

	VCC
13	8
A0-A12	DQ0-DQ7

W

M48T58

E1 M48T58Y FT

E2

G

VSS

AI01374B

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Table 1. Signal Names

A0-A12						Address Inputs
DQ0-DQ7						Data Inputs / Outputs
	FT					Frequency Test Output (Open
						Drain)
						Chip Enable 1
	E1
	E2					Chip Enable 2
						Output Enable
		G
						WRITE Enable
		W
VCC						Supply Voltage
VSS						Ground

M48T58, M48T58Y

Figure 4. DIP Connections

FT	1		28	VCC
A12	2		27	W
A7	3		26	E2
A6	4		25	A8
A5	5		24	A9
A4	6		23	A11
A3	7		22
		M48T58		G
A2	8	M48T58Y	21	A10
A1	9		20
				E1
A0	10		19	DQ7
DQ0	11		18	DQ6
DQ1	12		17	DQ5
DQ2	13		16	DQ4
VSS	14		15	DQ3
		AI01375B

Figure 5. SOIC Connections

FT					VCC
	1		28
A12	2		27		W
A7	3		26		E2
A6	4		25		A8
A5	5		24		A9
A4	6		23		A11
A3	7		22
		M48T58Y			G
A2	8		21		A10
A1	9		20
					E1
A0	10		19		DQ7
DQ0	11		18		DQ6
DQ1	12		17		DQ5
DQ2	13		16		DQ4
VSS	14		15		DQ3
		AI01376B

Figure 6. Block Diagram

FT
OSCILLATOR AND	8 x 8 BiPORT
CLOCK CHAIN
	SRAM ARRAY
32,768 Hz
CRYSTAL		A0-A12
	POWER
	8184 x 8	DQ0-DQ7
LITHIUM	SRAM ARRAY
CELL		E1
VOLTAGE SENSE	VPFD	E2
AND		W
SWITCHING
CIRCUITRY		G
VCC	VSS	AI01377C

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M48T58, M48T58Y

OPERATION MODES

As Figure 6., page 5 shows, the static memory array and the quartz controlled clock oscillator of the M48T58/Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour BCD format (except for the century). Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.

The eight clock bytes are not the actual clock counters themselves; they are memory locations

Table 2. Operating Modes

consisting of BiPORT™ READ/write memory cells. The M48T58/Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array.

The M48T58/Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out-of-tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns.

VCC

Mode

E1

E2

G

W

DQ0-DQ7

Power

Deselect

VIH

X

X

X

High Z

Standby

Deselect

4.75 to 5.5V

X

VIL

X

X

High Z

Standby

WRITE

VIL

VIH

X

VIL

DIN

Active

or

4.5 to 5.5V

READ

VIL

VIH

VIL

VIH

DOUT

Active

READ

VIL

VIH

VIH

VIH

High Z

Active

Deselect

VSO to VPFD (min)(1)

X

X

X

X

High Z

CMOS Standby

Deselect

≤ VSO(1)

X

X

X

X

High Z

Battery Back-up Mode

Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.

1. See Table 11., page 20 for details.

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M48T58, M48T58Y

READ Mode

The M48T58/Y is in the READ Mode whenever W (WRITE Enable) is high, E1 (Chip Enable 1) is low, and E2 (Chip Enable 2) is high. The unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O

pins within Address Access time (tAVQV) after the last address input signal is stable, providing that

the E1, E2, and G access times are also satisfied. If the E1, E2 and G access times are not met, valid data will be available after the latter of the Chip En-

able Access times (tE1LQV or tE2HQV) or Output Enable Access time (tGLQV).

The state of the eight three-state Data I/O signals is controlled by E1, E2 and G. If the outputs are ac-

tivated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address

Inputs are changed while E1, E2 and G remain active, output data will remain valid for Output Data

Hold time (tAXQX) but will go indeterminate until the next Address Access.

Figure 7. READ Mode AC Waveforms

A0-A12

tAVAV

VALID

tAVQV

tAXQX

tE1LQV

tE1HQZ

E1

tE1LQX

E2

tE2HQV

tE2LQZ

tE2HQX

tGLQV

tGHQZ

G

tGLQX

DQ0-DQ7

VALID

AI00962

Note: WRITE Enable

= High.

(W)

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M48T58, M48T58Y

Table 3. READ Mode AC Characteristics

Symbol		Parameter(1)			M48T58/Y		Unit
				Min		Max
tAVAV	READ Cycle Time			70			ns
tAVQV	Address Valid to Output Valid					70	ns
tE1LQV	Chip Enable 1 Low to Output Valid					70	ns
tE2HQV	Chip Enable 2 High to Output Valid					70	ns
tGLQV	Output Enable Low to Output Valid					35	ns
tE1LQX(2)	Chip Enable 1	Low to Output Transition		5			ns
tE2HQX(2)	Chip Enable 2	High to Output Transition		5			ns
tGLQX(2)	Output Enable Low to Output Transition			5			ns
tE1HQZ(2)	Chip Enable 1	High to Output Hi-Z				25	ns
tE2LQZ(2)	Chip Enable 2	Low to Output Hi-Z				25	ns
tGHQZ(2)	Output Enable High to Output Hi-Z					25	ns
tAXQX	Address Transition to Output Transition			10			ns

Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 5pF.

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M48T58, M48T58Y

WRITE Mode

The M48T58/Y is in the WRITE Mode whenever W and E1 are low and E2 is high. The start of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2. The addresses must be held valid throughout the cycle. E1 or W

must return high or E2 low for a minimum of tE1HAX or tE2LAX from Chip Enable or tWHAX from WRITE

Enable prior to the initiation of another READ or

WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cy-

cles to avoid bus contention; although, if the output bus has been activated by a low on E1 and G and a high on E2, a low on W will disable the outputs tWLQZ after W falls.

Figure 8. WRITE Enable Controlled, WRITE AC Waveform

	tAVAV
A0-A12	VALID
	tAVWH
tAVE1L	tWHAX
E1
tAVE2H
E2
	tWLWH
tAVWL
W
tWLQZ	tWHQX
	tWHDX
DQ0-DQ7	DATA INPUT

tDVWH

AI00963

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