STMicroelectronics M48T37Y, M48T37V User Manual
5.0 or 3.3V, 256 Kbit (32 Kbit x8) TIMEKEEPER® SRAM
FEAT URES SUMMARY
■ INTEGRATED ULTRA-L OW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, AND BATTERY
■ FREQUENCY TEST OUTPUT FOR REAL
TIME CLOCK SOFTWARE CALIBRATION
■ YEAR 2000 COMPLIANT
■ AUTOMATIC POWER-FAIL CHIP
DESELECT and WRITE PR OTEC T ION
■ WATCHDOG TIMER
■ WRITE PROTECT VOLTAGE
= Power-Fail Deselect Voltage):
(V
PFD
– M48T37Y: V
4.2V ≤ V
– M48T37V: V
2.7V ≤ V
■ PACKAGING INCLUDES A 44-LEAD SOIC
AND SNAPHAT
separately)
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL
■ MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
■ PROGRAMMABLE ALAR M OUTPUT
ACTIVE IN THE BATTERY BACK-UP MODE
■ BATTERY LOW FLAG
= 4.5 to 5.5V
CC
≤ 4.5V
PFD
= 3.0 to 3.6V
CC
≤ 3.0V
PFD
®
TOP (to be ordered
M48T37Y
M48T37V
Figure 1. Package
SNAPHAT (SH)
Battery/Crystal
44
1
SOH44 (MH)
44-pin SOIC
1/29April 2004
M48T37Y, M48T37V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. RE A D Mode AC Charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reading the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Alarm Interrupt Reset Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 6. A larm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 9. Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Programmable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
Battery Low Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
Table 7. Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
V
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CC
Figure 10.Supply Voltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.Clock Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/29
M48T37Y, M48T37V
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11.DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
Figure 14.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12.Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13.Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15.SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Outline. . . . . . . 24
Table 14. SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Mech. Data . . . 24
Figure 16.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 25
Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 25
Figure 17.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 26
Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18.SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
M48T37Y, M48T37V
SUMMARY DESCRIPTION
The M48T37Y/V TIMEKEEPER® RAM is a 32 Kb
x8 non-volatile static RAM and real time clock. The
monolithic chip is availab le in a special package
which provides a highly integrated battery backedup memory and real time clock solution.
The 44-lead, 330mil SOIC package provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT housing
containing the battery and crystal. The unique design allows the SNAPHAT
®
battery/crystal package to be mounted o n top of the SOIC package
after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
Figure 2. Logic Diagram Table 1. Signal Names
to the high temperatures required for device surface-mounting. The SNAPHAT ho using is keyed
to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape &Reel
form. For the 44-lead SOIC, the battery/crystal
package (e.g., SNAPHAT) part number is “M4T28BR12SH” or “M4T32-BR12SH” (see Table
18., page 27).
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
A0-A14
W
WDI
V
CC
15
M48T37Y
E
G
M48T37V
V
SS
8
DQ0-DQ7
RST
IRQ/FT
AI02172
A0-A14 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
RST
/FT
IRQ
WDI Watchdog Input
E
G
W
V
CC
V
SS
NC Not connected Internally
Reset Output (Open Drain)
Interrupt / Frequency Test Output
(Open Drain)
Chip Enable
Output Enable
WRITE Enable
Supply Voltage
Ground
4/29
Figure 3. SOIC Connections
M48T37Y, M48T37V
NC
RST
NC
NC
A14
A12
A7
A6
A5
A4
A3
NC
NC
WDI
A2
A1
A0
DQ0
DQ2
NC
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
M48T37Y
M48T37V
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
AI02174
V
CC
NC
NC
NC
IRQ/FT
W
A13
A8
A9
A11
G
NC
NC
A10
E
NC
DQ7
DQ6
DQ5DQ1
DQ4
DQ3
NC
5/29
M48T37Y, M48T37V
Figure 4. Block Diagram
32,768 Hz
CRYSTAL
IRQ/FT WDI
OSCILLATOR AND
CLOCK CHAIN
16 x 8 BiPORT
SRAM ARRAY
POWER
A0-A14
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
CC
RSTV
V
PFD
32,752 x 8
SRAM ARRAY
V
SS
DQ0-DQ7
E
W
G
AI03253
6/29
OPERATION MODES
As Figure 4., page 6 shows, the static memory array and the quartz controlled clock oscillator of the
M48T37Y/V are integrated on one silicon chip.
The memory locations that provide user accessible BYTEWIDE™ clock information are in the
bytes with addresses 7FF1 and 7FF9h-7FFFh (located in Table 5., page 13). The clock locations
contain the century, year, month, date, day, hour,
minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until the year
2100), 30, and 31 day months are made automatically.
Byte 7FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
Byte 7FF7h contains the watchdog timer setting.
The watchdog timer redirects an out-of-control microprocessor and provides a reset or interrupt to it.
Bytes 7FF2h-7FF5h a re reserved for clock alarm
programming. These bytes can be used to set the
alarm. Th is will generate an active low sig nal on
Table 2. Operating Modes
4.5 to 5.5V
3.0 to 3.6V
to V
SO
≤ V
V
PFD
or
SO
CC
(min)
(1)
(1)
E G W DQ0-DQ7 Power
V
IH
V
IL
V
IL
V
IL
X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode
Mode
Deselect
WRITE
READ
READ
Deselect
Deselect
Note: X = VIH or VIL; VSO = Batte ry Back -u p S wi tchover Voltage.
1. See Table 13., page 23 for details.
V
M48T37Y, M48T37V
the I RQ
date, hours, minutes, and seconds of the clock.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory
cells. The M48T37Y/V includes a clock control circuit which updates the clock bytes with current information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T37Y/V also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single V
condition. When V
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable system operation brought on by low V
below the Battery Back-up Switchover Voltage
(V
which maintains data and clock operation until valid power returns.
X X High Z Standby
X
V
IL
V
IH
/FT pin when the alarm bytes match the
supply for an out of tolerance
CC
is out of tolerance, the circuit
CC
. As VCC falls
CC
), the control circuitry connects the battery
SO
V
IL
V
IH
V
IH
D
IN
D
OUT
High Z Active
Active
Active
7/29
M48T37Y, M48T37V
READ Mode
The M48T37Y/V is in the READ Mode whenever
WRITE Enable (W
low. The unique address specified by the 15 Address Inputs defines which one of the 32,752 bytes
of data is to be acces sed . Vali d data w ill be av ailable at the Data I/O pi ns within Address Access
time (t
) after the last address input signal is
AVQV
stable, providing that the E
access times are also satisfied. If the E
cess times are not met, valid data will be available
Figure 5. READ Mode AC Waveforms
) is high and Chip Enable (E) is
and Output Enable (G)
and G ac-
after the latter of the Chip Enable Access time
) or Output Enable Access time (t
(t
ELQV
The state of the eight t hree-state Da ta I/O si gnals
is controlled by E
ed before t
indeterminate state until t
and G. If the outputs are activat-
, the data lines will be driven to an
AVQV
AVQV
.
If the Address Inputs are changed while E
remain active, output data will remain valid for Output Data Hold time (t
) but will be indetermi-
AXQX
nate until the next Address Access.
tAVAV
GLQV
and G
).
A0-A14
tAVQV tAXQX
tELQV
E
tELQX
tGLQV
G
tGLQX
DQ0-DQ7
Note: WRITE Enabl e (W) = High.
VALID
tEHQZ
tGHQZ
VALID
AI00925
Table 3. READ Mode AC Characteristics
M48T37Y M48T37V
Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. Vali d fo r Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5. 5V or 3.0 to 3.6V (except wh ere not ed ).
2. C
READ Cycle Time 70 100 ns
Address Valid to Output Valid 70 100 ns
Chip Enable Low to Output Valid 70 100 ns
Output Enable Low to Output Valid 35 50 ns
(2)
Chip Enable Low to Output Transition 5 10 ns
(2)
Output Enable Low to Output Transition 5 5 ns
(2)
Chip Enable High to Output Hi-Z 25 50 ns
(2)
Output Enable High to Output Hi-Z 25 40 ns
Address Transition to Output Transition 10 10 ns
= 5pF.
L
Parameter
(1)
Unit–70 –100
Min Max Min Max
8/29
WRITE Mode
The M48T37Y/V is in the WRITE M ode whenev er
and E are low. The start of a WRITE is refer-
W
enced from the latter occurring falling edge of W
. A WRITE is terminated by the earlier rising
E
edge of W
throughout the cycle. E
a minimum of t
or E. The addresses must be held valid
or W must return high for
from Chip Enable or t
EHAX
or
WHAX
er READ or WRITE cycle. Data-in must be valid t
prior to the end of WRITE and remain valid for
VWH
t
WHDX
WRITE cycles to avoid bus contention; however, if
the output bus has b een activated by a low on E
and G, a low on W will disable the outputs t
after W falls.
from WRITE Enable prior to the initiation of anoth-
Figure 6. WRITE Enable Controlled, WRITE AC Waveform
tAVAV
M48T37Y, M48T37V
D-
afterward. G should be kept high during
WLQZ
A0-A14
tAVEL
E
tAVWL
W
tWLQZ
DQ0-DQ7
VALID
tAVWH
tWLWH
Figure 7. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A14
tAVEL
VALID
tAVEH
tELEH
tDVWH
tWHAX
tWHQX
tWHDX
DATA INPUT
AI00926
tEHAX
E
W
DQ0-DQ7
tAVWL
DATA INPUT
tDVEH
tEHDX
AI00927
9/29
Loading...