5.0 or 3.3V, 256 Kbit (32 Kbit x8) TIMEKEEPER® SRAM
FEAT URES SUMMARY
■ INTEGRATED ULTRA-L OW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, AND BATTERY
■ FREQUENCY TEST OUTPUT FOR REAL
TIME CLOCK SOFTWARE CALIBRATION
■ YEAR 2000 COMPLIANT
■ AUTOMATIC POWER-FAIL CHIP
DESELECT and WRITE PR OTEC T ION
■ WATCHDOG TIMER
■ WRITE PROTECT VOLTAGE
= Power-Fail Deselect Voltage):
(V
PFD
– M48T37Y: V
4.2V ≤ V
– M48T37V: V
2.7V ≤ V
■ PACKAGING INCLUDES A 44-LEAD SOIC
AND SNAPHAT
separately)
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL
■ MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
■ PROGRAMMABLE ALAR M OUTPUT
ACTIVE IN THE BATTERY BACK-UP MODE
■ BATTERY LOW FLAG
= 4.5 to 5.5V
CC
≤ 4.5V
PFD
= 3.0 to 3.6V
CC
≤ 3.0V
PFD
®
TOP (to be ordered
M48T37Y
M48T37V
Figure 1. Package
SNAPHAT (SH)
Battery/Crystal
44
1
SOH44 (MH)
44-pin SOIC
1/29April 2004
M48T37Y, M48T37V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. RE A D Mode AC Charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reading the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Alarm Interrupt Reset Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 6. A larm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 9. Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Programmable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
Battery Low Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
Table 7. Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
V
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CC
Figure 10.Supply Voltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.Clock Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/29
M48T37Y, M48T37V
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11.DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
Figure 14.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12.Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13.Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15.SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Outline. . . . . . . 24
Table 14. SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Mech. Data . . . 24
Figure 16.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 25
Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 25
Figure 17.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 26
Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18.SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
M48T37Y, M48T37V
SUMMARY DESCRIPTION
The M48T37Y/V TIMEKEEPER® RAM is a 32 Kb
x8 non-volatile static RAM and real time clock. The
monolithic chip is availab le in a special package
which provides a highly integrated battery backedup memory and real time clock solution.
The 44-lead, 330mil SOIC package provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT housing
containing the battery and crystal. The unique design allows the SNAPHAT
®
battery/crystal package to be mounted o n top of the SOIC package
after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
Figure 2. Logic Diagram Table 1. Signal Names
to the high temperatures required for device surface-mounting. The SNAPHAT ho using is keyed
to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape &Reel
form. For the 44-lead SOIC, the battery/crystal
package (e.g., SNAPHAT) part number is “M4T28BR12SH” or “M4T32-BR12SH” (see Table
18., page 27).
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
A0-A14
W
WDI
V
CC
15
M48T37Y
E
G
M48T37V
V
SS
8
DQ0-DQ7
RST
IRQ/FT
AI02172
A0-A14 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
RST
/FT
IRQ
WDI Watchdog Input
E
G
W
V
CC
V
SS
NC Not connected Internally
Reset Output (Open Drain)
Interrupt / Frequency Test Output
(Open Drain)
Chip Enable
Output Enable
WRITE Enable
Supply Voltage
Ground
4/29
Figure 3. SOIC Connections
M48T37Y, M48T37V
NC
RST
NC
NC
A14
A12
A7
A6
A5
A4
A3
NC
NC
WDI
A2
A1
A0
DQ0
DQ2
NC
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
M48T37Y
M48T37V
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
AI02174
V
CC
NC
NC
NC
IRQ/FT
W
A13
A8
A9
A11
G
NC
NC
A10
E
NC
DQ7
DQ6
DQ5DQ1
DQ4
DQ3
NC
5/29
M48T37Y, M48T37V
Figure 4. Block Diagram
32,768 Hz
CRYSTAL
IRQ/FT WDI
OSCILLATOR AND
CLOCK CHAIN
16 x 8 BiPORT
SRAM ARRAY
POWER
A0-A14
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
CC
RSTV
V
PFD
32,752 x 8
SRAM ARRAY
V
SS
DQ0-DQ7
E
W
G
AI03253
6/29
OPERATION MODES
As Figure 4., page 6 shows, the static memory array and the quartz controlled clock oscillator of the
M48T37Y/V are integrated on one silicon chip.
The memory locations that provide user accessible BYTEWIDE™ clock information are in the
bytes with addresses 7FF1 and 7FF9h-7FFFh (located in Table 5., page 13). The clock locations
contain the century, year, month, date, day, hour,
minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until the year
2100), 30, and 31 day months are made automatically.
Byte 7FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
Byte 7FF7h contains the watchdog timer setting.
The watchdog timer redirects an out-of-control microprocessor and provides a reset or interrupt to it.
Bytes 7FF2h-7FF5h a re reserved for clock alarm
programming. These bytes can be used to set the
alarm. Th is will generate an active low sig nal on
Table 2. Operating Modes
4.5 to 5.5V
3.0 to 3.6V
to V
SO
≤ V
V
PFD
or
SO
CC
(min)
(1)
(1)
E G W DQ0-DQ7 Power
V
IH
V
IL
V
IL
V
IL
X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode
Mode
Deselect
WRITE
READ
READ
Deselect
Deselect
Note: X = VIH or VIL; VSO = Batte ry Back -u p S wi tchover Voltage.
1. See Table 13., page 23 for details.
V
M48T37Y, M48T37V
the I RQ
date, hours, minutes, and seconds of the clock.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory
cells. The M48T37Y/V includes a clock control circuit which updates the clock bytes with current information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T37Y/V also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single V
condition. When V
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable system operation brought on by low V
below the Battery Back-up Switchover Voltage
(V
which maintains data and clock operation until valid power returns.
X X High Z Standby
X
V
IL
V
IH
/FT pin when the alarm bytes match the
supply for an out of tolerance
CC
is out of tolerance, the circuit
CC
. As VCC falls
CC
), the control circuitry connects the battery
SO
V
IL
V
IH
V
IH
D
IN
D
OUT
High Z Active
Active
Active
7/29
M48T37Y, M48T37V
READ Mode
The M48T37Y/V is in the READ Mode whenever
WRITE Enable (W
low. The unique address specified by the 15 Address Inputs defines which one of the 32,752 bytes
of data is to be acces sed . Vali d data w ill be av ailable at the Data I/O pi ns within Address Access
time (t
) after the last address input signal is
AVQV
stable, providing that the E
access times are also satisfied. If the E
cess times are not met, valid data will be available
Figure 5. READ Mode AC Waveforms
) is high and Chip Enable (E) is
and Output Enable (G)
and G ac-
after the latter of the Chip Enable Access time
) or Output Enable Access time (t
(t
ELQV
The state of the eight t hree-state Da ta I/O si gnals
is controlled by E
ed before t
indeterminate state until t
and G. If the outputs are activat-
, the data lines will be driven to an
AVQV
AVQV
.
If the Address Inputs are changed while E
remain active, output data will remain valid for Output Data Hold time (t
) but will be indetermi-
AXQX
nate until the next Address Access.
tAVAV
GLQV
and G
).
A0-A14
tAVQV tAXQX
tELQV
E
tELQX
tGLQV
G
tGLQX
DQ0-DQ7
Note: WRITE Enabl e (W) = High.
VALID
tEHQZ
tGHQZ
VALID
AI00925
Table 3. READ Mode AC Characteristics
M48T37Y M48T37V
Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. Vali d fo r Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5. 5V or 3.0 to 3.6V (except wh ere not ed ).
2. C
READ Cycle Time 70 100 ns
Address Valid to Output Valid 70 100 ns
Chip Enable Low to Output Valid 70 100 ns
Output Enable Low to Output Valid 35 50 ns
(2)
Chip Enable Low to Output Transition 5 10 ns
(2)
Output Enable Low to Output Transition 5 5 ns
(2)
Chip Enable High to Output Hi-Z 25 50 ns
(2)
Output Enable High to Output Hi-Z 25 40 ns
Address Transition to Output Transition 10 10 ns
= 5pF.
L
Parameter
(1)
Unit–70 –100
Min Max Min Max
8/29
WRITE Mode
The M48T37Y/V is in the WRITE M ode whenev er
and E are low. The start of a WRITE is refer-
W
enced from the latter occurring falling edge of W
. A WRITE is terminated by the earlier rising
E
edge of W
throughout the cycle. E
a minimum of t
or E. The addresses must be held valid
or W must return high for
from Chip Enable or t
EHAX
or
WHAX
er READ or WRITE cycle. Data-in must be valid t
prior to the end of WRITE and remain valid for
VWH
t
WHDX
WRITE cycles to avoid bus contention; however, if
the output bus has b een activated by a low on E
and G, a low on W will disable the outputs t
after W falls.
from WRITE Enable prior to the initiation of anoth-
Figure 6. WRITE Enable Controlled, WRITE AC Waveform
tAVAV
M48T37Y, M48T37V
D-
afterward. G should be kept high during
WLQZ
A0-A14
tAVEL
E
tAVWL
W
tWLQZ
DQ0-DQ7
VALID
tAVWH
tWLWH
Figure 7. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A14
tAVEL
VALID
tAVEH
tELEH
tDVWH
tWHAX
tWHQX
tWHDX
DATA INPUT
AI00926
tEHAX
E
W
DQ0-DQ7
tAVWL
DATA INPUT
tDVEH
tEHDX
AI00927
9/29
M48T37Y, M48T37V
Table 4. WRITE Mode AC Characteristics
M48T37Y M48T37V
Symbol
Parameter
(1)
Min Max Min Max
t
AVAV
t
AVWL
t
AVEL
t
WLWH
t
ELEH
t
WHAX
t
EHAX
t
DVWH
t
DVEH
t
WHDX
t
EHDX
(2,3)
t
WLQZ
t
AVWH
t
AVEH
(2,3)
t
WHQX
Note: 1. Vali d fo r Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5. 5V or 3.0 to 3.6V (except wh ere not ed ).
2. C
L
3. If E
WRITE Cycle Time 70 100 ns
Address Valid to WRITE Enable Low 0 0 ns
Address Valid to Chip Enable Low 0 0 ns
WRITE Enable Pulse Width 50 80 ns
Chip Enable Low to Chip Enable High 55 80 ns
WRITE Enable High to Address Transition 0 10 ns
Chip Enable High to Address Transition 0 10 ns
Input Valid to WRITE Enable High 30 50 ns
Input Valid to Chip Enable High 30 50 ns
WRITE Enable High to Input Transition 5 5 ns
Chip Enable High to Input Transition 5 5 ns
WRITE Enable Low to Output Hi-Z 25 50 ns
Address Valid to WRITE Enable High 60 80 ns
Address Valid to Chip Enable High 60 80 ns
WRITE Enable High to Output Transition 5 10 ns
= 5pF.
goes low simultaneously with W going low, the outp uts remain in the high impeda nce state.
Unit–70 –100
10/29
Data Retention Mode
With valid V
applied, the M48T37Y/V operat es
CC
as a conventional BYTEWIDE™ static RAM.
Should the Supply Voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself whe n V
falls within the V
CC
PFD
(max), V
PFD
(min) window. All outputs become high impedance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently a ddressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
(min), the user can be
PFD
assured the memory will be i n a write protected
state, provided the V
fall time is not less than tF.
CC
The M48T37Y/V may respond to transient noise
spikes on V
that reach into the deselect window
CC
M48T37Y, M48T37V
during the time the device is sampling V
fore, decoupling of t he power supply l ines is recommended.
When V
drops below VSO, the control circuit
CC
switches power to the internal battery which preserves data and powers the clock. The internal
button cell will maintain data in the M48T37Y/V for
an accumulated period of at least 7 years at room
temperature when V
tem power returns and V
is less than VSO. As sys-
CC
rises above VSO, the
CC
battery is disconnected and the power supply is
switched to external V
can resume t
after VCC reaches V
REC
. Normal RAM operation
CC
For more information on Battery Storage Life refer
to the Application Note AN1012.
CC
PFD
. There-
(max).
11/29
M48T37Y, M48T37V
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER
be halted before clock data is read to prevent
reading data in transition. The BiPORT ™ TIMEKEEPER cel ls in th e R AM a r ra y are onl y d a ta registers and not the actual clock counters, so
updating the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register 7FF8h. As
long as a '1' remains in that position , updating is
halted. After a h alt is issu ed, the registers reflect
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in
progress. Updating will resume within a second after th e bi t i s reset to a ' 0 .'
Setting the Clock
Bit D7 of the Control Register (7FF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER registers. The user can then load t hem with the cor-
®
registers should
rect day, date, and time data in 24 hour BCD
format (see Table 5., page 13). Resetting the
WRITE Bit to a '0' then transfers the values of all
time registers (7FF1h, 7FF9h-7FFFh) to the actual
TIMEKEEPER counters and allows normal operation to resume. After the WRITE Bit is reset, the
next clock update will occ ur in approxi mately one
second.
Note: Upon power-up following a power failure,
both the WRITE Bit and the READ Bit will be reset
to '0.'
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. W hen reset to a '0,' the
M48T37Y/V oscillator starts within one second.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
12/29
M48T37Y, M48T37V
Table 5. Register Map
Address
Data
D7 D6 D5 D4 D3 D2 D1 D0
7FFFh 10 Years Year Year 00-99
7FFEh 0 0 0 10 M Month Month 01-12
7FFDh 0 0 10 Date Date: Day of Month Date 01-31
7FFCh 0 FT 0 0 0 Day of Week Day 01-7
7FFBh 0 0 10 Hours Hours Hours 00-23
7FFAh 0 10 Minutes Minutes Min 00-59
7FF9h ST 10 Seconds Seconds Sec 00-59
7FF8h W R S Calibration Control
7FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
7FF6hAFE0ABE00000Interrupts
7FF5h RPT4 0 AIarm 10 Date Alarm Date Alarm Date 01-31
7FF4h RPT3 0 AIarm 10 Hours Alarm Hours Alarm Hour 00-23
7FF3h RPT2 Alarm 10 Minutes Alarm Minutes Alarm Min 00-59
7FF2h RPT1 Alarm 10 Seconds Alarm Seconds Alarm Sec 00-59
Function/Range
BCD Format
7FF1h 1000 Year 100 Year Century 00-99
7FF0h WDF AF Z BL Z Z Z Z Flags
Keys : S = Si gn Bit
FT = Frequency Test Bit
R = READ Bit
W = WRITE B i t
ST = Stop Bit
0 = Must be set to '0'
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
AFE = Alarm Flag Enable Flag
RB0-RB 1 = Watchdog Res olution Bits
WDS = Watchdog Steering B i t
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RP T 4 = Alarm Repeat M ode Bits
WDF = Watchdog Flag (Read only)
AF = Alarm Flag (Read only)
Z = '0' and are Read only
13/29
M48T37Y, M48T37V
Setting the Alarm Clock
Registers 7FF5h-7FF2h contain the alarm settings. The alarm can be configured to go off at a
predetermined time on a specific day of the month
or repeat every day, hour, minute, or second . It
can also be programmed to go off while the
M48T37Y/V is in the battery back-up mode of operation to serve as a system wake-up call.
RPT1-RPT4 put the alarm in the repeat mode of
operation. Table 6 shows the possible configurations. Codes not listed in the table default to the
once per second mode t o qu ickly alert the us er of
an incorrect alarm setting.
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the m atch criteria d efined
by RPT1-RPT4, AF is set. If AFE is also set, the
alarm condition activates the IRQ
Figure 8. Alarm Interrupt Reset Waveform
/FT pin. To dis-
able alarm, write '0' to the Alarm Date registers
and RPT1-4. The alarm flag and th e IRQ
/FT ou tput are cleared by a RE AD to the Flags Regi ster
as shown in Figure 8. A subseq uent READ of the
Flags Register is necessary to see that the value
of the Alarm Flag has been reset to '0.'
The IRQ
tery back-up mode. The IRQ
/FT pin can also be activated in the bat-
/FT will go low if an
alarm occurs and both the Alarm in Battery Backup Mode Enable (ABE) and the A FE are set. The
ABE and AFE bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M48T37Y/V was in the deselect mode during power-up. Figure 9., page 15 illustrates the back-up mode alarm timing.
A0-A14
ACTIVE FLAG BIT
IRQ/FT
ADDRESS 7FF0h
15ns Min
Table 6. Alarm Repeat Modes
RPT4 RPT3 RPT2 RPT1 Alarm Activated
1 1 1 1 Once per Second
1 1 1 0 Once per Minute
1 1 0 0 Once per Hour
1 0 0 0 Once per Day
0 0 0 0 Once per Month
AI01677B
14/29
Figure 9. Back-up Mode Alarm Waveforms
M48T37Y, M48T37V
V
CC
V
(max)
PFD
V
(min)
PFD
V
SO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
HIGH-Z
Calibrating the Clock
The M48T37Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed ±35 PPM
(parts per million) oscillator frequency error at
25 °C, which equates to abou t ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T37Y/V improves to better
than +1/–2 PPM at 25 °C.
The oscillation rate of any crystal changes with
temperature (see Figure 11., page 19). Most cl ock
chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. The M48T37Y/V design, how ever, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 12., page 19. T he num ber of time s pulses are
blanked (subtracted, negat ive calibration) or split
(added, positive calibration) depends upon the
value loaded into the five-bit Calibration byte found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negat ive
calibration. Calibration occurs within a 64 m inute
cycle. The first 62 m inut es i n t he c ycle m ay , once
tREC
HIGH-Z
AI03254B
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has t he effect of
adding 512 or subtracting 256 oscillator cycles for
every 125, 829, 120 (64 minutes x 60 seconds/
minute x 32,768 cycles/second) actual oscillator
cycles, that is +4.068 or –2.034 PPM of adjustment per calibration step in the calibration register.
Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increment s in the
Calibration Byte would represent +10.7 or –5.35
seconds per month which correspond s to a total
range of +5.5 or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T37Y/V may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accurate reference (like WWW broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his environment may require, even after the final product
is packaged in a non-user serviceable enclosure.
All the designer has to do is provide a simple utility
that accesses the Calibration Byte.
15/29
M48T37Y, M48T37V
The second approach is better suited t o a manufacturing environment, and involves the use of the
/FT pin. The pin will toggle at 512 Hz when the
IRQ
Stop Bit (ST, D7 of 7FF9h) is '0' the Frequency
Test Bit (FT, D6 of 7FFCh) is '1,' t he Alarm Flag
Enable Bit (AFE, D7 of 7FF6h) is '0,' and the
Watchdog Steering Bit (WDS, D7 of 7FF7h) is '1'
or the Watchdog Register is reset (7FF7h=0).
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024
Hz would indicate a +20 PPM oscillator frequency
error, requiring a –10(WR001010) to be loaded
into the Calibration Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output frequency.
The IRQ
/FT pin is an open drain output which requires a pull-up resistor for proper operation. A
500-10kΩ resistor is recommended in order to
control the rise time. The FT Bit is cleared on power-down.
For more information on calibration, see the Application Note AN934, “TIMEKEEPER Calibration.”
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the eight-bit Watchdog Register, address 7FF7h. The five bits (BMB4-BMB0) that
store a binary multiplier and the two lower order
bits (RB1-RB0) select the resolution, where
1
/16 second, 01 =1/4second, 10 = 1 second,
00 =
and 11 = 4 seconds. The amount of time-out is
then determined to be the multiplication of the fivebit multiplier value with th e resol ution. (F or e xample: writing 00001110 in the Watc hdog Register =
3x1, or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T 37Y/V sets the Watchdog Flag (WDF) and generates a wat chdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address 7FF0h).
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
Reset will not oc cur unless the add re sse s are sta ble at the flag location for at leas t 15ns while the
device is in the READ Mode as shown in Figure
10., page 18.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit. When set to a '0,' the
watchdog will activate the IRQ
/FT pin when timedout. When WDS is set to a '1,' the watchdog will
output a negative pulse on the RST
tion of t
. The Watchd og Register, the FT Bit,
REC
pin for a dura-
AFE Bit, and ABE Bit will reset to a '0' at the end of
a Watchdog time-out when the WDS bit is set to a
'1.'
The watchdog timer resets when the microprocessor performs a re-write of the Watchdog Register
or an edge transition (low to high / high to l ow) on
the WDI pin occurs. The time-out period then
starts over.
The watchdog timer is disabled by writing a value
of 00000000 to the eight bits in the Watchdog Register. Should the watchdog timer time-out, a value
of 00h needs to be written to t he Watchdog Register in order to clear the IRQ/FT pin.
The watchdog function is automatically disabled
upon power-down and the Watchd og Register is
cleared. If the watchdog function is set to output to
the IR Q
/FT pin and the frequency tes t function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied. The WDI
pin should be connected to V
if not used.
SS
Power-on Reset
The M48T37Y/V continuously monitors V
When V
the RST
power-up for t
valid for all V
falls to the power fail detect trip point,
CC
pulls low (open drain) and remains low on
after VCC passes V
REC
conditions. The RST pin is an
CC
PFD
CC
. RST is
open drain output and an appropriate resistor to
should be chosen to control rise time (see
V
CC
Figure 14., page 23).
.
16/29
Programmable Interrupts
The M48T37Y/V provides two programmable interrupts: an alarm and a watchdog. When an interrupt condition occurs, the M48T37Y/V sets the
appropriate flag bit in the Flag Register 7FF0h.
The interrupt enable bits (AFE and ABE) in 7FF6h
and the Watchdog Steering (WDS) Bit in 7FF7h allow the inter r u p t to activate the IRQ
The Alarm flag and the IRQ
/FT output are cleared
/FT pin.
by a READ to the Flags Register. An interrupt condition reset will not occur unless the addresses are
stable at the flag location for at least 15ns whi le
the device is in the READ Mode as shown in Fig-
ure 8., page 14.
The IRQ
/FT pin is an open drain output and re-
quires a pull-up resistor (10kΩ recom mended) to
. The pin remains in the high impedance state
V
CC
unless an interrupt occurs or the Frequency Te st
Mode is enabled.
Battery Low Fl ag
The M48T37Y/V automatically performs periodic
battery voltage monitoring upon power-up. The
Battery Low Flag (BL), Bit D4 of the Fl ags Register
7FF0h, will be asserted high if the SNAPHAT
battery is found to be less than approximately
2.5V. The BL Flag will re m a in active u nti l c o m p letion of battery replacement and subsequent bat-
M48T37Y, M48T37V
tery low monitoring tests during the next power-up
sequence.
If a battery low is generated during a power-up sequence, this indicates the battery voltage is below
2.5V (approximately), which may be insufficient to
maintain data integrity. Data should be considered
suspect and verified as correct. A fresh battery
should be installed. The SNAPHAT top may be replaced while VCC is applied to the device.
Note: This will cause the clock to lose time during
the interval the battery/crystal is removed.
Note: Battery monitoring is a useful technique only
when performed periodically. The M48T37Y/V
only monitors the battery when a nominal V
applied to the device. Thus applications which require extensive durations in the battery back-up
mode should be powered-up periodically (at least
once every few months) in order for this technique
to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
Initi a l Power - o n Defa ults
®
Upon application of power to the de vice, the following register bits are set to a '0' state: WDS;
BMB0-BMB4 ; RB0 - R B1; AFE; ABE; W; R; and FT
(see Table 7).
CC
is
Table 7. Default Values
Condition W R FT AFE ABE
Initial Power-up
(Battery Attach for SNAPHAT)
Subsequent Power-up / RESET
Power-down
Note: 1. WDS, BMB0-B M B4, RBO, RB 1.
2. St at e of other cont rol bits undef i ned.
3. St at e of other cont rol bits remai ns unchanged.
4. As suming these bi ts set to '1' prior t o power-down .
(4)
(2)
(3)
WATCHDOG
Register
00000 0
00000 0
00011 0
(1)
17/29
M48T37Y, M48T37V
VCC Noise And Negative Going Transients
transients, including those produced by output
I
CC
switching, can produce voltage fluctuations, resulting in spikes on the V
bus. These transients
CC
can be reduced if capacitors are used to store energy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure
10) is recommended in order to provide the need-
ed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on V
below V
by as much as one volt. These negative
SS
that drive it to values
CC
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to connect a schottky diode from V
connected to V
, anode to VSS). Schottky diode
CC
to VSS (cathode
CC
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
Figure 10. Supply Voltage Protection
V
CC
V
CC
0.1µF DEVICE
V
SS
AI02169
18/29
Figure 11. Crystal Accuracy Across Temp eratur e
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
–120
–140
–160
0 10203040506070
∆F
F
Temperature °C
= -0.038 (T - T
ppm
2
C
T0 = 25 °C
)2 ± 10%
0
M48T37Y, M48T37V
80–10–20–30–40
AI00999
Figure 12. Cl ock Ca l ib rat i on
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
19/29
M48T37Y, M48T37V
MAXIMUM RA T ING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
Table 8. Absolute Maximum Ratings
Symbol Parameter Value Unit
not implied. Exposure to Absol ute Max imum Ra ting conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.
T
A
T
STG
(1,2)
T
SLD
Ambient Operating Temperature
Storage Temperature (VCC Off, Oscillator
Off)
Lead Solder Temperature for 10 seconds 260 °C
Grade 1 0 to 70 °C
Grade 6 –40 to 85 °C
SNAPHAT
®
–40 to 85 °C
SOIC –55 to 125 °C
M48T37Y –0.3 to 7 V
V
IO
Input or Output Voltages
M48T37V –0.3 to 4.6 V
M48T37Y –0.3 to 7 V
V
CC
I
O
P
D
Note: 1. For SO package, standard (SnPb) lead finish: Reflow at peak t em perature of 225°C (tota l thermal budg et not to exceed 180°C for
between 90 t o 15 0 s e c o nds).
2. F or S O package , Lead-free (Pb-free) l ead finish: Reflow at peak tempera ture of 260°C (total therm al budget n o t to exceed 245°C
for greater than 30 seconds).
CAUTION: Nega tive undershoot s below –0.3V are not allowed on any pin whil e i n the Battery Ba ck-up mode.
CAUTION: Do NOT wave s older SOI C t o avoid da m ag i ng SNAPHAT s o c kets.
Supply Voltage
M48T37V –0.3 to 4.6 V
Output Current 10 mA
Power Dissipation 1 W
20/29
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Meas ure-
Table 9. Operating and AC Measurement Conditions
Parameter M48T37Y M48T37V Unit
M48T37Y, M48T37V
ment Conditions listed in t he relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Supply Voltage (V
CC
)
4.5 to 5.5 3.0 to 3.6 V
Grade 1 0 to 70 0 to 70 °C
Ambient Operating Temperature (T
Load Capacitance (C
)
L
)
A
Grade 6 –40 to 85 –40 to 85 °C
100 50 pF
Input Rise and Fall Times ≤ 10 ≤ 10 ns
Input Pulse Voltages 0 to 3 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 1.5 V
Note: Output Hi-Z is defined as the p oi nt where data is no longer driven.
Figure 13. AC Testin g Load Cir cuit
DEVICE
UNDER
TEST
645Ω
CL = 100pF
(1)
1.75V
CL includes JIG capacitance
Note: Excluding open-drain output pins
1. ; 50pF for M48T37V .
AI02325
Table 10. Capacitance
Symbol
C
IN
C
IO
Note: 1. Effec tive capacitance measured with powe r supply at 5V. Sam pled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs desele ct ed.
Input Capacitance 10 pF
(3)
Input / Output Capacitance 10 pF
Parameter
(1,2)
Min Max Unit
21/29
M48T37Y, M48T37V
Table 11. DC Characteristics
M48T37Y M48T37V
Symbol Parameter
Test Condition
(1)
MinMaxMinMax
(2)
Input Leakage Curren t
(2)
Output Leakage Current
Supply Current Outputs open 50 33 mA
CC
Supply Current (Standby) TTL
Supply Current (Standby)
CMOS
(3)
Input Low Voltage –0.3 0.8 – 0.3 0.8 V
IL
Input High Voltage 2. 2
IH
I
V
I
LI
LO
I
I
CC1
I
CC2
V
Output Low Voltage
(standard)
V
OL
Output Low Voltage
(open drain)
(3)
V
OH
Note: 1. Vali d fo r Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5. 5V or 3.0 to 3.6V (except wh ere not ed ).
Output High Voltage
2. Outputs desele ct ed.
3. Negati ve spik e s of –1V allo wed for up to 10ns onc e pe r cycle .
0V ≤ V
IN
0V ≤ V
OUT
E
= V
= VCC – 0.2V
E
= 2.1mA
I
OL
= 10mA
I
OL
I
= –1mA
OH
≤ V
≤ V
IH
CC
CC
±1 ±1 µA
±1 ±1 µA
32mA
32mA
V
CC
+ 0.3
2.2
VCC + 0.3
0.4 0.4 V
0.4 0.4 V
2.4 2.4 V
Unit–70 –100
V
22/29
Figure 14. Power Down/Up Mode AC Waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSO
M48T37Y, M48T37V
RST
INPUTS
OUTPUTS
tF
VALID
VALID VALID
tFB
tDR
tRB
DON'T CARE
HIGH-Z
tR
tREC
VALID
AI03078
Table 12. Power Down/Up AC Characteristics
Symbol
(2)
t
F
(3)
t
FB
t
R
t
RB
(4)
t
REC
Note: 1. Vali d fo r Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5. 5V or 3.0 to 3.6V (except wh ere not ed ).
2. V
es V
3. V
4. t
REC
V
(max) to V
PFD
V
(min) to VSS VCC Fall Time
PFD
V
(min) to V
PFD
VSS to V
V
(max) t o V
PFD
(min).
PFD
(min) to VSS fall time of less than tFB may cause corruption of RA M data.
PFD
(min) = 20ms for Industrial Tem perature Range - Grade 6 devi ce.
PFD
(max) to RST High
PFD
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
PFD
Parameter
(min) VCC Fall Time
PFD
(max) VCC Rise Time
PFD
(min) VCC Rise Time
(1)
Min Max Unit
300 µs
10 µs
10 µs
1µs
40 200 ms
Table 13. Power Down/Up Trip Points DC Characteristics
Symbol
Parameter
(1)
M48T37Y 4.2 4.4 4.5 V
V
Power-fail Deselect Voltage
PFD
M48T37V 2.7 2.9 3.0 V
M48T37Y
V
t
DR
Note: All voltages referenced to VSS.
Battery Back-up Switchover Voltage
SO
(3)
Expected Data Retention Time
M48T37V
Grade 1 5 7 YEARS
Grade 6
1. Valid for Ambient Operating T em perature : T
2. Using larger M 4T 32-BR12SH 6 S NAPHAT top (recommended for Industrial Temperature Range - Gra de 6 device).
3. At 25°C, V
CC
= 0V.
= 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5. 5V or 3.0 to 3.6V (except wh ere not ed ).
A
Min Typ Max Unit
V
BAT
V
–100mV
PFD
(2)
10
V
V
YEARS
23/29
M48T37Y, M48T37V
PACKAG E MECHANICAL INFORMAT ION
Figure 15. SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Outli ne
A2
A
C
Be
eB
CP
D
N
E
H
LA1 α
1
SOH-A
Note: Drawing is not to scale.
Table 14. SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Mech. Data
Symb
Typ Min Max Typ Min Max
A 3.05 0.120
mm inches
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.46 0.014 0.018
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e0.81– –0.032– –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N44 44
CP 0.10 0.004
24/29
M48T37Y, M48T37V
Figure 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
eA
D
A1
A
B
eB
A3
L
E
SHTK-A
Note: Drawing is not to scale.
Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Packag e Mech. Data
Symb
Typ Min Max Typ Min Max
mm inches
A2
A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
25/29
M48T37Y, M48T37V
Figure 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
eA
D
A1
A
B
eB
A3
L
E
SHTK-A
Note: Drawing is not to scale.
Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
Symb
Typ Min Max Typ Min Max
mm inches
A2
A 10.54 0.415
A1 8.00 8.51 0.315 .0335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 .0710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
26/29
M48T37Y, M48T37V
PART NUMBERING
Table 17. Ordering Information Scheme
Example: M48T 37Y –70 MH 1 E
Device Type
M48T
Supply Voltage and Write Protect Voltage
37Y = V
37V = V
Speed
–70 = 70ns (37Y)
–10 = 100ns (37V)
= 4.5 to 5.5V; V
CC
= 3.0 to 3.6V; V
CC
= 4.2 to 4.5V
PFD
= 2.7 to 3.0V
PFD
Package
(1)
MH
= SOH44
Temperature Rang e
1 = 0 to 70°C
6 = –40 to 85°C
Shipping Method
blank = Tubes (Not for New Design - Use E)
E = Lead-free Package (ECO PACK
F = Lead-free Package (ECO PACK
®
), Tubes
®
), Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
Note: 1. The SOIC package (SOH44) requires the SNAPHAT® battery package which is ordered separately under the part number “M4TXX-
BR12SH” in pl astic tube or “M4TXX-BR 12SHTR” in Tape & Reel form (see Table 18).
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
Table 18. SNAPHAT Battery Table
Part Number Description Package
M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH
M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH
27/29
M48T37Y, M48T37V
REVISION HISTORY
Table 19. Document Revision History
Date Rev. # Revision Details
December 1999 1.0 First Issue
07-Feb-00 2.0
11-Jul-00 2.1
19-Jun-01 3.0 Reformatted; added temp./voltage info. to tables (Table 10, 11, 3, 4, 12, 13)
06-Aug-01 3.1 Fix text for Setting the Alarm Clock (Figure 8)
15-Jan-02 3.2 Fix footnote numbering (Table 17)
20-May-02 3.3 Modify reflow time and temperature footnote (Table 8)
31-Mar-03 4.0 v2.2 template applied; data retention condition updated (Table 13)
01-Apr-04 5.0 Reformatted; updated with Lead-free package information (Table 8, 17)
From Preliminary Data to Data Sheet; Battery Low Flag paragraph changed; 100ns
speed class identifier changed (Tables 3, 4)
changed (Table 12); watchdog timer paragraph changed
t
FB
28/29
M48T37Y, M48T37V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics a ssumes no responsibility fo r the c onsequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authori zed for use as criti cal component s in life support devices or sys tems without express written approval of STMicroele ct ronics.
The ST logo is a registered trademark of STMi croelectronics.
All other na m es are the property of their respective ow ners.
© 2004 STMi croelectroni cs - All rights reserved
Australi a - B elgium - Braz i l - Canada - China - Czech Republ i c - Finland - France - Germany -
Hong Kong - India - Israel - It al y - Japan - Malays i a - Malta - Moroc co - Singapore -
STMicroelectroni cs GROUP OF COMPANIES
Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
29/29
Loading...