STMicroelectronics M48T35, M48T35Y User Manual

5V, 256 Kbit (32 Kb x8) TIMEKEEPER® SRAM

FEAT URES SUMMARY

■ INTEGRATED, ULT RA LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT AND BATTERY

■ BYTEWIDE™ RAM-LIKE CLOCK ACCESS

■ BCD CODED YEAR, MONTH, DAY, DATE,

HOURS, MINUTES, AND SECONDS

■ FREQUENCY TEST OUTPUT FOR REAL

TIME CLOCK

■ AUTOMATIC POWER-FAIL CHIP

DESELECT AND WRITE PROTECT ION

■ WRITE PROTECT VOLTAGES

= Power-fail Deselect Voltage):

(V

PFD

– M48T35: V

4.5V ≤ V

– M48T35Y: V

4.2V ≤ V

■ SELF-CONTAINED BATTERY AND

CRYSTAL IN THE CAPHAT™ DIP
PACKAGE

■ SOIC PACKAGE PROVIDES DIRECT

CONNECTION FOR A SNAPHAT
HOUSING CONTAINING THE BATTERY
AND CRYSTAL

■ SNAPHAT

®

CRYSTAL) IS REPLACEABLE

■ PIN AND FUNCTION COMPATIBLE WITH

JEDEC STANDARD 32 Kb x 8 SRAMs

= 4.75 to 5.5V

CC

≤ 4.75V

PFD

= 4.5 to 5.5V

CC

≤ 4.5V

PFD

®

HOUSING (BATTERY AND

M48T35

M48T35Y

Figure 1. 28-pin PCDIP, CAPHAT™ Package

28

1

PCDIP28 (PC)
Battery/Crystal

CAPHAT

Figure 2. 28-pi n S O I C Package

SNAPHAT (SH)

Battery/Crystal

28

1

SOH28 (MH)

1/26April 2004

M48T35, M48T35Y

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 28-pin PCDIP, CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. RE A D Mode AC Charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 8. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 9. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reading the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

Figure 10.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11.Clock Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V

Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CC

Figure 12.Supply Voltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 14.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2/26

M48T35, M48T35Y

Table 10.Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11.Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 15.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline . . . . . . . . . . . . . . . . 19

Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data. . . . . . . . . 19

Figure 16.SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline. 20

Table 13. SOH28 – 28-lead Plastic SO, 4-socket battery SNAPHAT, Package Mech. Data . . . . . 20

Figure 17.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 21

Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 21

Figure 18.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 22

Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 22

Figure 19.PMDIP28 – 28-pin Plastic DIP, Hybrid, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 16. PMDIP28 – 28-pin Plastic DIP, Hybrid, Package Mechanical Data . . . . . . . . . . . . . . . . . 23

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 17.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 18.SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 19.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3/26

M48T35, M48T35Y

SUMMARY DESCRIPTIO N

The M48T35/Y TIMEKEEPER® RAM is a 32K b x
8 non-volatile static RAM and real time clock. The
monolithic chip is available in two special packag­es to provide a highly integrated battery backed-up
memory and real time clock solution.

The M48T35/Y is a non-volatile pin and function
equivalent to any JEDEC standard 32Kb x 8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.

The 28-pin, 600mil DIP CAPHAT houses the
M48T35/Y silicon with a quartz crystal and a long
life lithium button cell in a single package.

Figure 3. Logic Diagram Table 1. Signal Names

The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at bot h ends for direct con­nection to a separate SNAPHAT
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser­tion of the SNAPHAT housing after reflow pre­vents potential battery and c rystal dam age due to
the high temperatures required for device surface­mounting. The SNAPHAT housing is keyed to pre­vent reverse insertion. The SOIC and battery/crys­tal packages are shipped separately in plastic anti­static tubes or in Tape & Reel form.

For the 28-lead SOIC, the battery/crystal package
(e.g., SNAPHAT) part number is “M4T28­BR12SH” (see Table 18., page 24).

®

housing con-

A0-A14

W

V

CC

15

M48T35

M48T35Y

E

G

V

SS

8

DQ0-DQ7

AI01620B

A0-A14 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E
G
W
V
V

CC

SS

Chip Enable
Output Enable
WRITE Enable
Supply Voltage
Ground

4/26

M48T35, M48T35Y

Figure 4. DIP C on ne ctions Figure 5. SOI C Co nn e ct io ns

1

A14 V

2

A12

3

A7

4

A6

5

A5
A4

6

A3

7

M48T35

8

A2
A1
A0

DQ0

M48T35Y
9
10
11
12

DQ2

13
14

SS

Figure 6. Block Diagram

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI01621B

CC

W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

A14 V
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

1
2
3
4
5
6
7
8
9
10
11

M48T35Y

12

DQ2

SS

13
14

AI01622B

28
27
26
25
24
23
22
21
20
19
18
17
16
15

CC

W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

32,768 Hz
CRYSTAL

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

V

CC

POWER

V

PFD

8 x 8 BiPORT

SRAM ARRAY

32,760 x 8

SRAM ARRAY

V

SS

A0-A14

DQ0-DQ7

E

W

G

AI01623

5/26

M48T35, M48T35Y

OPERATION MODES

As Figure 6., page 5 shows, the static memory ar­ray and the quartz controlled clock oscillator of the
M48T35/Y are integr ated on one silicon c hip. T he
two circuits are interconnected at the up per eight
memory locations to provide user accessible
BYTEWIDE clock information in the bytes with ad­dresses 7FF8h-7FFFh.

The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for­mat. Corrections for 28, 29 (leap yea r - valid until

2100), 30, and 31 day months are made automat­ically. Byte 7FF8h is the clock control register. This
byte controls user access t o the clock inform ation
and also stores the clock calibration setting.

The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory

Table 2. Operating Modes

Mode

Deselect
WRITE
READ
READ

Deselect
Deselect

Note: X = VIH or VIL; VSO = Batte ry Back-up Switchover Vo l tage.

1. See Table 11., page 18 for details.

V

V

4.75 to 5.5V

4.5 to 5.5V

to V

SO

PFD

≤ V

or

SO

CC

(min)

(1)

(1)

E G W DQ0-DQ7 Power

V

IH

V

IL

V

IL

V

IL

X X X High Z C MOS Standby
X X X High Z Battery Back-up Mode

cells. The M48T35/Y includes a clock control cir­cuit which updates the clock bytes with current in­formation once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.

The M48T35/Y also has its own Pow er-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi­tion. When V

is out of tolerance, the circuit write

CC

protects the SRAM, providing a high degree of
data security in the midst of unpredictable system
operation brought on by low V

. As VCC falls be-

CC

low the Battery Back-up Switchover Voltage

), the control circuitry connects the battery

(V

SO

which maintains data and clock operation until val­id power returns.

X X High Z Standby
X

V

IL

V

IH

V

IL

V

IH

V

IH

D

IN

D

OUT

High Z Active

Active
Active

6/26

READ Mode

The M48T35/Y is in the READ Mode whenever W
(WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 15 Ad­dress Inputs defines which one of the 32,768 bytes
of data is to be acces sed . Vali d data w ill be av ail­able at the Data I/O pi ns within Address Access
time (t
stable, providing that the E

) after the last address input signal is

AVQV

and G access times

are also satisfied.
If the E

and G access times are not met, valid data

will be avai la ble after the latter of the Chi p Ena ble

Figure 7. READ Mode AC Waveforms

M48T35, M48T35Y

Access time (t

).

(t

GLQV

The state of the eight t hree-state Da ta I/O si gnals
is controlled by E
ed before t

AVQV

indeterminate state until t
If the Address Inputs are changed while E

remain active, output data will remain valid for Out­put Data Hold time (t
nate until the next Address Access.

tAVAV

) or Output Enable Access time

ELQV

and G. If the outputs are activat-

, the data lines will be driven to an

.

AVQV

) but will go indetermi-

AXQX

and G

A0-A14

tAVQV tAXQX

tELQV

E

tELQX

tGLQV

G

tGLQX

DQ0-DQ7

Note: W RITE Enable (W) = High.

VALID

tEHQZ

tGHQZ

VALID

AI00925

Table 3. READ Mode AC Characteristics

Symbol

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXQX

Note: 1. Valid for Ambient Op erating Temp erature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4. 5 to 5.5V (except where noted) .

2. C

READ Cycle Time 70 ns
Address Valid to Output Valid 70 ns
Chip Enable Low to Output Valid 70 ns
Output Enable Low to Output Valid 35 ns

(2)

Chip Enable Low to Output Transition 5 ns

(2)

Output Enable Low to Output Transition 5 ns

(2)

Chip Enable High to Output Hi-Z 25 ns

(2)

Output Enable High to Output Hi-Z 25 ns
Address Transition to Output Transition 10 ns

= 5pF.

L

Parameter

(1)

M48T35/Y

Unit

Min Max

7/26

M48T35, M48T35Y

WRITE Mode

The M48T35/Y is in the WRITE Mode whenever W
and E are low. The start of a WRITE is referenced
from the latter occurri ng fallin g edge of W

or E. A

WRITE is terminated by the earlier rising edge of

or E. The addresses must be held valid through-

W
out the cycle. E
mum of t

or W must return high for a mini-

from Chip Enable or t

EHAX

WHAX

from

WRITE Enable prior to the initiation of another

Figure 8. WRITE Enable Controlled, WRITE AC Waveform

READ or WRITE Cycle. Data-in must be valid t

prior to the end of WRITE and remain valid for

VWH

t

WHDX

WRITE Cycles to avoid bu s contention; although,
if the output bus has been activated by a low on E
and G, a low o n W will d isable the out puts t
after W falls.

tAVAV

D-

afterward. G should be kept high during

WLQZ

A0-A14

tAVEL

E

tAVWL

W

tWLQZ

DQ0-DQ7

VALID

tAVWH

tWLWH

Figure 9. Chip Enable Controlled, WRITE AC Waveforms

tAVAV

A0-A14

tAVEL

VALID

tAVEH

tELEH

tDVWH

tWHAX

tWHQX

tWHDX

DATA INPUT

AI00926

tEHAX

8/26

E

W

DQ0-DQ7

tAVWL

DATA INPUT

tDVEH

tEHDX

AI00927