5.0 or 3.3V, 1 Mbit (128 Kb x 8) TIMEKEEPER® SRAM
FEAT URES SUMMARY
■ INTEGRATED, ULT RA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, BATTERY, AND
CRYSTAL
■ BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, AND SECONDS
■ AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECT ION
■ WRITE PROTECT VOLTAGES
= Power-fail Deselect Voltage):
(V
PFD
– M48T128Y: V
4.1V ≤ V
PFD
– M48T128V*: V
2.7V ≤ V
■ CONVENTIONAL SRAM OPERATION;
PFD
UNLIMITED WRITE CYCLES
■ SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
■ 10 YEARS OF DATA RETENTION AND
CLOCK OPERATION IN THE ABSENCE O F
POWER
■ SELF-CONTAINED BATTERY AND
CRYSTAL IN THE DIP PACKAGE
■ PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128K x 8 SRAMs
= 4.5 to 5.5V
CC
≤ 4.5V
= 3.0 to 3.6V
CC
≤ 3.0V
M48T128Y
M48T128V*
Figure 1. 32-pi n PMDIP Mo du le
32
1
PMDIP32 (PM)
Module
* Contact local ST sales office for availability of 3.3V version.
1/22February 2005
M48T128Y, M48T128V*
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 32-pin PMDIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 3. RE A D Mode AC Charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reading the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
V
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CC
Figure 10.Supply Voltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10.Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11.Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/22
M48T128Y, M48T128V*
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.PMDIP32 – 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data . . . . . . . . . . . . . . . . 19
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
M48T128Y, M48T128V*
SUMMARY DESCRIPTION
The M48T128Y/V TIMEKEEPER® RAM is a
128Kb x 8 non-vol atile static RAM and real time
clock. The special DIP package provides a fully integrated battery back-up memory and real time
clock solution. The M48T 128Y /V d irectly replaces
industry standard 128Kb x 8 SRAM.
Figure 2. Logic Diagram Table 1. Signal Names
It also provides the non-vol atility of Flash without
any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 32-pin, 600mil DIP Hybrid houses a
controller chip, SRAM, quartz crystal, and a l ong
life lithium button cell in a single package.
V
CC
17
A0-A16 DQ0-DQ7
W
E
G
M48T128Y
M48T128V
V
SS
8
Figure 3. DIP C on ne ctions
1
NC V
2
A16
A14
3
A12
4
5
A7
6
A6
7
A5
A4
A3
A2
A1
A0
DQ0
DQ2
SS
M48T128Y
8
M48T128V
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AI02245
CC
A15
NC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
AI02244
A0-A16 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E
G
W
V
CC
V
SS
NC Not Connected Internally
Chip Enable
Output Enable
WRITE Enable
Supply Voltage
Ground
4/22
Figure 4. Block Diagram
M48T128Y, M48T128V*
32,768 Hz
CRYSTAL
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
CC
POWER
V
PFD
8 x 8
TIMEKEEPER
REGISTERS
131,064 x 8
SRAM ARRAY
V
SS
A0-A16
DQ0-DQ7
E
W
G
AI01804
5/22
M48T128Y, M48T128V*
OPERATION MODES
Figure 4., page 5 illus tra tes the s tatic mem ory ar-
ray and the quartz controlled clock o scillator. The
clock locations contain the year, month, date, day,
hour, minute, and sec ond in 24 hour BCD form at.
Corrections for 28, 29 (leap year - valid until 2100),
30, and 31 day months are made a utomatically.
Byte 1FFF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting. The seven
clock bytes (1FFFFh - 1F FF8h) are not the actual
clock counters, they are memory locations consisting of BiPORT™ READ/WRITE memory cells
within the static RAM array. T he M48T128Y /V includes a clock control circuit which updates the
clock bytes with current information once per sec-
Table 2. Operating Modes
4.5 to 5.5V
3.0 to 3.6V
to V
SO
≤ V
V
or
PFD
CC
SO
(min)
(1)
(1)
E G W DQ0-DQ7 Power
V
IH
V
IL
V
IL
V
IL
X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode
X X High Z Standby
X
V
V
Mode
Deselect
WRITE
READ
READ
Deselect
Deselect
Note: X = VIH or VIL; VSO = Battery B ack-up Switc hover Voltage.
1. See Table 11., page 18 for details.
V
ond. The information can be accessed by the user
in the same manner as any other location in the
static memory array. The M48T128Y/V also has its
own Power-Fail Detect circuit. This control circuitry
constantly monitors the supply voltage for an out
of tolerance condition. When V
is out of toler-
CC
ance, th e cir cuit wri te pro tect s the TIMEK EEPER
Register data and external SRAM, providin g data
security in the midst of unpredictable system operation. As V
Switchover Voltage (V
falls below the Battery Back-up
CC
), the control circuitry au-
SO
tomatically switches to the battery, maintaining
data and clock operation until valid power is restored.
V
IL
IL
IH
V
IH
V
IH
D
IN
D
OUT
High Z Active
Active
Active
®
6/22
READ Mode
The M48T128Y/V is in the READ Mode whenever
(WRITE Enable) is high and E (Chip Enable) is
W
low. The unique address specified by the 17 Address Inputs defines which one of the 131,072
bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within t
address input signal is stable, providing the E
access times are also satisfied. If the E and G
G
(Address Access Time) after the last
AVQV
and
access t imes are n ot me t, v alid d ata w ill be av ail-
Figure 5. READ Mode AC Waveforms
M48T128Y, M48T128V*
able after the latter of the Chip Enable Access
Times (t
). The state of the eight three-state Data I/O
(t
GLQV
signals is controlled by E
activated before t
to an indeterminate state until t
dress Inputs are changed while E
active, output data will remain valid for t
put Data Hold Time) but will go indeterminate until
the next Address Acce ss.
tAVAV
) or Output Enable Access Time
ELQV
and G. If the outputs are
, the data lines will be driven
AVQV
AVQV
and G remain
. If the Ad-
(Out-
AXQX
A0-A16
tAVQV tAXQX
tELQV
E
tELQX
G
tGLQX
DQ0-DQ7
Note: WE = High.
tGLQV
VALID
tEHQZ
tGHQZ
DATA OUT
AI01197
Table 3. READ Mode AC Characteristics
M48T128Y M48T128V
Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. Valid for Ambient Operating Tem perature : TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (exc ept where noted ).
2. C
READ Cycle Time 70 85 ns
Address Valid to Output Valid 70 85 ns
Chip Enable Low to Output Valid 70 85 ns
Output Enable Low to Output Valid 40 55 ns
(2)
Chip Enable Low to Output Transition 5 5 ns
(2)
Output Enable Low to Output Transition 5 5 ns
(2)
Chip Enable High to Output Hi-Z 25 30 ns
(2)
Output Enable High to Output Hi-Z 25 30 ns
Address Transition to Output Transition 10 5 ns
= 5pF.
L
Parameter
(1)
Min Max Min Max
Unit–70 –85
7/22
M48T128Y, M48T128V*
WRITE Mode
The M48T128Y/V is in the WRITE Mode whenever
(WRITE Enable) and E (Chip Ena ble) are low
W
state after the address inputs are stable.
The start of a WRITE is referenced from the latter
occurring falling edge of W
nated by the earlier rising edge of W
or E. A WRITE is termi-
or E. The addresses must be held valid throughout the cycle. E
or W must return high for a minimum of t
EHAX
from
Figure 6. WRITE Enable Controlled, WRITE AC Waveform
Chip Enable or t
the initiation of another READ or WRITE cycle.
Data-in must be valid t
WRITE and remain valid for t
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E
disable the outputs t
tAVAV
from WRITE Enable prior to
WHAX
prior to the end of
DVWH
afterward. G
WHDX
and G a low on W will
after W falls.
WLQZ
A0-A16
tAVEL
E
tAVWL
W
tWLQZ
DQ0-DQ7
VALID
tAVWH
tWLWH
Figure 7. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A16
tAVEL
VALID
tAVEH
tELEH
tDVWH
tWHAX
tWHQX
tWHDX
DATA INPUT
AI02382
tEHAX
8/22
E
W
DQ0-DQ7
tAVWL
DATA INPUT
tDVEH
tEHDX
AI02383
M48T128Y, M48T128V*
Table 4. WRITE Mode AC Characteristics
M48T128Y M48T128V
Symbol
t
AVAV
t
AVWL
t
AVEL
t
WLWH
t
ELEH
t
WHAX
t
EHAX
t
DVWH
t
DVEH
t
WHDX
t
EHDX
(2,3)
t
WLQZ
t
AVWH
t
AVEH
t
WHQX
Note: 1. Valid for Ambient Operating Tem perature : TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (exc ept where noted ).
2. C
3. If E
WRITE Cycle Time 70 85 ns
Address Valid to WRITE Enable Low 0 0 ns
Address Valid to Chip Enable Low 0 0 ns
WRITE Enable Pulse Width 50 60 ns
Chip Enable Low to Chip Enable 1 High 55 65 ns
WRITE Enable High to Address Transition 5 5 ns
Chip Enable High to Address Transition 10 15 ns
Input Valid to WRITE Enable High 30 35 ns
Input Valid to Chip Enable High 30 35 ns
WRITE Enable High to Input Transition 5 5 ns
Chip Enable High to Input Transition 10 15 ns
WRITE Enable Low to Output Hi-Z 25 30 ns
Address Valid to WRITE Enable High 60 70 ns
Address Valid to Chip Enable High 60 70 ns
(2,3)
WRITE Enable High to Output Transition 5 5 ns
= 5pF.
L
goes low simultaneously with W going low, the outputs remai n in the high impedance stat e.
Parameter
(1)
Min Max Min Max
Unit–70 –85
9/22
M48T128Y, M48T128V*
Data Retention Mode
With valid V
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V
(min) window. All outputs become high impedance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently a ddressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
assured the memory will be i n a write protected
state, provided the V
The M48T128Y/V may respond t o transient noise
applied, the M48T128Y/V operates
CC
falls within the V
CC
PFD
fall time is not less than tF.
CC
(min), the user can be
PFD
(max), V
PFD
spikes on V
during the time the device is sampling V
that reach into the deselect window
CC
CC
. Therefore, decoupling of the power supply lines is recommended.
When V
drops below VSO, the control circuit
CC
switches power to the internal b attery, preserving
data and powering the clock. The internal energy
source will maintain data in the M48T128Y/ V for
an accumulated period of at least 10 years at room
temperature. As system power rises abo ve V
SO
the battery is disconnected, and the power supply
is switched to external V
after VCC reaches V
t
REC
. Deselect continues for
CC
(max).
PFD
,
10/22
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER
be halted before clock data is read to prevent
reading data in transition. The BiPORT ™ TIMEKEEPER cel ls in th e R AM a r ra y are onl y d a ta registers and not the actual clock counters, so
updating the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (1FFF8h). As
long as a '1' remains in that position , updating is
halted. After a h alt is issu ed, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was issued. All of the TI MEKEEPER regist ers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after th e bi t i s reset to a ' 0 .'
Setting the Clock
Bit D7 of the Control Register (1FFF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
®
registers should
M48T128Y, M48T128V*
READ Bit, halts updates to the TIMEKEEPER registers. The user can then load t hem with the correct day, date, and time data in 24 hour BCD
format (see Table 5., page 11). Resetting the
WRITE Bit to a '0' then transfers the values of all
time registers 1FFFFh-1FFF9h to the actual TIMEKEEPER counters and all ows normal operation to
resume. After the WRITE Bit is reset, the next
clock update will occur one second later.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within 1FFF9h. Setting it to
a '1' stops the oscillator. The M48T128Y/V is
shipped from STMicroelectronics with the STOP
Bit set to a '1.' When reset to a '0,' the M48T128Y/
V oscillator starts after one second.
Table 5. Register Map
Address
Data
D7 D6 D5 D4 D3 D2 D1 D0
1FFFFh 10 Years Year Year 00-99
1FFFEh 0 0 0 10 M Month Month 01-12
1FFFDh 0 0 10 Date Date Date 01-31
1FFFCh 0 FT 0 0 0 Day Day 01-07
1FFFBh 0 0 10 Hours Hours Hours 00-23
1FFFAh 0 10 Minutes Minutes Minutes 00-59
1FFF9h ST 10 Seconds Seconds Seconds 00-59
1FFF8h W R S Calibration Control
Keys : S = SI G N Bit
R = READ Bit
W = WRITE B i t
ST = STOP Bit
0 = Must be set to '0'
Z = '0' and are Read only
Y = '1' or '0'
Function/Range
BCD Format
11/22
M48T128Y, M48T128V*
Calibrating the C lock
The M48T128Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25°C and
tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53
minutes per month. When the Calibration circuit is
properly employed, accuracy improves to better
than +1/–2 ppm at 25°C. The oscillation rate of
crystals changes with temperature (see Figure
8., page 13). The M48T128Y/V design employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 128 stage, as shown in Fig-
ure 9., page 13.
The number of times pulses are blanked (subtracted, negative calibration) or split (added, pos itive
calibration) depends upon the value loaded into
the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Cali bration
bits occupy the five lower order bits (D4-D0) in the
Control Register 1FFF8h. These bits can be set to
represent any value be tween 0 and 31 in binary
form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62
minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened
by 256 oscillator cycles. If a binary '1' is loaded into
the register, only the first 2 minutes in the 64
minute cycle will be modified; if a binary 6 is load-
ed, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding
512 or subtracting 256 oscillator cycles for every
125, 829, 120 actual oscillator cycles, that is
+4.068 or –2.034 ppm o f adjustment per ca libration step in the calibrat ion registe r. Assum ing that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte wo uld
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
One method is available for ascertaining how
much calibration a given M48T128Y/V may require. This involves setting the clock, letting it run
for a month and comparing it to a known accurate
reference and recording deviation over a fixed period of time.
Calibration values, including the number of seconds lost or gained in a given period, can be found
in the STMicroelectronics Application Note,
“TIMEKEEPER CALIBRATION.”
This allows the designer to give the end user the
ability to calibrate the clock as the environment requires, even if the final product is packaged in a
non-user serviceable enclosure. The designer
could provide a simple utility that accesses the
Calibration byte. For e xample, a devia tion of 21
seconds slow over a period of 30 days would indicate a –8 ppm oscillator frequency error, requiring
a +2(WR100010) to be loaded into the Calibration
Byte for correction.
12/22
Figure 8. Crystal Accuracy Across Temperature
ppm
20
0
-20
-40
M48T128Y, M48T128V*
-60
-80
-100
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
Figure 9. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
∆F
= -0.038 (T - T
F
ppm
T0 = 25 °C
)2 ± 10%
0
2
C
°C
AI02124
AI00594B
13/22
M48T128Y, M48T128V*
VCC Noise And Negative Going Transients
transients, including those produced by output
I
CC
switching, can produce voltage fluctuations, resulting in spikes on the V
bus. These transients
CC
can be reduced if capacitors are used to store energy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure
10) is recommended in order to provide the need-
ed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on V
below V
by as much as one volt. These negative
SS
that drive it to values
CC
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to connect a schottky diode from V
connected to V
, anode to VSS). Schottky diode
CC
to VSS (cathode
CC
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
Figure 10. Supply Voltage Protection
V
CC
V
CC
0.1µF DEVICE
V
SS
AI02169
14/22
M48T128Y, M48T128V*
MAXIMUM RA T ING
Stressing the device above the rating l isted in t he
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
Table 6. Absolute Maximum Ratings
Symbol Parameter Value Unit
not implied. Exposure to Absol ute Max imum Ra ting conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.
T
A
T
STG
(1)
T
SLD
V
IO
V
CC
I
O
P
D
Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
No preheat above 150°C , or di rect exposure to IR reflow (or IR preheat) al l owed, to avoid damaging the Lithium battery.
CAUTION: Negative undershoo ts bel ow –0.3V are not al l owed on any pin whi l e i n th e Battery Back-up mode.
Ambient Operating Temperature 0 to 70 °C
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages –0.3 to 7 V
M48T128Y –0.3 to 7 V
Supply Voltage
M48T128V –0.3 to 4.6
Output Current 20 mA
Power Dissipation 1 W
–40 to 85 °C
15/22
M48T128Y, M48T128V*
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Meas ure-
Table 7. Operating and AC Measurement Conditions
Parameter M48T128Y M48T128V Unit
ment Conditions listed in t he relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Supply Voltage (V
Ambient Operating Temperature (T
Load Capacitance (C
CC
)
)
A
)
L
4.5 to 5.5 3.0 to 3.6 V
0 to 70 0 to 70 °C
100 50 pF
Input Rise and Fall Times ≤ 5 ≤ 5ns
Input Pulse Voltages 0 to 3 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 1.5 V
Note: Output Hi-Z is defined as the poi nt where data i s no longer dri ven.
Figure 11. AC Testin g Load Cir cuit
DEVICE
UNDER
TEST
650Ω
CL = 100pF
or 50pF
(1)
1.75V
CL includes JIG capacitance
Note: 5 0pF for M48T12 8V .
AI03630
Table 8. Capacitance
Symbol
C
IN
C
IO
Note: 1. Effec tive capacita nce measured with powe r supply at 5V. S am pled only, not 100% test ed.
2. At 25°C, f = 1MHz.
3. Out puts deselect ed.
Input Capacitance 20 pF
(3)
Input / Output Capacitance 20 pF
Parameter
16/22
(1,2)
Min Max Unit
M48T128Y, M48T128V*
Table 9. DC Characteristics
M48T128Y M48T128V
IN
≤ V
≤ V
IH
CC
CC
(1)
Min Max Min Max
±2 ±2 µA
±2 ±2 µA
84mA
43mA
V
CC
+ 0.3
2.2
VCC + 0.3
0.4 0.4 V
2.4 2.2 V
Symbol Parameter
I
I
LO
I
CC
I
CC1
I
CC2
V
V
V
V
OH
Note: 1. Valid for Ambient Operating Tem perature : TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (exc ept where noted ).
2. Out puts deselect ed.
Input Leakage Current
LI
(2)
Output Leakage Current
Supply Current Outputs open 95 50 mA
Supply Current (Standby)
TTL
Supply Current (Standby)
CMOS
Input Low Voltage –0.3 0.8 –0.3 0.4 V
IL
Input High Voltage 2.2
IH
Output Low Voltage
OL
Output High Voltage
Test Condition
0V ≤ V
0V ≤ V
OUT
= V
E
= VCC – 0.2V
E
I
= 2.1mA
OL
I
= –1mA
OH
Unit–70 –85
V
17/22
M48T128Y, M48T128V*
Figure 12. Power Down/Up Mode AC Waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSS
tDR
tRB
DON'T CARE
HIGH-Z
tREC
RECOGNIZEDRECOGNIZED
INPUTS
OUTPUTS
tF
tFB
VALID VALID
Table 10. Power Down/Up AC Characteristics
Symbol
(2)
t
F
(3)
t
FB
t
R
t
RB
t
REC
Note: 1. Valid for Ambient Operating Tem perature : TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (exc ept where noted ).
2. V
es V
3. V
V
(max) to V
PFD
V
(min) to VSS VCC Fall Time
PFD
V
(min) to V
PFD
VSS to V
V
(max) to V
PFD
(min).
PFD
(min) to VSS fall time of less than tFB may cause corruption of RAM data.
PFD
PFD
(max) to Inputs Recognized
PFD
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
PFD
Parameter
(min) VCC Fall Time
PFD
(max) VCC Rise Time
PFD
(min) VCC Rise Time
(1)
Min Max Unit
300 µs
10 µs
0µs
1µs
40 200 ms
AI03612
Table 11. Power Down/Up Trip Points DC Characteristics
Symbol
V
PFD
V
SO
t
DR
Note: 1. All voltages referenced to VSS.
2. Va l i d for Ambient Op erating Temp erature: T
3. At 25°C; V
Power-fail Deselect Voltage
Battery Back-up Switchover Voltage
(3)
Expected Data Retention Time 10 YEARS
= 0V.
CC
18/22
Parameter
(1,2)
M48T128Y 4.1 4.35 4.5 V
M48T128V 2.7 2.9 3.0 V
M48T128Y 3.0 V
M48T128V
= 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (exc ept where noted ).
A
Min Typ Max Unit
V
PFD
–100mV
V
PACKAG E MECHANICAL INFORMAT ION
Figure 13. PMDIP32 – 32-pin Plastic Module DIP, Package Outline
M48T128Y, M48T128V*
A1AL
S
B
e1
eA
e3
D
N
E
1
Note: D rawing is not to scale.
PMDIP
Table 12. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 9.27 9.52 0.365 0.375
A1 0.38 – 0.015 –
B 0.43 0.59 0.017 0.023
C 0.20 0.33 0.008 0.013
mm inches
C
D 42.42 43.18 1.670 1.700
E 18.03 18.80 0.710 0.740
e1 2.29 2.79 0.090 0.110
e3 34.29 41.91 1.350 1.650
eA 14.99 16.00 0.590 0.630
L 3.05 3.81 0.120 0.150
S 1.91 2.79 0.075 0.110
N32 32
19/22
M48T128Y, M48T128V*
PART NUMBERING
Table 13. Ordering Information Scheme
Example: M48T 128Y –70 PM 1 TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
128Y = V
128V
Speed
–70 = 70ns (128Y)
–85 = 85ns (128V)
= 4.5 to 5.5V; V
CC
(1)
= VCC = 3.0 to 3.6V; V
= 4.1 to 4.5V
PFD
= 2.7 to 3.0V
PFD
Package
PM = PMDIP32
Temperature Range
1 = 0 to 70°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. Contact local ST sales office for availability of 3.3V version.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
20/22
M48T128Y, M48T128V*
REVISION HISTORY
Table 14. Document Revision History
Date Version Revision Details
June 1998 1.0 First Issue
01/31/00 1.1 Calibrating The Clock Paragraph changed
03/30/00 1.2 Storage Temperature changed (Table 6)
07/20/01 2.0 Reformatted; temperature information added to tables (Table 8, 9, 3, 4, 10, 11)
09/21/01 2.1 Corrected speed grade in ordering information
05/23/02 2.2 Add countries to disclaimer; add marketing status
08/07/02 2.3 Refine marketing status text
28-Mar-03 3.0 v2.2 template applied; test condition updated (Table 11)
06-Aug-04 4.0 Reformatted; updated Register Map (Table 5)
22-Feb-05 5.0 IR reflow update (Table 6)
21/22
M48T128Y, M48T128V*
Information furnished is believed to be accurate and reliable. However, STMicroelectronics a ssumes no responsibility fo r the c onsequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authori zed for use as crit i cal components in life support devices or systems w i th out express written approval of STMicroelectro nics.
The ST logo is a registered tra demark of STMi croelectronics.
All other nam es are the property of their respective owners
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22/22
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