5.0V, 16 Kbit (2Kb x 8) TIMEKEEPER® SRAM
FEATURES SUMMARY
■ INTEGRATED, ULTRA LOW POWER SRAM,
REAL TIME CLOCK, and POWER-FAIL
CONTROL CIRCUIT
■ BYTEWIDE™ RAM-LIKE CLOCK ACCESS
■ BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, and SECONDS
■ TYPICAL CLOCK ACCURACY OF ±1 MINUTE
A MONTH, AT 25°C
■ SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■ WRITE PROTECT VOLTAGES
(V
= Power-fail Deselect Voltage):
PFD
– M48T02: V
4.5V ≤ V
– M48T12: V
4.2V ≤ V
■ SELF-CONTAI N ED BATTER Y and CRY STAL
IN THE CAPHAT™ DIP PACKAGE
■ PIN and FUNCTION COMPATIBLE WITH
JEDEC STANDARD 2K x 8 SRAMs
= 4.75 to 5.5 V
CC
≤ 4.75V
PFD
= 4.5 to 5.5V
CC
≤ 4.5V
PFD
M48T02
M48T12
Figure 1. 24-pin PCDIP, CAPHAT™ Package
24
1
PCDIP24 (PC)
Battery/Crystal
CAPHAT
1/19July 2001
M48T02, M48T12
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DIP Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating and AC Measurement Condit ions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
AC Testing Load Circuit (Figure 5.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating Modes (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode AC Waveforms (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE Enable Controlled, WRITE AC Waveform (Figure 7.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable Controlled, WRITE AC Waveforms (Figure 8.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Checking the BOK Flag Status (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Down/Up Mode AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Down/Up AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Down/Up Trip Points DC Characteristics (Table 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Register Map (Table 11.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Crystal Accuracy Across Temperature (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock Calibration (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Supply Decoupling and Undershoot Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Supply Voltage Protection (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
M48T02, M48T12
SUMMARY DESCRIPTION
®
The M48T 02/ 12 TI MEK EEPE R
RAM is a 2Kb x 8
non-volatile static RAM and real time c lock which
is pin and functional compatible with the DS1642.
A special 24-pin, 600mil DIP CAPHAT™ package
houses the M48T02/12 silicon with a quartz crystal
and a long life lithium but ton cell to form a hi ghly
integrated battery backed-up memory and real
time clock solution.
The M48T02/12 button cell has sufficient capacity
and storage life to maintain data and clock func-
tionality for an accumulated time period of at least
10 years in the absence of power over the operating temperature range.
The M48T02/12 i s a non-volatile pin and function
equivalent to any JEDEC standard 2Kb x 8 SRAM.
It also easily fits into many ROM , EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
Figure 2. Logic Diagram Table 1. Signal Names
A0-A10 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E
G
W
V
V
CC
SS
Chip Enable
Output Enable
WRITE Enable
Supply Voltage
Ground
A0-A10
W
V
CC
11
M48T02
M48T12
E
G
8
DQ0-DQ7
V
SS
Figure 3. DIP C on ne ctions
AI01027
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ2
SS
1
2
3
4
5
6
7
8
9
10
11
12
M48T02
M48T12
24
23
22
21
20
19
18
17
16
15
14
13
AI01028
V
CC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
3/19
M48T02, M48T12
Figure 4. Block Diagram
OSCILLATOR AND
CLOCK CHAIN
32,768 Hz
CRYSTAL
POWER
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
CC
MAXIMUM RATIN G
Stressing the device ab ove the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the dev ice at
these or any other conditions above those indicated in the Operating sections of this specification is
8 x 8 BiPORT
SRAM ARRAY
A0-A10
DQ0-DQ7
E
W
G
AI01329
V
PFD
BOK
2040 x 8
SRAM ARRAY
V
SS
not implied. Exposure to Absol ute Maxim um Ra ting conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
STG
(2)
T
SLD
V
IO
V
CC
I
O
P
D
Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative unders hoots below –0.3V are not allowe d on any pin while in the Batter y Back-up mode.
4/19
Ambient Operating Temperature 0 to 70 °C
Storage Temperature (VCC Off, Oscillator Off)
–40 to 85 °C
Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages –0.3 to 7 V
Supply Voltage –0.3 to 7 V
Output Current 20 mA
Power Dissipation 1 W
M48T02, M48T12
DC AND AC PARAMETERS
This section summarizes the operat ing and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the M easure-
Table 3. Operating and AC Measurement Conditions
Parameter M48T02 M48T12 Un it
Supply Voltage (V
Ambient Operating Temperature (T
Load Capacitance (C
CC
)
)
A
)
L
Input Rise and Fall Times
Input Pulse Voltages 0 to 3 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 1.5 V
Note: Output Hi -Z is define d as the point wh ere data is no l onger driven.
Figure 5. AC Testing Load Circuit
5V
ment Conditions listed in the rel evant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
4.75 to 5.5 4.5 to 5.5 V
0 to 70 0 to 70 °C
100 100 pF
5
≤
5ns
≤
1.8kΩ
DEVICE
UNDER
TEST
1kΩ
CL includes JIG capacitance
OUT
CL = 100pF
AI01019
Table 4. Capacitance
Symbol
C
IN
C
IO
Note: 1. Effec tive capacit ance measured with power supply at 5V. Sampl ed only, not 10 0% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
Input Capacitance 10 pF
(3)
Input / Output Capacitance 10 pF
Parameter
(1,2)
Min Max Unit
5/19
M48T02, M48T12
Table 5. DC Characteristics
Symbol Parameter
Test Condition
(1)
Min Max Unit
I
LI
I
LO
I
CC
I
CC1
I
CC2
V
IL
V
V
OL
V
OH
Note: 1. Vali d for Ambient Operating Tem perature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2. Outputs deselected.
3. Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0.'
4. Negati ve spike s of –1V allowe d f or up to 10ns once per Cycl e.
Input Leakage Current
(2)
Output Leakage Current
Supply Current Outputs open 80 mA
(3)
Supply Current (Standby) TTL
(3)
Supply Current (Standby) CMOS
(4)
Input Low Voltage –0.3 0.8 V
Input High Voltage 2.2
IH
Output Low Voltage
Output High Voltage
0V ≤ V
0V ≤ V
E
≤ V
IN
CC
≤ V
OUT
E
= V
IH
= VCC – 0.2V
I
= 2.1mA
OL
I
= –1mA
OH
CC
±1 µA
±1 µA
3mA
3mA
V
+ 0.3
CC
0.4 V
2.4 V
OPERATION MODES
As Figure 4, page 4 s hows, the static memory array and the quartz controlled clock oscillator of the
M48T02/12 are integrated on one silicon chip. The
two circuits are interconnected at the up per eight
memory locations to provide user accessible
BYTEWIDE™ clock information in the by tes with
addresses 7F8h-7FFh. The clock locations contain the year, month, date, day, hour, minute, and
second in 24 hour BCD format. Corrections for 28,
29 (leap year - valid until 2100), 30, and 31 day
months are made automatically.
Byte 7F8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locat ions
consisting of BiPORT™ READ/WRITE memory
cells. The M48T02/12 includes a clock cont rol circuit which updates the clock bytes with current information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T02/12 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condition. When V
is out of tolerance, the circuit write
CC
protects the SRAM, providing a high degree of
data security in the midst of unpredictable system
operation brought on by low V
CC
. As V
low approximately 3V, the control circuitry connects the battery which maintains data and clock
operation until valid power returns.
CC
V
falls be-
Table 6. Operating Modes
Mode
Deselect
WRITE
READ
READ
Deselect
V
Deselect
Note: X = VIH or VIL; VSO = Battery Back-up Swit chover Voltage.
1. See Table 10, pag e 11 for details.
6/19
V
CC
4.75 to 5.5V
or
4.5 to 5.5V
to V
SO
PFD
V
≤
SO
(min)
(1)
(1)
E G W DQ0-DQ7 Power
V
IH
V
IL
V
IL
V
IL
X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode
X X High Z Standby
X
V
IL
V
IH
V
IL
V
IH
V
IH
D
IN
D
OUT
Active
Active
High Z Active
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