STMicroelectronics M41T56 Technical data
512 bit (64 bit x8) Serial Access TIMEKEEPER® SRAM
FEATURES SUMMARY
■ 5V ±10% SUPPLY VOLTAGE
■ COUNTERS FOR SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEARS, AND
CENTURY
■ YEAR 2000 COMPLIANT
■ SOFTWARE CLOCK CALIBRATIO N
■ AUTOMATIC POWER-FAIL DETECT AND
SWITCH CIRCUITRY
2
■ I
C BUS COMPATIBLE
■ 56 BYTES OF GENERAL PURPOSE RAM
■ ULTRA-LOW BATTERY SUPPLY CURRENT
OF 450nA
■ LOW OPERATING CURRENT OF 300µA
■ OPERATING TEMPERATURE OF –40 to
85°C
■ AUTOMATIC LEAP YEAR C OMPENSATION
■ SPECIAL SOFTWARE PROGRAMMABLE
OUTPUT
■ PACKAGING OPTIONS INCLUDE:
– 28-lead SOIC and SNAPHAT
ordered separately)
–SO8
®
TOP (to be
M41T56
Figure 1. 8-pin SOIC Package
8
1
SO8 (M)
150mil Width
Figure 2. 28-pin SOIC Package
SNAPHAT (SH)
Battery & Crystal
28
1
SOH28 (MH)
1/24June 2004
M41T56
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 8-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. 8-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Stop data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. Acknowledge Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 9. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 12.Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 13.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/24
M41T56
Figure 16.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Crystal Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Power Down/Up Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Power Down/Up Trip Points DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 18.SO8 – 8-pin Plastic Small Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. SO8 – 8-pin Plastic Small Outline, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . 18
Figure 19.SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline. 19
Table 12. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Mech. Data. . . . . 19
Figure 20.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 20
Table 13. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 20
Figure 21.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 21
Table 14. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 16. SNAPHAT Battery/Crystal Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 17. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3/24
M41T56
SUMMARY DESCRIPTION
The M41T56 TIMEKEEPER® is a low power, 512bit static CMOS RAM organized as 64 word s by 8
bits. A built-in 32,768Hz oscillator (external crystal
controlled) and the first 8 bytes of the RAM are
used for the clock/c alendar func tion and ar e configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a twoline, bi-directiona l bus. Th e built-in ad dress regi ster is incremented automatically after each WRITE
or READ data byte.
The M41T56 clock has a bui lt-in p ower s ense ci rcuit which detects power failures and automatically switches to the battery supply during power
failures. The energy needed to s ustain the RAM
and clock operations can be supplied from a small
lithium coin cell.
Typical data retention time is in excess of 10 years
with a 50mAh, 3V lithium cell. The M41T56 is supplied in an 8-lead Pl astic SOIC package or a 28lead SNAPHAT
®
package.
Figure 3. Logic Diagram Table 1. Signal Names
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both en ds for direct connection to a separate SNAPHAT ho usin g cont ain ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential batter y and crys tal dama ge due to
the high temperatures required for device surfacemounting . Th e SNA PHAT h ous ing i s key ed t o pr event reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic antistatic tubes or in Tape & Reel form.
For the 28-lead SOIC, the battery/crystal package
(e.g., SNAPHAT) part number is “M4TxxBR12SH” (see Table 16., page 22).
Caution: Do not place the SNAPHAT battery/crystal package “M4T xx -BR12SH” in conducti ve foam
as this will drain the lithium button-cell battery.
OSCI
SCL
V
CC
M41T56
V
SS
V
BAT
OSCO
SDA
FT/OUT
AI02304B
OSCI Oscillator Input
OCSO Oscillator Output
FT/OUT
SDA Serial Data Address Input / Output
SCL Serial Clock
V
BAT
V
CC
V
SS
Frequency Test / Output Driver
(Open Drain)
Battery Supply Voltage
Supply Voltage
Ground
4/24
Figure 4. 8-pin SOIC Connections Figure 5. 28-pin SOIC Connections
M41T56
M41T56
OSCI V
1
2
V
BAT
SS
3
4
AI02306B
Figure 6. Block Diagram
OSCI
OSCO
FT/OUT
V
CC
V
SS
V
BAT
8
FT/OUTOSCO
7
SCL
6
SDAV
5
OSCILLATOR
32.768 kHz
VOLTAGE
SENSE
and
SWITCH
CIRCUITRY
CC
DIVIDER
CONTROL
LOGIC
NC V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1 Hz
M41T56
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI03607
SECONDS
MINUTES
CENTURY/HOURS
DAY
DATE
MONTH
YEAR
CONTROL
CC
NC
FT/OUT
NC
NC
NC
NC
NC
SCL
NC
NC
NC
SDA
NC
SCL
SDA
SERIAL
BUS
INTERFACE
RAM
(56 x 8)
ADDRESS
REGISTER
AI02566
5/24
M41T56
OPERATION
The M41T56 clock operates as a slave devic e on
the serial bus. Access is obtained by implementing
a start condition fo llowed by th e correc t slave ad dress (D0h). The 64 bytes contained in the device
can then be accessed sequentially in the following
order:
1. Seconds Register
2. Minutes Register
3. Century/Hours Register
4. Day Register
5. Date Register
6. Month Register
7. Years Register
8. Control Register
9 to 64.RAM
The clock continually monitors V
tolerance condition. Shou ld V
the device termina tes an access in progress and
resets the device ad dress counter. Inputs to the
device will not be recogniz ed at this time to prevent erroneous data from be ing written to th e device from an out of toler ance system. When V
falls below V
, the device automatica lly switch -
BAT
es over to the battery and powers down into an ultra low current mode of operation to conserve
battery life. Upon power-up, the dev ice switches
from battery to V
when V
goes above V
CC
CC
at V
and recognizes inputs
BAT
volts.
PFD
2-Wire Bus Characteristics
This bus is inten ded for communication betwe en
different ICs. It consist s of two lines: o ne bi- direc tional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL line s mu st
be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the
bus is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line while the clock line is
High will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
for an out of
CC
fall below V
CC
PFD
CC
Bus not busy. Both data and clock l ines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state o f the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data valid. The state of the data line r epresents
valid data when after a start condition, the data line
is stable for the durati on of the Hi gh period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
,
transmitted byte-wide and eac h rec eiv er ac kn owl edges with a ninth bit.
By definition, a device that gives out a message is
called “transmitter,” the receiving device th at gets
the message is call ed “receiver.” The de vice that
controls the messag e is called “master. ” The devices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowle dge B it. Thi s Ack nowledg e Bi t is
a low level put on the bus by the receiver, whereas
the master generates an extra acknowledge related clock pulse.
A slave receiver which is addresse d is obliged to
generate an acknowledge after the reception of
each byte. Also, a master recei ver must generate
an acknowledge aft er the reception of ea ch byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line durin g the ackn owledge clo ck pulse
in such a way that the SDA line is a st able Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end-of-data to the slave transmitte r by not
generating an acknowl edge on the last byte that
has been cl ocke d out o f the slav e. In t his ca se, th e
transmitter must leave the data line High to enable
the master to generate the STOP condition.
6/24
Figure 7. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
M41T56
START
CONDITION
Figure 8. Acknowledge Sequence
START
SCLK FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
CHANGE OF
DATA ALLOWED
12 89
MSB LSB
STOP
CONDITION
AI00587
CLOCK PULSE FOR
ACKNOWLEDGEMENT
AI00601
7/24
M41T56
Figure 9. Bus Timing Requirements Sequence
SDA
SCL
tHD:STAtBUF
tR
SP
tHIGH
tLOW
tF
tSU:DAT
tHD:DAT
SR
tHD:STA
Table 2. AC Characteristics
Symbol
f
SCL
t
LOW
t
HIGH
t
R
t
F
t
HD:STA
t
SU:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V (except where not ed).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
SCL Clock Frequency 0 100 kHz
Clock Low Period 4.7 µs
Clock High Period 4 µs
SDA and SCL Rise Time 1 µs
SDA and SCL Fall Time 300 ns
START Condition Hold Time
(after this period the first clock pulse is generated)
START Condition Setup Time
(only relevant for a repeated start condition)
Data Setup Time 250 ns
(2)
Data Hold Time 0 µs
STOP Condition Setup Time 4.7 µs
Time the bus must be free before a new transmission can start 4.7 µs
Parameter
(1)
Min Max Unit
4µs
4.7 µs
tSU:STOtSU:STA
P
AI00589
8/24
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