STMicroelectronics M41ST85Y, M41ST85W Technical data

M41ST85Y

M41ST85W

5.0 or 3.0V, 512 bit (64 x 8) Serial RTC and NVRAM Supervisor

FEATURES SUMMARY

■5.0 OR 3.0V OPERATING VOLTAGE

■SERIAL INTERFACE SUPPORTS I2C BUS (400 KHz)

■NVRAM SUPERVISOR FOR EXTERNAL LPSRAM

■OPTIMIZED FOR MINIMAL INTERCONNECT TO MCU

■2.5 TO 5.5V OSCILLATOR OPERATING VOLTAGE

■AUTOMATIC SWITCH-OVER AND DESELECT CIRCUITRY

■CHOICE OF POWER-FAIL DESELECT VOLTAGES

–M41ST85Y: VCC = 4.5 to 5.5V; 4.20V ≤ VPFD ≤ 4.50V

–M41ST85W: VCC = 2.7 to 3.6V; 2.55V ≤ VPFD ≤ 2.70V

■1.25V REFERENCE (for PFI/PFO)

■COUNTERS FOR TENTHS/HUNDREDTHS OF SECONDS, SECONDS, MINUTES, HOURS, DAY, DATE, MONTH, YEAR, AND CENTURY

■44 BYTES OF GENERAL PURPOSE RAM

■PROGRAMMABLE ALARM AND INTERRUPT FUNCTION (VALID EVEN DURING BATTERY BACK-UP MODE)

■WATCHDOG TIMER

■MICROPROCESSOR POWER-ON RESET

■BATTERY LOW FLAG

■POWER-DOWN TIMESTAMP (HT BIT)

■ULTRA-LOW BATTERY SUPPLY CURRENT OF 500nA (MAX)

Figure 1. 28-pin SOIC Package

SNAPHAT (SH)

Battery & Crystal

28

1

SOH28 (MH)

Figure 2. 28-pin (300mil) SOIC Package

EMBEDDED Crystal

SOX28 (MX)

■PACKAGING INCLUDES A 28-LEAD SOIC AND SNAPHAT® TOP (to be ordered separately)

■SOIC SNAPHAT PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY AND CRYSTAL

■SOIC EMBEDDED CRYSTAL PACKAGE (MX) OPTION

September 2004

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M41ST85Y, M41ST85W

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. 28-pin (300mil) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. 28-pin, 300mil SOIC (MX) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 8. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 10.WRITE Cycle Timing: RTC & External SRAM Control Signals . . . . . . . . . . . . . . . . . . . . . 9

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 11.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 12.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 13.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 14.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power-down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 2. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 15.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 16.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 17.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 18.Back-Up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 19.RSTIN1 & RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Output Driver Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

trec Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. trec Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 9. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 20.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 21.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 12. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 22.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 13. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 23.SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline . . . . . . . . 28 Table 14. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 28 Figure 24.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 29 Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Mechanical Data . . . . . . . 29 Figure 25.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 30 Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Mechanical Data . . . . . . 30 Figure 26.SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline. 31 Table 17. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Mech. Data. . . . . 31

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 19. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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SUMMARY DESCRIPTION

The M41ST85Y/W Serial TIMEKEEPER® /Controller SRAM is a low power 512-bit, static CMOS SRAM organized as 64 words by 8 bits. A built-in 32.768 kHz oscillator (external crystal controlled) and 8 bytes of the SRAM (see Table 2., page 14) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format.

An additional 12 bytes of RAM provide status/control of Alarm, Watchdog and Square Wave functions. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41ST85Y/W has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a small lithium button-cell supply when a power failure occurs.

Functions available to the user include a non-vol- atile, time-of-day clock/calendar, Alarm interrupts, Watchdog Timer and programmable Square Wave output. Other features include a Power-On Reset as well as two additional debounced inputs (RSTIN1 and RSTIN2) which can also generate an output Reset (RST). The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically.

The M41ST85Y/W is supplied in a 28-lead SOIC SNAPHAT® package (which integrates both crystal and battery in a single SNAPHAT top) or a 28pin, 300mil SOIC package (MX) which includes an embedded 32kHz crystal.

The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be mounted on top of the SOIC package after the completion of the surface mount process.

Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion.

The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4TXX-BR12SH” (see Table 19., page 32).

Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.

The 300mil, embedded crystal SOIC requires only a user-supplied battery to provide non-volatile operation.

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Figure 3. Logic Diagram

(1)

VCC VBAT

SCL		ECON
SDA		RST
EX	M41ST85Y	IRQ/FT/OUT
RSTIN1	M41ST85W	SQW
RSTIN2		PFO
WDI		VOUT
PFI

VSS

AI03658

Note: 1. For 28-pin, 300mil embedded crystal SOIC only.

Table 1. Signal Names

	ECON							Conditioned Chip Enable Output
								External Chip Enable
	EX
								Interrupt/Frequency Test/Out Output
	IRQ/FT/OUT
								(Open Drain)
	PFI							Power Fail Input
								Power Fail Output
	PFO
								Reset Output (Open Drain)
	RST
								Reset 1 Input
	RSTIN1
								Reset 2 Input
	RSTIN2
	SCL							Serial Clock Input
	SDA							Serial Data Input/Output
	SQW							Square Wave Output
	WDI							Watchdog Input
	VCC							Supply Voltage
	VOUT							Voltage Output
	VSS							Ground
	VBAT(1)							Battery Supply Voltage
	NC							No Connect
	NF							No Function

Note: 1. For 28-pin, 300mil embedded crystal SOIC only.

Figure 4. 28-pin SOIC Connections

		SQW							VCC
						1	28
			NC			2	27		EX
			NC			3	26
									IRQ/FT/OUT
			NC			4	25		VOUT
			NC			5	24		NC
			NC			6	23		NC
			NC			7	M41ST85Y 22		PFI
			WDI			8	M41ST85W 21		NC
		RSTIN1				9	20		SCL
						10	19		NC
	RSTIN2
			NC			11	18
											RST
			NC			12	17		NC
						13	16		SDA
			PFO
		VSS				14	15					CON
										E
							AI03659

Figure 5. 28-pin, 300mil SOIC (MX)

Connections

		NF			1	28		VCC
		NF			2	27		EX
		NF			3	26		IRQ/FT/OUT
		NF			4	25		VOUT
		NC			5	24	NC
		NC			6	23		PFI
		NC			7	M41ST85Y 22		SCL
	SQW				8	M41ST85W 21			NC
		WDI			9	20			NC
					10	19
	RSTIN1								RST
					11	18		NC
RSTIN2
					12	17		SDA
		PFO
		NC			13	16				E	CON
		VSS			14	15			VBAT
												AI06370d

Note: No Function (NF) pins should be tied to VSS. Pins 1, 2, 3, and 4 are internally shorted together.

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Figure 6. Block Diagram

				REAL TIME CLOCK
				CALENDAR
	SDA	I2C		44 BYTES
				USER RAM
		INTERFACE		RTC w/ALARM	AFE
	SCL
				& CALIBRATION	IRQ/FT/OUT(1)
				WATCHDOG	WDS
	(2)	32KHz
Crystal
		OSCILLATOR
				SQUARE WAVE	SQW
	WDI
	VCC				VOUT
		VBAT
		VBL= 2.5V	COMPARE	BL
		VSO = 2.5V	COMPARE
		VPFD = 4.4V	COMPARE	POR
RSTIN1		(2.65V for ST85W)			RST(1)
RSTIN2
	EX				ECON
	PFI		COMPARE		PFO
1.25V
(Internal)					AI03932

Note: 1. Open drain output

2. Integrated into SOIC package for MX package option.

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Figure 7. Hardware Hookup

Unregulated	Regulator			M41ST85Y/W
	VIN	VCC		VCC	VOUT	VCC
Voltage
					ECON	E
						M68Z128Y/W
				EX		or
			MCU			M68Z512Y/W
				SCL
			From	WDI	SDA
				RSTIN1	RST	To RST
	Pushbutton			RSTIN2	SQW	To LED Display
R1		Reset			PFO	To NMI
				PFI
R2				(1)	IRQ/FT/OUT	To INT
				VBAT
				VSS
						AI03660

Note: 1. Required for embedded crystal (MX) package only.

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OPERATING MODES

The M41ST85Y/W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 64 bytes contained in the device can then be accessed sequentially in the following order:

1.Tenths/Hundredths of a Second Register

2.Seconds Register

3.Minutes Register

4.Century/Hours Register

5.Day Register

6.Date Register

7.Month Register

8.Year Register

9.Control Register

10.Watchdog Register

11 - 16. Alarm Registers

17 - 19. Reserved

20. Square Wave Register

21 - 64. User RAM

The M41ST85Y/W clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC.

Write protection continues until VCC reaches VPFD(min) plus trec (min).

For more information on Battery Storage Life refer to Application Note AN1012.

2-Wire Bus Characteristics

The bus is intended for communication between different ICs. It consists of two lines: a bi-direction- al data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

–Data transfer may be initiated only when the bus is not busy.

–During data transfer, the data line must remain stable whenever the clock line is High.

–Changes in the data line, while the clock line is High, will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy. Both data and clock lines remain High.

Start data transfer. A change in the state of the data line, from High to Low, while the clock is High, defines the START condition.

Stop data transfer. A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition.

Data Valid. The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message is called “receiver.” The device that controls the message is called “master.” The devices that are controlled by the master are called “slaves.”

Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition.

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Figure 8. Serial Bus Data Transfer Sequence

			DATA LINE
			STABLE
			DATA VALID
	CLOCK
	DATA
	START		CHANGE OF		STOP
	CONDITION		DATA ALLOWED		CONDITION
					AI00587
	Figure 9. Acknowledgement Sequence
					CLOCK PULSE FOR
	START				ACKNOWLEDGEMENT
	SCL FROM	1	2	8	9
	MASTER
	DATA OUTPUT	MSB		LSB
	BY TRANSMITTER
	DATA OUTPUT
	BY RECEIVER
					AI00601

Figure 10. WRITE Cycle Timing: RTC & External SRAM Control Signals

EX

tEXPD

tEXPD

ECON

AI03663

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M41ST85Y, M41ST85W

READ Mode

In this mode the master reads the M41ST85Y/W slave after setting the slave address (see Figure 11., page 10). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ Mode Control Bit (R/W=1). At this point the master transmitter becomes the master receiver.

The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Clock. The M41ST85Y/W slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2.

Figure 11. Slave Address Location

This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter (see Figure 12., page 10).

The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to a non-clock or RAM address.

Note: This is true both in READ Mode and WRITE Mode.

An alternate READ Mode may also be implemented whereby the master reads the M41ST85Y/W slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 13., page 11).

R/W

START

A

SLAVE ADDRESS

MSB
1		0		1		0		0
	1

LSB

0

AI00602

Figure 12. READ Mode Sequence

BUS ACTIVITY: MASTER

SDA LINE

BUS ACTIVITY:

START

R/W

WORD

START

R/W

S

S

DATA n

DATA n+1

ADDRESS (An)

ACK

ACK

ACK

ACK

ACK

SLAVE

SLAVE

ADDRESS

ADDRESS

	STOP
DATA n+X	P
	NO ACK

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M41ST85Y, M41ST85W

Figure 13. Alternate READ Mode Sequence

BUS ACTIVITY: MASTER

SDA LINE

BUS ACTIVITY:

START		R/W									STOP
S			DATA n		DATA n+1	DATA n+X					P
			ACK	ACK	ACK	ACK				ACK
	SLAVE									NO

ADDRESS

AI00895

WRITE Mode

In this mode the master transmitter transmits to the M41ST85Y/W slave receiver. Bus protocol is shown in Figure 14., page 11. Following the START condition and slave address, a logic '0' (R/ W=0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is

strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock. The M41ST85Y/W slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address (see Figure 11., page 10) and again after it has received the word address and each data byte.

Figure 14. WRITE Mode Sequence

BUS ACTIVITY: MASTER

SDA LINE

BUS ACTIVITY:

START		R/W	WORD					STOP
S				DATA n		DATA n+1	DATA n+X	P
			ADDRESS (An)
		ACK		ACK	ACK	ACK		ACK
	SLAVE
	ADDRESS						AI00591

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