STMicroelectronics M41ST85Y, M41ST85W Technical data

Serial RTC and NVRAM Supervisor

FEAT URES SUM MARY

■ 5.0 OR 3.0V OPERATING VOLTAGE

■ SERIAL INTERFACE SUP PORT S I

(400 KHz)

■ NVRAM SUPERVISO R FOR EXTERNAL

LPSRAM

■ OPTIMI ZE D FOR MINIM A L

INTERCONNECT TO MCU

■ 2.5 TO 5.5V OSCILLATOR OPERATING

VOLTAGE

■ AUTOMATIC SWITCH-OVER AND

DESELECT CIRCUITRY

■ CHOICE OF POWER-FAIL DESEL ECT

VOLTAGES
– M41ST85Y: V

4.20V ≤ V

– M41ST85W: V

2.55V ≤ V

■ 1.25V REFERENCE (for PFI/PFO)

■ COUNTERS FOR TENTHS/HUNDREDTHS

PFD

PFD

= 4.5 to 5.5V;

CC

≤ 4.50V

= 2.7 to 3.6V;

CC

≤ 2.70V

OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY

■ 44 BYTES OF GENERAL PURPOSE RAM

■ PROGRAMMABLE ALAR M AN D

INTERRUPT FUNCTION (VALID EVEN
DURING BATTERY BACK-UP MODE)

■ WATCHDOG TIMER

■ MICROPROCESSOR POWER-ON RESET

■ BATTERY LOW FLAG

■ POWER-DOWN TIMESTAMP (HT BIT)

■ ULTRA-LOW BATTER Y SUPPLY CURRE NT

OF 500nA (MAX)

■ PACKAGING INCLUDES A 28-LEAD SOIC

AND SNAPHAT

®

TOP (to be ordered

separately)

■ SOIC SNAPHAT PACKAGE PROVIDES

DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY
AND CRYSTAL

■ SOIC EMBEDDED CRYSTAL PACKAGE

(MX) OPTION

2

C BUS

M41ST85Y

M41ST85W

5.0 or 3.0V, 512 bit (64 x 8)

Figure 1. 28-pi n S O I C Package

SNAPHAT (SH)

Battery & Crystal

28

1

SOH28 (MH)

Figure 2. 28-pin (300mil) SOIC Package

EMBEDDED Cryst al

SOX28 (MX)

1/34September 2004

M41ST85Y, M41ST85W

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. 28-pin (300mil) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. 28-pin, 300mil SOIC (MX) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 8. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 9. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 10.WRITE Cycle Timing: RTC & External SRAM Control Signals. . . . . . . . . . . . . . . . . . . . . 9

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 11.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 12.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 13.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 14.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power-down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

TIMEKEEPER

Table 2. TIMEKEEPER

®

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

®

Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 15.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 16.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 17.Alarm Interrupt Reset Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 3. A larm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 18.Back-Up Mode Alarm Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4. S quare Wav e Output Frequen cy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 19.RSTIN1

& RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2/34

M41ST85Y, M41ST85W

Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Output Driver Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

t

Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

rec

Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. t

Table 7. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 9. DC and A C Measurem ent Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 20.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 10.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5

Figure 21.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 12.AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 22.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 13.Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

rec

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 23.SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline. . . . . . . . 28

Table 14. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 28

Figure 24.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 29

Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Mechanical Data . . . . . . . 29

Figure 25.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 30

Table 16. SH – 4-pin SNAPHAT Housing for 120mAh B attery & Crystal, Mechanical Data . . . . . . 30

Figure 26.SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline. 31

Table 17. SOX28 – 28-lead P lastic Small Ou tline, 300mils, Embed ded Crystal, Mech. Data. . . . . 31

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 18.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 19.SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 20.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3/34

M41ST85Y, M41ST85W

SUMMARY DESCRIPTIO N

The M41ST85Y/W Serial TIMEKEEPER®/Con­troller SRAM is a low power 512-bit, static CMOS
SRAM organized as 64 words by 8 bi ts. A built-in

32.768 kHz oscilla tor (external crystal controlled)
and 8 bytes of the SRAM (see Table 2., page 14)
are used for the c lock/calendar function and are
configured in binary coded decimal (BCD) format.

An additional 12 bytes of RAM provide status/con­trol of Alarm, Watchdog and Square Wav e func­tions. Addresses and data are transferred serially
via a two line, bi-directional I
built-in address register is incremented automati­cally after each WRITE or READ data byte. The
M41ST85Y/W has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power f ail­ure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
small lithium button-cell supply when a power fail­ure occurs.

Functions available to the user include a non-vol­atile, time-of-day clock/calendar, Alarm interrupts,
Watchdog Timer and programmable Square
Wave output. Other features include a Power-On
Reset as well as two addi tional d ebounc ed inputs
(RSTIN1
output Reset (RST

and RSTIN2) which can also generate an

). The eight clock address loca­tions contain the century, year, month, date, day,
hour, minute, second and tenths/hundredt hs of a
second in 24 hour BCD format. Corrections for 28,
29 (leap year - valid until year 2100), 30 and 31
day months are made automatically.

2

C interface. The

The M41ST85Y/W is supplied in a 28-lead SOIC
SNAPHAT

®

package (which integrates b oth crys­tal and battery in a single SNAP HA T top) o r a 28­pin, 300mil SOIC package (MX) which includes an
embedded 32kHz crystal.

The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at bot h ends for direct con­nection to a separate SNAPHAT housing contain­ing the battery and crystal. The unique design
allows the SNAPHAT battery/crystal package to
be mounted on top of th e S OIC package after the
completion of the surface mount process.

Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur­face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.

The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 2 8-lead SOIC, t he ba t­tery/crystal package (e.g., SNAPHAT) part num­ber is “M4TXX-BR12SH” (see Table

19., page 32).

Caution: Do not place the SNAPHAT battery/crys­tal top in conductive foam, as this will drain the lith­ium button-cell battery.

The 300mil, embedded crystal SOIC requires only
a user-supplied battery to provide non-volatile op­eration.

4/34

M41ST85Y, M41ST85W

Figure 3. Logic Diagram

V

CC

SCL

SDA

EX

M41ST85Y

RSTIN1

M41ST85W

RSTIN2

WDI

PFI

V

SS

Note: 1. For 28 -pin, 300mil em bedded cry st al SOIC only.

V

BAT

(1)

E

CON

RST

IRQ/FT/OUT

SQW

PFO

V

OUT

AI03658

Table 1. Signal Names

E

CON

EX External Chip Enable

/FT/OUT

IRQ

PFI Power Fail Input
PFO
RST
RSTIN1
RSTIN2
SCL Serial Clock Input
SDA Serial Data Input/Output
SQW Square Wave Output
WDI Watchdog Input
V

CC

V

OUT

V

SS

(1)

V

BA T

NC No Connect
NF No Function

Note: 1. For 28 -pin, 300mil em bedded cry st al SOIC only.

Conditioned Chip Enable Output

Interrupt/Frequency Test/Out Output
(Open Drain)

Power Fail Output
Reset Output (Open Drain)
Reset 1 Input
Reset 2 Input

Supply Voltage
Voltage Output
Ground
Battery Supply Voltage

Figure 4. 28-pin SOIC Connections Figure 5. 28-pin, 300mil SOIC (MX)

Connections

SQW V

NC
NC
NC
NC
NC
NC

WDI
RSTIN1
RSTIN2

NC

1
2
3
4
5
6

M41ST85Y

7

M41ST85W

8
9
10
11

12
PFO
V

SS

13

14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI03659

CC

EX
IRQ/FT/OUT
V

OUT

NC
NC
PFI
NC
SCL
NC
RST
NCNC
SDA
E

CON

NF V
NF
NF

NF
NC
NC
NC

SQW

WDI

RSTIN1
RSTIN2

PFO

NC

V

SS

Note: No Funct ion ( NF) pin s shou ld be tie d t o VSS. Pins 1, 2, 3, and

4 are inter nally shorted together.

1
2
3
4
5
6

M41ST85Y

7

M41ST85W

8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

EX
IRQ/FT/OUT
V
NC

PFI
SCL
NC
NC

RST
NC
SDA
E
V

CC

OUT

CON
BAT

AI06370d

5/34

M41ST85Y, M41ST85W

Figure 6. Block Diagram

SDA

SCL

(2)

Crystal

WDI

V

CC

V

BAT

I2C

INTERFACE

32KHz

OSCILLATOR

VBL= 2.5V

COMPARE

REAL TIME CLOCK

CALENDAR

44 BYTES

USER RAM

RTC w/ALARM

& CALIBRATION

WATCHDOG

SQUARE W AVE

BL

AFE

WDS

IRQ/FT/OUT

SQW

V

OUT

(1)

V

SO

V

PFD

RSTIN1
RSTIN2

EX

PFI

1.25V
(Internal)

Note: 1. Open drain outpu t

2. Integrated int o S O I C package for MX package option.

= 2.5V

= 4.4V

(2.65V for ST85W)

COMPARE

COMPARE

COMPARE

POR

RST

E

CON

PFO

(1)

AI03932

6/34

Figure 7. Hardware Hookup

M41ST85Y, M41ST85W

Unregulated

Voltage

R1

R2

Note: 1. Required for emb edded crystal (MX) pack age only.

Regulator

V

V

IN

Pushbutton

Reset

CC

From MCU

M41ST85Y/W

V

CC

EX

SCL

WDI

RSTIN1

RSTIN2

PFI

(1)

V

BAT

V

SS

V

OUT

E

CON

SDA

RST

SQW

PFO

IRQ/FT/OUT

V

CC

E

M68Z128Y/W

or

M68Z512Y/W

To RST

To LED Display
To NMI

To INT

AI03660

7/34

M41ST85Y, M41ST85W

OPERAT IN G MODES

The M41ST85Y/W clock operates as a slave de­vice on the serial bus. Access is obtained by im­plementing a start condition followed by the
correct slave address (D0h). The 64 bytes con­tained in the device can then be accessed sequen­tially in the following order:

1. Tenths/Hundredths of a Second Register

2. Seconds Register

3. Minutes Register

4. Century/Hours Register

5. Day Register

6. Date Register

7. Month Register

8. Year Register

9. Control Register

10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved

20. Square Wave Register
21 - 64. User RAM
The M41ST85Y/W clock continually monitors V

for an out-of-tolerance condition. Should VCC fall
below V

, the device terminates an access in

PFD

progress and resets t he device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data f rom bei ng wri tten
to the device from a an out-of-tolerance system.
When V

falls below VSO, the device a utomati-

CC

cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve batte ry life. As system p ower returns and

rises above VSO, the battery is disconnected,

V

CC

and the power supply is switched to external V
Write protection continues until V

V

PFD

(min) plus t

rec

(min).

reaches

CC

For more information on Battery Storage Life refer
to Application Note AN1012.

2-Wire Bus Characteristics

The bus is intended for communication between
different ICs. It consists of two lines: a bi-direction­al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.

The following protocol has been defined:
– Data transfer may be initiated only when the bus

is not busy.

CC

CC

– During data transfer, the data line must remain

stable whenever the clock line is High.

– Changes in the data line, while the clock line is

High, will be interpreted as control signals.

Accordingly, the following bus conditions have
been defined:

Bus not busy. Both data and clock li nes remain
High.

Start data transfer. A change in the s tate of the
data line, from High t o Low, while the c lock is High,
defines the START condition.

Stop data transfer. A c hange in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.

Data Valid. T he state of the data line rep resents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.

Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl­edges with a ninth bit.

By definition a device that gives o ut a m essag e is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de­vices that are controlled by the master are cal led
“slaves.”

Acknowledge. E ac h byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is

.

a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat­ed clock pulse. A slave receiver which is ad­dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.

The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur­ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig­nal an end of data to the slave transm itter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.

8/34

Figure 8. Serial Bus Data Transfer Sequence

DATA LINE

STABLE

DATA VALID

CLOCK

DATA

M41ST85Y, M41ST85W

START

CONDITION

CHANGE OF

DATA ALLOWED

Figure 9. Acknowledgement Sequence

START

SCL FROM
MASTER

DATA OUTPUT
BY TRANSMITTER

DATA OUTPUT
BY RECEIVER

12 89

MSB LSB

Figure 10. WRITE Cycle Timing: RTC & External SRAM Control Signals

EX

STOP

CONDITION

AI00587

CLOCK PULSE FOR

ACKNOWLEDGEMENT

AI00601

E

tEXPD

tEXPD

CON

AI03663

9/34

M41ST85Y, M41ST85W

READ Mode

In this mode the master reads the M 41ST85Y/W
slave after setting the slave address (see Figure

11., page 10). Following the WRITE Mode Control

Bit (R/W
address 'An' is written to the on-chip address
pointer. Next the START condition and slave ad­dress are repeated followed by the READ Mode
Control Bit (R/W
mitter becomes the master receiver.

The data byte which was add re ssed will be trans­mitted and the master receiver will send an Ac­knowledge Bit to the slave transmitter. The
address pointer is only i ncremented on rec eption
of an Acknowledge Clock. The M41ST85Y/W
slave transmitter will now place the data byte at
address An+1 on the bus, the master receiver
reads and acknowledges the new byte and the ad­dress pointer is incremented to An+2.

Figure 11. Slave Address Location

=0) and the Acknowledge Bit, the word

=1). At this point the master trans-

This cycle of reading con secutive addresses will
continue until the master rec eiver sends a STOP
condition to the slave transmitter (see Figure

12., page 10).

The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resum e ei­ther due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.

Note: This is true both in READ Mode and WRITE
Mode.

An alternate READ Mode may also be implement­ed whereby the master reads the M41ST85Y/W
slave without first writing to the (volatile) addres s
pointer. The first address that is read is the l ast
one stored in the pointer (see Figure

13., page 11).

R/W

START A

Figure 12. RE A D Mo de S equence

BUS ACTIVITY:
MASTER

SDA LINE

BUS ACTIVITY:

START

S

ADDRESS

R/W

ADDRESS (An)

ACK

SLAVE

DATA n+X

WORD

MSB

STOP

P

SLAVE ADDRESS

0100011

START

S

ACK

SLAVE

ADDRESS

LSB

AI00602

R/W

DATA n DATA n+1

ACK

ACK

ACK

10/34

AI00899

NO ACK

Figure 13. Al te rnat e RE A D Mode Seque nce

M41ST85Y, M41ST85W

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

START

S

SLAVE

ADDRESS

R/W

DATA n DATA n+1 DATA n+X

ACK

WRITE Mode

In this mode the master transmitter transmits to
the M41ST85Y/W slave receiver. Bus protocol is
shown in Figure 14., page 11. Following the
START condition and slave address, a logic '0' (R/

=0) is placed on the bus and indicates to the ad-

W
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is

Figure 14. WR I TE Mode Seque nce

BUS ACTIVITY:
MASTER

START

R/W

STOP

PSDA LINE

ACK

ACK

ACK

NO ACK

AI00895

strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST85Y/W sla ve receiver will send
an acknowledge clock to the master transmitter af­ter it has received the slave address (see Figure

11., page 10) and again after it has received the

word address and each data byte.

STOP

BUS ACTIVITY:

S

ADDRESS

SLAVE

WORD

ADDRESS (An)

ACK

DATA n DATA n+1 DATA n+X

ACK

ACK

ACK

PSDA LINE

ACK

AI00591

11/34