STMicroelectronics M27W101 Technical data

M27W101

1 Mbit (128Kb x8) Low Voltage UV EPROM and OTP EPROM

■ 2.7V to 3.6V LOW VOLTAGE in READ

OPERATION

■ ACCESS TIME:

–70ns at V –80ns at V

■ PIN COMPATIBLE with M27C1001

■ LOW POWER CONSUMPTION:

= 3.0V to 3.6V

CC

= 2.7V to 3.6V

CC

– Active Current 15mA at 5MHz – Standby Current 15µA

■ PROGRAMMING TIME 100µs/byte

■ HIGH RELIABILITY CMOS TECHNOLOGY

– 2,000V ESD Protection – 200mA Latchup Protection Immunity

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: 05h

DESCRIPTION

The M27W101 is a low voltage 1 Mbit EPROM offered in two range UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage and is organized as 131,072 by 8 bits.

The M27W101 operates in the read mode with a supply voltage as low as 2.7V at –40 to 85 °C temperature range.

The decrease in operating power allows either a reduction of the size of the battery or an increas e in the time between battery recharges.

The FDIP32W (window ceramic frit-seal package) has a transparent lid which all ows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.

For application where the content is programmed only one time and erasure is not required, the M27W101 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages.

32

1

FDIP32W (F) PDIP32 (B)

PLCC32 (K) TSOP32 (N)

Figure 1. Logic Diagram

V

17

A0-A16

P

E

G

32

V

CC

M27W101

V

SS

1

8 x 20 mm

PP

8

Q0-Q7

AI01587

1/15April 2000

M27W101

Figure 2A. DIP Connections

V

1

PP

2

A15

3

A12

4 5

A7

6

A6

7

A5

8

A4 A3 A2 A1 A0

Q0

Q2 SS

M27W101

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

AI02674

V

CC

PA16 NC A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5Q1 Q4 Q3V

Figure 2B. LCC Connections

A16

A7 A6 A5 A4 A3 A2 A1 A0

Q0

A12

9

Q1

VPPV

A15

1

32

M27W101

17

Q2

Q3

SS

V

Q4

CC

P

Q5

NC

25

Q6

A14 A13 A8 A9 A11 G A10 E Q7

AI01588

Figure 2C. TSOP Connections

A11 G

A9

A8 A13 A14

NC

V

CC

V

PP

A16 A15 A12

A7

A6

A5

A4 A3

1

P

M27W101

8

(Normal)

9

16 17

32

25 24

AI01589

A10 E Q7 Q6 Q5 Q4 Q3 V

SS

Q2 Q1 Q0 A0 A1 A2

Table 1. Signal Names

A0-A16 Address Inputs

Q0-Q7 Data Outputs

E

G

P

V

PP

V

CC

V

SS

NC Not Connected Internally

Chip Enable

Output Enable

Program

Program Supply

Supply Voltage

Ground

2/15

M27W101

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the ra ting "Operating Temperature Range", stresses abo ve those lis ted in the Table "Absolute Maxi m um Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indi cated in t he Operat in g section s of this specification is not impl i ed. Exposure to Absolute Maximum Rating c onditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .

2. Minimum D C volta ge on Input or O utpu t is –0. 5V with possibl e under shoot t o –2.0V for a period less than 20n s. Maxim um D C

voltage on Output is V

3. Depends on range.

Ambient Operating Temperature

Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC +2V for a period l ess than 20ns.

CC

(3)

–40 to 85 °C

Table 3. Operating Modes

Mode E

Read Output Disable Program Verify Program Inhibit Standby Electronic Signature

Note: X = VIH or VIL, VID = 12V ± 0.5V.

G P A9

V

IL

V

IL

V

VIHVIL Pulse

IL

V

IL

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

X XXX

V

IL

XX XX

X

V

IH

X

XX

V

IH

V

ID

V

PP

V

or V

CC

SS

V

or V

CC

SS

V

PP

V

PP

V

PP

V

or V

CC

SS

V

CC

Q7-Q0

Data Out

Hi-Z

Data In

Data Out

Hi-Z Hi-Z

Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code Device Code

V

IL

V

IH

00100000 20h 00000101 05h

3/15

M27W101

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only, not 100% tested.

Input Capacitance Output Capacitance

(1)

(TA = 25 °C, f = 1 MHz)

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE UNDER

TEST

CL

CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance

V

IN

OUT

= 0V

6pF

12 pF

OUT

AI01823B

DEVICE OPERATION

The operating modes of the M27W101 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for V

and 12V on A9 for Electronic

PP

Signature.

Read Mode

The M27W101 has two control functions, both of which must be logically ac tive in order to obtain data at the output s. Chip Enable (E

) is the power control and should be used for device selection. Output Enable (G

) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time

4/15

(t

) is equal to the delay from E to output

AVQV

(t

). Data is available at the output after a delay

ELQV

of t E

has been low and the addresses have been sta-

ble for at least t

from the falling edge of G, assum ing that

GLQV

AVQV-tGLQV

.

Standby Mode

The M27W101 has a standby mode which reduc-

es the supply current from 15mA to 15µA with low voltage operation V

≤ 3.6V, see Read Mode DC

CC

Characteristics table for details. The M27W101 is placed in the standby mode b y applying a CMOS high signal to the E

input. When in the standby mode, the outputs are in a h igh impedanc e state, independent of the G

input.

M27W101

Table 7. Read Mode DC Characteristics

(1)

(TA = –40 to 85°C; VCC = 2.7V to 3.6V; VPP = VCC)

Symbol Parameter Test Condition Min Max Unit

I

CC

I

CC1

I

CC2

I V

V

IH

V

Note: 1. VCC must be ap pl i e d simultan eously with or before VPP and removed simultane ously or aft er VPP.

Input Leakage Current

LI

Output Leakage Curren t

LO

Supply Current

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

Program Current

PP

Input Low Voltage –0.6

IL

(2)

Input High Voltage Output Low Voltage

OL

Output High Voltage TTL

OH

2. Maximum DC voltage on Ou tput is V

CC

+0.5 V.

I

OUT

0V ≤ V

E

≤ V

IN

CC

≤ V

OUT

= VIL, G = VIL,

= 0mA, f = 5MHz,

V

CC

E

= V

> VCC – 0.2V,

V

CC

V

PP

I

= 2.1mA

OL

I

= –400µA

OH

≤ 3.6V

IH

≤ 3.6V

= V

CC

±10 µA ±10 µA

15 mA

1mA

15 µA

10 µA

0.2 V

CC

0.7 V

CCVCC

2.4 V

+ 0.5

0.4 V

V V

Two Line Outp ut C ontrol

Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection.

The two line control function allows: a. the lowest possible memory power dissipation, b. comple te assuranc e that output bus contention

will not occur.

For the most efficient use of these two control lines, E ry device selecting function, while G

should be decoded and used as the prima-

should be made a common connectio n to all devices in the array and connected to the READ

line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

System Considerations

The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, I

, has three seg-

CC

ments that are of interest to the system designe r: the standby current level, the active current level, and transient current peaks that are p roduced by the falling and rising edges of E

. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling

capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between V

CC

and VSS. This should be a high frequency capac itor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between V

and VSS for every eight devic-

CC

es. The bulk capacitor sho uld be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

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