STMicroelectronics M27C64A Technical data

64 Kbit (8Kb x8) UV EPROM and OTP EPROM

■ 5V ± 10% SUPPLY VOLTAGE in READ

OPERATION

■ ACCESS TIME: 100ns

■ LOW POWER “CMOS” CONSUMPTION:

– Active Current 30mA – Standby Current 100µ A

■ PROGRAMMI NG VOLT AGE: 12.5V ± 0 .25V

■ HIGH SPEED PROGRAMMING

(less than 1 minute)

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 9Bh – Device Code: 08h

28

1

FDIP28W (F)

M27C64A

PLCC32 (K)

DESCRIPTION

The M27C64A is a 64K bit EPROM o ffered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large programs and is organized as 8,192 by 8 bits.

The FDIP28W (window ceramic frit-seal package) has transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.

For applications where the content is programmed only on time and erasure is not required, the M27C64A is offered in PLCC32 package.

Figure 1. Logic Diagram

V

CC

13

A0-A12

P

E

G

M27C64A

V

SS

V

PP

8

Q0-Q7

AI00834B

1/14October 2002

M27C64A

Figure 2A. DIP Connections

V

1

PP

2

A7

3 4

A6

5

A5 A4

6 7

A3 A2 A1

A0 Q0 Q1 Q2

V

SS

M27C64A

8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AI00835

V

CC

PA12 NC A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3

Figure 2B. Pin Connections

PP

V

A6 A5 A4 A3 A2 A1 A0

NC

Q0

A7

9

Q1

DU

A12

1

M27C64A

17

Q2

SS

DU

V

32

CC

V

Q3

P

Q4

NC

25

Q5

A8 A9 A11 NC G A10 E Q7 Q6

AI00836

Table 1. Signal Names

A0-A12 Address Inputs

Q0-Q7 Data Outputs E

G P

V

PP

V

CC

V

SS

NC Not Connected Internally

DU Don’t Use

Chip Enable

Output Enable Program

Program Supply

Supply Voltage

Ground

DEVICE OPERATION

The modes of operation of the M27C64A are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for V

and 12V on A9 for Electronic

PP

Signature.

Read Mode

The M27C64A ha s two control functions, both of which must be logically ac tive in order to obtain data at the output s. Chip Enable (E

) is the power control and should be used for device selection. Output Enable (G

) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (t

) is equal to the delay from E to output

AVQV

(t

). Data is available at the output after a delay

ELQV

of t E ble for at least t

from the falling edge of G, assuming that

GLQV

has been low and the addresses have been sta-

AVQV-tGLQV

.

2/14

M27C64A

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A Ambient Operating Temperature

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the rating "Operating Temperatur e Range", stresses abo ve those lis te d i n the Table " A bsolute Maximum Rati ngs" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operatin g sections of this s pecification is not i m plied. Ex posure to A bsolute Maximum Rating cond i tions for extended periods may a ffect device re liability. Refer also to the STMicroelectronics SU RE Program and other r elevant quality docum en ts .

2. Minimum DC vo ltage on Inpu t or Out put is – 0.5V w ith poss ible un dersh oot to –2. 0V fo r a peri od les s than 20ns. Ma ximum DC voltage on Output is V

3. Depends on range.

Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V

Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC +2V for a period l ess than 20ns.

CC

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E

Read Output Disable Program Verify Program Inhibit Standby Electronic Signature

Note: X = VIH or VIL, VID = 12V ± 0.5V.

G P A9

V

IL

V

IL

V

IL

V

IL

V

IH

V

IH

V

IL

V

IL

V

IH

X

V

IL

V

V V Pulse

IL

V

IH

X X X

IH

X XXX XXX

V

IL

V

IH

V

ID

V

PP

V

CC

V

CC

V

PP

V

PP

V

PP

V

CC

V

CC

Data Input

Data Output

Q70-Q0

Data Out

Hi-Z

Hi-Z Hi-Z

Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code Device Code

V

IL

V

IH

10011011 9Bh 00001000 08h

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M27C64A

Table 5. AC Measurement Conditions

Input Rise and Fall Times ≤ 20ns Input Pulse Voltages 0.4V to 2.4V Input and Output Timing Ref. Voltages 0.8 to 2.0V

Note that Output Hi-Z is defined as the point where data is no longer driven.

Figure 3. AC Testing Input Output Waveform

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only, not 100% tested.

Input Capacitance Output Capacitance

(1)

(TA = 25 °C, f = 1 MHz)

2.0V

0.8V

AI00826

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE UNDER

TEST

CL = 100pF

CL includes JIG capacitance

V

IN

OUT

= 0V

6pF

12 pF

OUT

AI00828

Standby Mode

The M27C64A has a standby mode which reduces the active current from 30mA to 100µA. The M27C64A is placed in the standby mode by applying a CMOS high signal to the E

input. When in the standby mode, the outputs are in a high impedance state, independent of the G

input.

Two Line Outp ut C on t rol

Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a. the lowest possible memory power dissipation, b. comple te assuranc e that output bus contention

will not occur.

For the most efficient use of these two control lines, E ry device selecting function, while G

should be decoded and used as the prima-

should be made a common connectio n to all devices in the array and connected to the READ

line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

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M27C64A

Table 7. Read Mode DC Characteristics

(1)

(TA = 0 to 70 °C or –40 to 85 °C: VCC = 5V ± 10%; VPP = VCC)

Symbol Parameter Test Condition Min Max Unit

I

LO

I

CC

I

CC1

I

CC2

I

PP

V

IH

V

Note: 1. VCC must be ap pl i ed simultaneously with or b ef ore VPP and removed s i m ul taneously or after VPP.

Input Leakage Current

LI

Output Leakage Curren t

Supply Current

0V ≤ V

E

= VIL, G = VIL,

I

= 0mA, f = 5MHz

OUT

Supply Current (Standby) TTL Supply Current (Standby) CMOS

E Program Current Input Low Voltage –0.3

IL

(2)

Input High Voltage 2 Output Low Voltage

OL

Output High Voltage TTL

OH

Output High Voltage CMOS

2. Maximu m DC voltage on Output is V

CC

+0.5 V .

I I

≤ V

IN

CC

≤ V

OUT

CC

E

= V

IH

> VCC – 0.2V

= V

V

PP

CC

I

= 2.1mA

OL

= –400µA

OH

= –100µA VCC– 0.7V

OH

±10 µA ±10 µA

30 mA

1mA 100 µA 100 µA

0.8

V

+ 1

CC

0.4 V

2.4 V

V V

System Considerations

The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, I

, has three seg-

CC

ments that are of interest to the system designe r: the standby current level, the active current level, and transient current peaks that are p roduced by the falling and rising edges of E

. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppres sed by comp lyi ng wit h the t wo lin e

output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between V

CC

and VSS. This should be a high frequency capac itor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between V

and VSS for every eight devic-

CC

es. The bulk capacitor sho uld b e locat ed near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

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