STMicroelectronics M27C1001 Technical data

1 Mbit (128Kb x8) UV EPROM and OTP EPROM

■ 5V ± 10% SUPPLY VOLTAGE in READ

OPERATION

■ ACCESS TIME: 35ns

■ LOW POWER CONSUMPTION:

– Active Current 30mA at 5Mhz – Standby Current 100µA

■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■ PROGRAMMING TIME: 10 0µs /w ord

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: 05h

M27C1001

32

1

FDIP32W (F) PDIP32 (B)

32

1

DESCRIPTION

The M27C1001 is a 1 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large programs and is organized as 131,072 words of 8 bits.

The FDIP32W (window ceramic frit-seal package) and the LCCC32W (leadless chip carrier package) have a transparent lids which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.

For applications where the content is programmed only one time and erasure is not required, the M27C1001 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages.

LCCC32W (L)

PLCC32 (C) TSOP32 (N)

Figure 1. Logic Diagram

V

CC

17

A0-A16

P

E

G

M27C1001

8 x 20 mm

V

PP

8

Q0-Q7

V

SS

AI00710B

1/17June 2002

M27C1001

Figure 2A. DIP Connections

V

1

PP

2

A15

3

A12

4 5

A7

6

A6

7

A5

8

A4 A3 A2 A1 A0

Q0

Q2 SS

M27C1001

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

AI00711

V

CC

PA16 NC A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5Q1 Q4 Q3V

Figure 2B. LCC Connections

A16

A7 A6 A5 A4 A3 A2 A1 A0

Q0

A12

9

Q1

VPPV

A15

1

32

M27C1001

17

Q2

Q3

SS

V

Q4

CC

P

Q5

NC

25

Q6

A14 A13 A8 A9 A11 G A10 E Q7

AI00712

Figure 2C. TSOP Connections

A11 G

A9

A8 A13 A14

NC

V

CC

V

PP

A16 A15 A12

A7

A6

A5

A4 A3

1

P

M27C1001

8

(Normal)

9

16 17

AI01151B

32

25 24

A10 E Q7 Q6 Q5 Q4 Q3 V

SS

Q2 Q1 Q0 A0 A1 A2

Table 1. Signal Names

A0-A16 Address Inputs

Q0-Q7 Data Outputs E

G

P V

PP

V

CC

V

SS

NC Not Connected Internally

Chip Enable

Output Enable

Program

Program Supply

Supply Voltage

Ground

2/17

M27C1001

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A Ambient Operating Temperature

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the ratin g " Operating Temperature Ran ge" , stresses above those listed in the Table "Absol ute Maxi m um Ratings " may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indi cated in the Operating sections of this s pecification is not impli ed. Exposure to Absolute M aximum Rating conditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroe lectronics SURE Program an d other relevan t quality docum en ts .

2. Minimum DC vo ltage on Inpu t or Out put is – 0.5V w ith poss ible un dersh oot to –2. 0V fo r a pe riod les s than 20ns. Ma ximum DC voltage on Output is V

3. Depends on range.

Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V

Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC +2V for a period l ess than 20n s.

CC

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E

Read Output Disable Program Verify Program Inhibit Standby Electronic Signature

Note: X = VIH or VIL, VID = 12V ± 0.5V.

G P A9

V

IL

V

IL

V

IL

V

IL

V

IH

V

IH

V

IL

V

IL

V

IH

V

IH

V

IL

XX XX

VIL Pulse

V

IH

X

X XXX XXX

V

IL

V

IH

V

ID

V

PP

V

or V

CC

SS

V

or V

CC

SS

V

PP

V

PP

V

PP

V

or V

CC

SS

V

CC

Q7-Q0

Data Out

Hi-Z

Data In

Data Out

Hi-Z Hi-Z

Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code Device Code

V

IL

V

IH

00100000 20h 00000101 05h

3/17

M27C1001

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only, not 100% tested.

Input Capacitance Output Capacitance

(1)

(TA = 25 °C, f = 1 MHz)

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE UNDER

TEST

CL

CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance

V

IN

OUT

= 0V

6pF

12 pF

OUT

AI01823B

DEVICE OPERATION

The operating modes of the M 27C1001 are list ed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for V

and 12V on A9 for Electronic

PP

Signature.

Read Mode

The M27C1001 has t wo control functions, both of which must be logically ac tive in order to obta in data at the output s. Chip Enable (E

) is the power control and should be used for device selection. Output Enable (G

) is the output control and should

be used to gate data to the output pins, indepen-

4/17

dent of device selection. Assuming that the addresses are stable, the address access time

) is equal to the delay from E to output

(t

AVQV

). Data is available at the output after a delay

(t

ELQV

of t E ble for at least t

from the falling edge of G, assuming that

GLQV

has been low and the addresses have been sta-

AVQV-tGLQV

.

Standby Mode

The M27C1001 has a standby mode which reduces the supply current from 30mA to 100µA. The M27C1001 is place d in the standby m ode by applying a CMOS high signal to the E

input. When in the standby mode, the outputs are in a high impedance state, independent of the G

input.

M27C1001

Table 7. Read Mode DC Characteristics

(1)

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

Symbol Parameter Test Condition Min Max Unit

I

LO

I

CC

I

CC1

I

CC2

I

PP

V

IH

V

Note: 1. VCC must be ap pl i e d simultaneously wi t h or before VPP and removed simultaneously or af ter VPP.

Table 8A. Read Mode AC Characteristics

Input Leakage Current

LI

Output Leakage Curren t Supply Current

0V ≤ V

E

= VIL, G = VIL,

I

= 0mA, f = 5MHz

OUT

Supply Current (Standby) TTL Supply Current (Standby) CMOS

E Program Current Input Low Voltage –0.3 0.8 V

IL

(2)

Input High Voltage 2 Output Low Voltage

OL

Output High Voltage TTL

OH

Output High Voltage CMOS

2. Maximu m DC voltage on Output is V

CC

+0.5 V .

(1)

I I

≤ V

IN

CC

≤ V

OUT

CC

E

= V

IH

> VCC – 0.2V

V

= V

PP

CC

I

= 2.1mA

OL

= –400µA

OH

= –100µA VCC – 0.7V

OH

2.4 V

±10 µA ±10 µA

30 mA

1mA

100 µA

10 µA

V

+ 1

CC

0.4 V

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

M27C1001

Symbol Alt Parameter Test Condition

Address Valid to

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

AXQX

Note: 1. VCC must be ap pl i e d simultaneously wi t h or before VPP and removed simultaneously or af ter VPP.

2. Sampled only, not 100% tested.

3. Speed obt ai ned with High Speed AC measurement conditions.

t

ACC

Output Valid Chip Enable Low to

t

CE

Output Valid Output Enable Low

t

OE

to Output Valid

(2)

Chip Enable High to

t

DF

Output Hi-Z Output Enable High

t

DF

to Output Hi-Z Address Transition

t

OH

to Output Transition

= VIL, G = V

E

= V

G

= V

E

= V

G

= V

E

= VIL, G = V

E

IL

-35

(3)

-45 -60 -70

Min Max Min Max Min Max Min Max

35 45 60 70 ns

25 25 30 35 ns

025025030030ns

0000ns

V

Unit

Two Line Outp ut C ontrol

Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a. the lowest possible memory power dissipation, b. comple te assuranc e that output bus contention

will not occur.

For the most efficient use of these two control lines, E ry device selecting function, while G

should be decoded and used as the prima-

should be made a common connectio n to all devices in the array and connected to the READ

line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

5/17

M27C1001

Table 8B. Read Mode AC Characteristics

(1)

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

M27C1001

Symbol Alt Parameter Test Condition

Min Max Min Max Min Max Min Max

Address Valid to

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

AXQX

Note: 1. VCC must be ap pl i e d simultaneously wi t h or before VPP and removed simultaneously or af ter VPP.

t

ACC

Output Valid Chip Enable Low to

t

CE

Output Valid Output Enable Low

t

OE

to Output Valid

(2)

2. Sampled only, not 100% tested.

Chip Enable High to

t

DF

Output Hi-Z Output Enable High

t

DF

to Output Hi-Z Address Transition

t

OH

to Output Transition

= VIL, G = V

E

= V

G

= V

E

= V

G

= V

E

= VIL, G = V

E

IL

80 90 100 120 ns

40 45 50 60 ns

030030030040ns

0000ns

Figure 5. Read Mode AC Waveforms

-12/-15/

-20/-25

Unit-80 -90 -10

A0-A16

E

G

Q0-Q7

VALID

tAVQV

tGLQV

tELQV

System Considerations

The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, I

, has three seg-

CC

ments that are of interest to the system designe r: the standby current level, the active current level, and transient current peaks that are p roduced by the falling and rising edges of E

. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by co m plyi ng with the two line

VALID

tAXQX

tEHQZ

tGHQZ

Hi-Z

AI00713B

output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between V

CC

and VSS. This should be a high frequency capac itor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between V

and VSS for every eight devic-

CC

es. The bulk capacitor sho uld be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

6/17