STMicroelectronics L9963E Datasheet

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L9963E

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L9963E

L9963E-TR

TQFP64EP

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L9963E

Datasheet

Automotive Multicell battery monitoring and balancing IC

Features

• AEC-Q100 qualified

• Measures 4 to 14 cells in series, with 0 μs desynchronization delay between samples. Supports also busbar connection without altering cell results

• Coulomb counter supporting pack overcurrent detection in both ignition on and off states. Fully synchronized current and voltage samples

• 16-bit voltage ADC with maximum error of ±2 mV in the [0.5 – 4.3] V range, after soldering, in [-40; +105] °C Tj range

• 2.66 Mbps isolated serial communication with regenerative buffer, supporting dual access ring. Less than 4 us latency between start of conversion of the 1st and the 31st device in a chain. Less than 4 ms to convert and read 96 cells in a system using 8 L9963E and L9963T transceiver. Less than 8 ms to convert and read 210 cells in a system using 15 L9963E and L9963T transceiver. Less than 16 ms to convert and read 434 cells in a system using 31 L9963E and L9963T transceiver. Supports both XFMR and CAP based isolation

• 200 mA passive internal balancing current for each cell in both normal and silent-balancing mode. Possibility of executing cyclic wake up measurements. Manual/Timed balancing, on multiple channels simultaneously; Internal/External balancing

• Fully redundant cell measurement path, with ADC Swap, for enhanced safety and limp home functionality

• Intelligent diagnostic routine providing automatic failure validation. Redundant fault notification through both SPI Global Status Word (GSW) and dedicated FAULT line

• Two 5 V regulators supporting external load connection with 25 mA (VCOM) and 50 mA (VTREF) current capability

• 9 GPIOs, with up to 7 analog inputs for NTC sensing

• Robust hot-plug performance. No Zeners needed in parallel to each cell

• Full ISO26262 compliant, ASIL-D systems ready

Application

• Automotive: 48 V and high-voltage battery packs

• Backup energy storage systems and UPS

• E-bikes, e-scooters

• Portable and semi-portable equipment

Description

The L9963E is a Li-ion battery monitoring and protecting chip for high-reliability automotive applications and energy storage systems. Up to 14 stacked battery cells can be monitored to meet the requirements of 48 V and higher voltage systems.

Each cell voltage is measured with high accuracy, as well as the current for the on-chip coulomb counting. The device can monitor up to 7 NTCs. The information is transmitted through SPI communication or isolated interface.

DS13636 - Rev 3 - April 2021 For further information contact your local STMicroelectronics sales office.

www.st.com

L9963E

Multiple L9963E can be connected in a daisy chain and communicate with one host processor via the transformer isolated interfaces, featuring high-speed, low EMI, long distance, and reliable data transmission.

Passive balancing with programmable channel selection is offered in both normal and low power mode (silent balance). The balancing can be terminated automatically based on internal timer interrupt. Nine GPIOs are integrated for external monitoring and controlling. The L9963E features a comprehensive set of fault detection and notification functions to meet the safety standard requirements.

DS13636 - Rev 3

page 2/184

1 Device introduction

The L9963E is intended for operation in both hybrid (HE) and full electric (FE) vehicles using lithium battery packs. The IC embeds all the features needed to perform battery management. A single device can monitor from 4 up to 14 cells. Several devices can be stacked in a vertical arrangement in order to monitor up to 31 battery packs for a total of 434 series cells.

The device can be supplied with the same battery it monitors, and generates stable internal references by means of a voltage regulator and a bootstrap. Both unit need to be surrounded by external components to be functional. It also features two internal bandgaps that are constantly monitored by internal circuitry to guarantee measurement precision. The microcontroller can also monitor the precision of the bandgap by reading the conversion of an internally generated voltage reference (VTREF).

L9963E main activity consists in monitoring cells and battery pack status through stack voltage measurement, cell voltage measurement, temperature measurement and coulomb counting. Measurement and diagnostic tasks can be executed either on demand or periodically, with a programmable cycle interval. Measurement data is available for an external microcontroller to perform charge balancing and to compute the State Of Health (SOH) and State Of Charge (SOC). In a typical use, the IC works in normal mode performing measurement conversions, diagnostics and communication; the device can also be put into a cyclic wake up state, in order to reduce the current consumption from the battery: while in this state, the main functions are activated periodically.

Passive cell balancing can be performed either via internal discharge path or via external MOSFETs. The controller can either manually control the balancing drivers or start a balancing task with a fixed duration. In the second case, the balancing may be programmed to continue also when the IC enters a low power mode called Silent Balancing, in order to avoiding unnecessary current absorption from the battery pack.

Thanks to the GPIOs, the device also offers the possibility to operate a distributed cell temperature sensing via external NTCs resistances. In general, the GPIOs can be used to perform both absolute and differential voltage conversions. They can also be configured as digital inputs/outputs. The IC supports up to 7 NTCs.

The external microcontroller can communicate with L9963E via SPI protocol, depending on the status of one pin at the startup (SPIEN pin). The physical layer can be either a classical 4-wire based SPI or a 2-wire, transformer/ capacitive based, isolated interface through a dedicated isolated transceiver device. L9963E, in fact, can be used as a transceiver, acting as a bridge between the two physical layers. In case of multiple L9963E vertically arrayed, each L9963E communicates with the others by means of a vertical isolated interface. The microcontroller can either address a single device of the chain or send broadcast commands.

L9963E has been engineered to perform automatic validation of any failure involving the cells or the whole battery pack. The device is able to detect the loss of the connection to a cell or GPIO terminal. Moreover it features an HardWare Self Check (HWSC) that verifies the correct functionality of the internal analog comparators and the ADCs. All these checks are automatically performed in case a failure involving both cells or the battery pack is detected, in order to provide always a reliable information to the external microcontroller. The current sensing interface used for coulomb counting is also capable of detecting failures such as open wires and overcurrent in sleep mode. Conversions for coulomb counting are validated by built in self-test of the precision and detecting any counter overflow. The cell balancing terminals can detect any short/open fault and the internal powerMOS are protected against overcurrent.

The stack voltage is monitored for OV/UV by three parallel and independent system. They have been engineered to protect the IC against AMR violation, to detect any overvoltage event as per LV 148 and to provide the possibility to trim the OV/UV levels according to the application and the total number of cells. Moreover, all internal voltage regulators are equipped with UV/OV detection circuitry, that is also self-validated upon failure detection via HWSC. Ground loss detection has also been implemented. In case of overtemperature, thermal shutdown protects the IC. GPIOs are capable of detecting ‘stuck @’ faults when used as digital outputs. Communication integrity is guaranteed by CRC check, while trimming and calibration data is continuously checked against corruption. Protocol errors such as incorrect address, inconsistent frame and communication interruption will be detected.

Critical failure modes will trigger the assertion of a dedicated FAULT line (implemented via two GPIOs), propagating through the L9963E chain via external optocouplers and reaching the microcontroller. L9963E can guarantee the FAULT line integrity via a heartbeat routine.

L9963E

Device introduction

DS13636 - Rev 3

page 3/184

Figure 1. Typical application

L9963E

VBAT

GNDREF

CGND DGND

AGND ISENSEp

ISENSEm

RSENSE

S2 B2_1

S1 C0

RLPF

RDIS

CLPF

CESD

CELL1

CELL2

C14

B4_3 C3

RLPF

RDIS

CLPF

CESD

CELL3

CELL4

B6_5

C5 S5

RLPF

RDIS

CLPF

CESD

CELL5

CELL6

S8 B8_7

C7 S7

RLPF

RDIS

CLPF

CESD

CELL7

CELL8

S10 B10_9

S9 C8

RLPF

RDIS

CLPF

CESD

CELL9

CELL10

S12

B12_11 C11

S11

C10

RLPF

RDIS

CLPF

CESD

CELL11

CELL12

S14

B14_13

C13 S13

C12

RLPF

RDIS

CLPF

CESD

CELL13

CELL14

RLPF

CESD

FR_BAT

BATT_MINUS

BATT_PLUS

CISENSE_1

VTREF

NPNDRV

VREG

CREG

CBAT_1

VCOM

CVCOM

VANA

CVANA

SPIEN

FAULTL

RFAULTL

RBAT_DOWNRFAULT_DOWN

FAULT_DOWN BAT_DOWN

DOPT

RBAT_UP

BATT_UP

FAULTH

CFLTH

RFLT

DZ_FLT

RFLT_PD

FAULT_UP

ISOHp

ISOHm

ISOLp_UP ISOLm_UP

ISOLp

ISOLm

ISOHp_DOWN

ISOHm_DOWN

RTERM

GPIO9

RNTC

RVTREF

CNTC

RGPIO

GPIO8

RNTC

RVTREF

CNTC

RGPIO

GPIO7

RNTC

RVTREF

CNTC

RGPIO

GPIO6

RNTC

RVTREF

CNTC

RGPIO

GPIO5

RNTC

RVTREF

CNTC

RGPIO

GPIO4

RNTC

RVTREF

CNTC

RGPIO

GPIO3

RNTC

RVTREF

CNTC

RGPIO

CAP1

CAP2

CBOOT

MREG

TRANSF

OPT

DZBAT

CVTREF

CESD

RISENSE

CESD

CBAT_2

CISENSE_2

CISENSE_3

CNPN

CBAT_3

AGND

DGND

GND_ESD

PACK_GND

L9963E

Device introduction

DS13636 - Rev 3

page 4/184

2 Block diagram and pin description

GADG1010180719PS

BOOTSTRAP

DGND

VBAT

CAP1

CAP2

c14

s14

b14_13

b12_11

c13

c11

c12

s13

s11

ISENSEp

ISENSEm

GNDREF

b2_1

VBAT

AGND CGND

GNDREF

CGND

AGND

DGND

GNDREF

DGND

AGND

CGND

NPNDRV

Ree

Digital Control & Data Register

VDIG

VANA

VCOM

ISO

SPI

GPIO

VTREF

CSA

DIAG

ADCs

VREG

VDIG

VANA

Bal CT

VANA

VCOM

VANA

VDIG

VTREF

VANA

VCOM

VTREF

SPIEN

GPIO9/SDO

GPIO8/SCK

GPIO7/WAKEUP

GPIO6

GPIO5

GPIO4 GPIO3

GPIO2/FAULTL

GPIO1/FAULTH

ISOHp

ISOHm

ISOLp/SDI

ISOLm/NCS

2.1 Block diagram

Figure 2. Block diagram

L9963E

Block diagram and pin description

DS13636 - Rev 3

page 5/184

2.2 Pin description

L9963E

Pin description

Figure 3. Pin connections (top view)

DS13636 - Rev 3

Pin #

1 GPIO8_ SCK

2 GPIO9_ SDO

3 ISOLp_SDI

4 ISOLm_NCS

Pin name Description

Table 1. Pin function

General-purpose I/O / Serial clock input (SPI). Its configuration is locked to Digital Input in case SPIEN = 1. Refer to Section 4.9 General purpose I/O:

GPIOs. Generally used to sense NTCs when not configured as SPI. Refer to Section 6.9 NTC analog front end.

General-purpose I/O / Serial data output (SPI). Its configuration is locked to Digital Output in case SPIEN = 1. Refer to Section 4.9 General purpose I/O:

GPIOs. Generally used to sense NTCs when not configured as SPI. Refer to Section 6.9 NTC analog front end.

Non-inverting, low-side isolated serial communication port (isolated SPI) / Serial data input (SPI). Its configuration is locked to Digital Input in case SPIEN = 1. Refer to

Section 4.2 Serial communication interface. When used as isolated SPI, refer to Section 6.8 ISO lines circuit.

Inverting, low-side isolated serial communication port (isolated SPI) / Active low, Chip-Select input (SPI). Its configuration is locked to Digital Input in case SPIEN =

1. Refer to Section 4.2 Serial communication interface. When used as isolated SPI, refer to Section 6.8 ISO lines circuit.

I/O type

DO/DI/AI

DI/AIO

page 6/184

(1)

L9963E

Pin description

Pin # Pin name Description

I/O type

Regulated power supply used for communication interfaces. Connect a tank

5 VCOM

capacitor as indicated in Table 73. Can be used to supply external loads with a maximum I

VCOM_ext

current budget.

6 CGND Communication ground. Connect to DGND on top. G

Non-inverting, high-side isolated serial communication port. Refer to

7 ISOHp

Section 4.2.3 Isolated Serial Peripheral Interface. Refer to Section 6.8 ISO lines

AIO

circuit.

Inverting, high-side isolated serial communication port. Refer to

8 ISOHm

Section 4.2.3 Isolated Serial Peripheral Interface. Refer to Section 6.8 ISO lines

AIO

circuit.

9 DGND Digital ground. Connect to AGND on top. G

10 GPIO1_ FAULTH Digital input used for FAULTH receiver. Refer to Section 4.3 FAULT line. DI

11 GPIO2_ FAULTL Digital output used for FAULTL transmitter. Refer to Section 4.3 FAULT line. DO

12 GPIO3

13 GPIO4 AI/DI/DO

14 GPIO5 AI/DI/DO

General-purpose I/O. Refer to Section 4.9 General purpose I/O: GPIOs. Generally used to sense NTCs. Refer to Section 6.9 NTC analog front end.

AI/DI/DO

15 GPIO6 AI/DI/DO

General-purpose I/O. Refer to Section 4.9 General purpose I/O: GPIOs. Generally

16 GPIO7_ WAKEUP

used to sense NTCs. Refer to Section 6.9 NTC analog front end. Can be

AI/DI/DO

configured to act as wake up input. Refer to Section 4.9.4 GPIO7: wake up feature.

17 NPNDRV

Internal voltage regulator controller output. Connect to the base of the external NPN transistor.

Regulated analog power supply for core circuitry. Connect a tank capacitor as

18 VREG

indicated in Table 73. It is disabled in low power modes (Silent Balancing, Sleep and during the OFF phase of Cyclic Wakeup). VCOM, VANA and VTREF regulators are fed by pre-regulated VREG.

19 VTREF

Buffered, precise analog reference voltage for driving multiple NTCs. Connect a tank capacitor as indicated in Table 73. It has a maximum IVTREF_ext current budget.

At first power up, after VCOM is out of undervoltage, this pin is sampled to

20 SPIEN

determine port L configuration. Connect to VCOM to configure SPI mode. Connect to AGND to select isolated SPI communication.

If left floating, this pin has a 100KΩ internal Pull down, forcing isolated SPI mode.

21 VANA Precise ADC analog supply. Connect a tank capacitor as indicated in Table 73. P

22 AGND Analog/ESD ground. Ground supply of chip. G

23 ISENSEp Non-inverting input of current measurement. Refer to Table 73. AI

24 ISENSEm Inverting input of current measurement. Refer to Table 73. AI

25 GNDREF Analog/reference GND. Connect to AGND on top G

26 C0 Connect to the negative terminal of 1st cell. AI

27 C1 Cell voltage input. Connect to the positive terminal of 1st cell. AI

28 S1 Cell balancing FET control output for 1st cell. AO

29 B2_1 Common terminal for cell balancing S1 and S2. AO

30 S2 Cell balancing FET control output for 2nd cell. AO

31 C2 Cell voltage input. Connect to the positive terminal of 2nd cell. AI

32 C3 Cell voltage input. Connect to the positive terminal of 3rd cell. AI

33 S3 Cell balancing FET control output for 3rd cell. AO

34 B4_3 Common terminal for cell balancing S3 and S4. AO

35 S4 Cell balancing FET control output for 4th cell. AO

(1)

DS13636 - Rev 3

page 7/184

L9963E

Pin description

Pin # Pin name Description

I/O type

36 C4 Cell voltage input. Connect to the positive terminal of 4th cell. AI

37 C5 Cell voltage input. Connect to the positive terminal of 5th cell. AI

38 S5 Cell balancing FET control output for 5th cell. AO

39 B6_5 Common terminal for cell balancing S5 and S6. AO

40 S6 Cell balancing FET control output for 6th cell. AO

41 C6 Cell voltage input. Connect to the positive terminal of 6th cell. AI

42 C7 Cell voltage input. Connect to the positive terminal of 7th cell. AI

43 S7 Cell balancing FET control output for 7th cell. AO

44 B8_7 Common terminal for cell balancing S7 and S8. AO

45 S8 Cell balancing FET control output for 8th cell. AO

46 C8 Cell voltage input. Connect to the positive terminal of 8th cell. AI

47 C9 Cell voltage input. Connect to the positive terminal of 9th cell. AI

48 S9 Cell balancing FET control output for 9th cell. AO

49 B10_9 Common terminal for cell balancing S9 and S10. AO

50 S10 Cell balancing FET control output for 10th cell. AO

51 C10 Cell voltage input. Connect to the positive terminal of 10th cell. AI

52 C11 Cell voltage input. Connect to the positive terminal of 11th cell. AI

53 S11 Cell balancing FET control output for 11th cell. AO

54 B12_11 Common terminal for cell balancing S11 and S12. AO

55 S12 Cell balancing FET control output for 12th cell. AO

56 C12 Cell voltage input. Connect to the positive terminal of 12th cell. AI

57 C13 Cell voltage input. Connect to the positive terminal of 13th cell. AI

58 S13 Cell balancing FET control output for 13th cell. AO

59 B14_13 Common terminal for cell balancing S13 and S14. AO

60 S14 Cell balancing FET control output for 14th cell. AO

61 C14 Cell voltage input. Connect to the positive terminal of 14th cell. AI

62 VBAT

Power supply of chip. This pin is also sensed by internal ADC through a voltage divider. Refer to Table 73.

63 CAP2 Pin2 external bootstrap capacitance. Refer to Table 73. AI

64 CAP1 Pin1 external bootstrap capacitance. Refer to Table 73. AI

- GNDEP Ground terminal, connect to AGND plane G

1. I/O type legend: AI = Analog Input; AO = Analog Output; AIO = Analog I/O; DI = Digital Input; DO = DigitalOutput; DIO = Digital I/O; P = Power; G = Ground; NC = Not Connect.

(1)

DS13636 - Rev 3

page 8/184

3 Product electrical ratings

3.1 Operating range

Within the operating range the part operates as specified and without parameter deviations. The device may not operate properly if maximum operating conditions are exceeded.

Once taken beyond the operative ratings and returned back within, the part will recover with no damage or degradation, unless the AMR are exceeded.

Additional supply voltage and temperature conditions are given separately at the beginning of each electrical specification table.

All voltages are related to the potential at substrate ground AGND, unless otherwise noted.

Symbol Parameter Test conditions Min. Typ. Max. Unit

VBAT Global

VBAT, VREG, VCOM, VTREF

C0 Global Lower Cell Terminal Voltage -0.3 0.3 V

B(n,n-1); Sn Global Cell Terminal Voltage 0 VBAT V

C(n) for n=1 to 9 Global Cell Terminal Voltage 0 VBAT – 4.5 V

C(n) for n=10 to 14 Global Cell Terminal Voltage 3 VBAT + 0.3 V

C(n)-C(n-1) for n=1 to 14 Cell Terminal Differential Voltage 0 4.7 V

S(n+1)-B(n+1,n); B(n+1,n)-S(n)

for n=1 to 13 odd

C(n)-S(n) for n=1 to 14 Cell Terminal Differential Voltage 0 4.7 V

VBAT – C(14)

ISOHP/M, ISOLP/M Global -0.3 VCOM V

GPIOn Local -0.3 VCOM V

SPIEN Local -0.3 VCOM V

VTREF Local 5 V

|ISENSEP – ISENSEM| Local

|ISENSEP + ISENSEM| / 2 Local

VCOM Local 5 V

VANA Local Info only 3.3 V

VREG Local 6.5 V

NPNDRV Local VREG-0.3 VREG + 1.5 V

CAP1 Local 0 VBAT V

CAP2 Local VREG VBAT + VREG V

L9963E

Product electrical ratings

Table 2. Operating ranges

Supply voltage 9.6 64 V

Transient operation, 40 ms pulse, repetitive as per VDA320 E48-02 test.

Supply voltage in case of transceiver use only (see

Section 6.12 Transceiver mode)

Cell Balance Terminal Differential Voltage

Battery / high Terminal Differential Voltage

CSA Input Differential Mode Range

CSA Input Common Mode Range (Referenced to GNDREF)

64 70 V

4.6 5 5.4 V

0 4.7 V

-0.3 61 V

-0.15 0.15 V

-0.225 0.225 V

DS13636 - Rev 3

page 9/184

3.1.1 Supply voltage ranges

AMR Violation

•Permanent damage

•Permanent parameter deviation

Critical UV

• Params may deviate

• Balance disabled

• Transceiver usage

Dyn UV

•No param deviation

•All functions guarante ed

Normal Op

•All functions guarantee d

Dyn OV

•Cell total error slightly increased

•All functions guarantee d

Critical OV

•Params may deviate

•All functions available

AMR Violation

•Permanent damage

•Permanent parameter deviation

VBAT

- 0.3 V

5.4 V

4.6 V

9.6 V

12 V

64 V

70 V

72 V

The device operates up to 14 cells of battery for hybrid and electric vehicles. The device can cover the voltage range of the main automotive Lithium batteries, up to a maximum of 4.6 V per cell in operating conditions. The IC has been engineered to sustain transient OV events as per LV 148

All operative ranges are listed in picture below.

If the stand by V3V3 regulator goes in POR, the device is put in reset.

Figure 4. Device operation in the VBAT supply voltage ranges

L9963E

Absolute maximum ratings

3.2

Absolute maximum ratings

Exceeding any Absolute Maximum Rating (AMR) may cause permanent damage to the integrated circuit.

All voltages are related to the potential at substrate ground AGND.

Table 3. Absolute Maximum Rating

Symbol Parameter Test conditions Min. Typ. Max. Unit

VBAT, C14 - -0.3 - 72 V

C0 - -0.3 - 0.3 V

C(n); B(n,n-1); Sn - -0.3 - 72 V

In this range, the device is not damaged, but leakage from

C(n)-C(n-1) for n=1 to 14 -

S(n+1)-B(n+1,n) B(n+1,n)-S(n)

for n=1 to 13 odd

C(n)-S(n) for n=1 to 14 - Vreg < 2 V -72 - 72 V

VBAT-C14 - -72 - 72 V

ISOHP/M, ISOLP/M - -0.3 - 6 V

GPIOn - -0.3 - 5.5 V

SPIEN - -0.3 - 12 V

VTREF - -0.3 - 6 V

pins may exceed I (see Table 39) if ADCs are

enabled; it doesn’t exceed if ADCs are disabled

In this range, the leakage from pins I

CELL_LEAK

(see Section 6.10.5 Busbar

connection) if ADCs are

enabled or disabled

- -0.3 -

CELL_LEAK

is guaranteed

-72 - 72 V

-6 - 6 V

BAL_CLAMP

DS13636 - Rev 3

page 10/184

Temperature ranges and thermal data

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISENSEP/M - -0.3 - 4.5 V

VCOM - -0.3 - 6 V

VANA - -0.3 - 4.5 V

VREG - -0.3 - 12 V

NPNDRV - -0.3 - 12 V

CAP1 - -0.3 - VBAT + 0.3V V

CAP2 - VREG – 0.3V - VBAT + 7V V

DGND, CGND - -0.3 - + 0.3 V

GNDREF shorted to AGND - -

Table 4. ESD protection

Item Parameter Test conditions Min. Typ. Max. Unit

All pins Except Isolated

Communication Terminals and

Global pins

Isolated Communication

Terminals

(1)(2)

(1)

and Global pins

HBM

(2)

versus all GND+EP connected

All pins except Corner Pins

Corner Pins -750 - 750 V

All pins -

(3)

CDM

Latch up

(4)

1. Tested per AEC-Q100-002.

2. Isolated Communication Terminals: ISOHP, ISOHM, ISOLP_SDI, ISOLM_NCS.

3. Tested per AEC-Q100-011.

4. Tested per AEC-Q100-004, Class-2, Level-A.

-2 - 2 kV

-4 - 4 kV

-500 - 500 V

-100 - 100 mA

L9963E

3.3

Pins are all GND connected together.

Temperature ranges and thermal data

Table 5. Temperature ranges and thermal data

Symbol Parameter Test conditions Min Max Unit

amb

stg

Thys

Thj-amb

1. In “2s2p”, the “s” suffix stands for “Signal” and the number before indicates how many PCB layers are dedicated to signal wires. The “p” suffix stands for “Power” and the number before indicates how many PCB layers are dedicated to power planes.

Operating and testing temperature (ECU environment) - -40 105 °C

Junction temperature for all parameters - -40 125 °C

Storage temperature - -65 150 °C

Thermal shut-down temperature (junction) - 175 200 °C

Temperature ADC accuracy - -10 +10 °C

Thermal shut-down temperature hysteresis - 5 15 °C

Thermal resistance junction-to-ambient

(1)

- 22 °C/W

DS13636 - Rev 3

page 11/184

3.4 Power management

All parameters are tested and guaranteed in the following conditions, unless otherwise noted:

9.6 V < VBAT < 64 V; -40 °C < Tambient < 105 °C

Symbol Parameter Test conditions Min. Typ. Max. Unit

BAT_NORM

in Normal Mode from VBAT pin

I Current in Normal Mode from

REG_NORM_CSEN1

Current in Normal Mode from

REG_NORM_CSEN0

Current in Normal Mode from

Supply Current in Normal Mode

supply current drawn from VREG

BAT_SLP

, Total Supply Current

BAT_NORM_ADC

, Total Supply

VBAT pin

, Total Supply

VREG MOS

, Total Supply

VREG MOS

REG_NORM_ADC_CSEN1

from VREG MOS

REG_NORM_ADC_CSEN0

from VREG MOS

REG_NORM_COMM

, Additional

for communication

, Supply Current in Sleep

Mode

BAT_SLP_BAL_CONF

BAT_BALANCE

, Total

Figure 5. Sketch of a 2s2p PCB with thermal vias

Table 6. Power Management

Normal state (refer to Section 4.1 Device

functional state); no load on VTREF; the chip

performs continuously data transmission via isolated communication interfaces to higher and lower sides

in a stack daisy chain.

Application info: IBAT is not affected by communication. Current needed for COM interfaces is drawn out of VREG regulator.

Normal state; No load on VTREF; no

communication; The chip performs continuously sampling and converting.

Normal state; No load on VTREF; no

communication; no ADC conversion; Curr sense. Enabled by coulombcounter_en = 1

Normal state; No load on VTREF; no

communication; no ADC conversion; Curr sense Disabled by coulombcounter_en = 0

Normal state; No load on VTREF; no communication; The chip performs continuously

sampling and converting. Curr sense Enabled by

coulombcounter_en = 1

Normal state; No load on VTREF; no communication; The chip performs continuously

sampling and converting. Curr sense Disabled by

coulombcounter_en = 0

Normal state; No load on VTREF; The chip performs continuously data transmission via isolated communication interfaces to higher and

lower sides in a stack daisy chain. (measured

with out_res_tx_isoh/l = 11, highest differential amplitude, highest consumption).

Lowest power state; Both internal oscillator and

external wakeup detection on.

Supply Current in Silent Balance Mode (enabled only regulators necessary to bias balance

preregulators, refer to Section 4.1 Device

functional state).

Delta current when the balancing of all 14 cells are

act ivated.

L9963E

Power management

1 2.5 mA

5.5 9 mA

21 mA

20 mA

38 mA

37 mA

8 10.8 13 mA

10 50 µA

1.2 2 2.8 mA

0.4 0.55 0.7 mA

DS13636 - Rev 3

page 12/184

Power management

Symbol Parameter Test conditions Min. Typ. Max. Unit

REG_GPIO_DIGOUT

Delta current from VREG pin needed to use 1 GPIO

as digital output.

0.4 0.8 1.2 mA

Average DC current consumption in application can be estimated according to the following equations:

Estimation of the average DC current consumption in application

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= 1  

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







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



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L9963E

(1)

DS13636 - Rev 3

page 13/184

4 Functional description

In the following paragraphs, the functionalities of the device are listed and described in detail.

4.1 Device functional state

L9963E

Functional description

Figure 6. Device functional states

4.1.1 Reset and Sleep states

Reset state: when stand-by logic is reset, all registers on device are reset.The battery voltage is still under

threshold.

From here, as soon as the PORN_STBY goes high the Stby Logic gets its supply power and the Sleep state is reached.

4.1.1.1 Operations in Reset state

No operation is possible in Reset state

Sleep state:

This state is reached:

• coming from Reset state on PORN_STBY rising

• from other states in case a Go2SLP cmd is sent by uP or no communication is received for t > t_SLEEP

• from Init State in case the device address is still 0b0000 after t > t_SHUT

• from Cyclic_Wup state once the Cyclic Wup job is done and a silent balancing is not to be resumed.

In this state the device is sensitive to External Sources in order to wake up the Main Logic. External sources are: ISO lines, Fault line, SPI_CS (SPI_CLK) pins, also a GPIO pin for “Master” units.

In this state a slow oscillator is working allowing the device to wake itself up every t = t

DS13636 - Rev 3

CYCLIC_WUP

and move to Cyclic Wup state.

CYCLIC_SLEEP

page 14/184

L9963E

Device functional state

During Sleep state, the current consumption is significantly reduced to I Communication wake up sources monitoring, low-speed oscillator for cyclic wake up timer, and the corresponding

reference and power supply are activated.

Different events can cause a wake up, depending on the configuration decided by the microcontroller:

• ISO COMM/ SPI SIGNAL: this wake-up during a regular SLEEP mode state moves the L9963 FSM to Init or Normal State. A proper signal will be detected as pre-wake up (simple edge readout), and later it must be followed by a wake-up signal that will be decoded by the L9963 which, in the meanwhile, has entered in a higher consumption mode (regulators turned ON, isolated RX/TX enabled). Any protocol frame recognized as electrically consistent will wake up the device. However, the command will not be interpreted and thus no execution takes place;

• INTERNAL COUNTER: it is possible that the microcontroller defines an automatic wake up of L9963 (when put in SLEEP mode) every T

state;

• GPIO SIGNAL: In case GPIO7 is configured as wake up source (GPIO7_WUP_EN = 1), a high logic level on it will wake up L9963;

• FAULT: in case a fault is detected in an upper L9963, a proper signal is communicated through the FAULT line. The receiver connected to GPIO1/FAULTH pin will detect the event and the device will be forced to evolve into the normal state, in order to transmit the fault downward.

The wake-up event coming from external wake up sources is verified by the stby logic (pattern confirmation step) before waking up the main logic (the main logic is kept under reset and its clock is gated off until the Sleep state is left).

The wakeup sequence lasts T

4.1.1.2 Operations in Sleep state

Only the Stand-by logic is working in Sleep state.

CYCLE_SLEEP

WAKEUP

current value: only the

SLEEP

, in order to perform the diagnostics in the CYCLIC WAKEUP

Wake up Management Always ON

Awakening Pattern Detection Once Comparison logic

4.1.2 Init state

In Init state, after having been woken up, the device waits for the uP to send the Address assignment command. Refer to Section 4.1.2.2 Addressing procedure.

If the address command is received before the Init timer expires (t_SHUT), the device address is stored into a stand-by logic register (chip_ID) and the device goes to Normal state.

The chip_ID field is then locked and no longer editable. Two actions can correctly re-initialize the device (including the chip_ID):

• Hard reset: (POR_STBY)

• Soft reset: it is recommended to set SW_RST and GO2SLP in the same frame

– Note that Soft reset will leave communication timeout (CommTimeout) unmodified

– Note that Soft reset will also clear the chip_ID

– If only SW_RST is sent, the device will wait for CommTimeout and then move to Sleep state

If the Init timer (t_SHUT) expires before the command is received, the device goes back to Sleep state.

All references are powered, interfaces are ready data transmission. The commands sent by the micro-controller can be read from both ISO lines and SPI pins. However, while in Init state, only the chip_ID, isotx_en_h and iso_freq_sel fields are writable. It is not possible to write/read other registers.

Any failure is masked until the device receives an address.

Table 7. Operations in Sleep state

Operation Timing mode Functions involved

Timers, Pin Input Buffer and ISO lines receiver ON. External sources activity detection, receivers and input buffers powered

DS13636 - Rev 3

page 15/184

4.1.2.1 Operations in Init state

Set X = 1

Send

BROADCAST

command

with

out_res_tx_is

o = XX ,

iso_freq_sel =

Send WRITE

command

with

chip_ID =

DEVICES

with

Farthest_Un

it = 1 (if not

in dual ring system, set

also

isotx_en_h

= 0 )

Send

BROADCAST

command

with

Lock_isoh_iso

freq = 1 to

lock the ISOH

port and ISO

frequency

configuration

Here below a list of operations the device can perform during Init State.

Operation Timing mode Functions involved

Communication Always ON SPI/isolated SPI Logic and storage

Init Timeout Always ON t_SHUT timer

4.1.2.2 Addressing procedure

The following algorithm describes the correct daisy-chain addressing procedure for a stack of N

Table 8. Operations in Init state

Figure 7. Daisy chain addressing algorithm

L9963E

Device functional state

DEVICES

Switching to high frequency (iso_freq_sel = 11) before initialization procedure has been completed is not recommended, since it might prevent other units from being initialized.

Once initialization procedure is done, it is possible to lock ISOH port status and ISO frequency configuration by setting Lock_isoh_isofreq = 1: the lock adds more safety against unwanted write access to iso_freq_sel and

isotx_en_h bit in DEV_GEN_CFG register.

4.1.3 Normal state

All references are powered, and the ADCs and interfaces are ready for measurement and data transmission respectively. The commands sent by the micro-controller can be read from both ISO lines and SPI pins.

On receiving a valid command, the L9963 executes the corresponding operations, such as voltage, current and over-temperature measurement.

Some core safety operations (e.g. OV, UV, OT, UV, and VBAT monitoring) are checked in the background automatically.

In case the communication with MCU is missing for t > t_SLEEP (programmable via CommTimeout, maskable via comm_timeout_dis) or a GO2SLP command is received, the device moves either to Sleep state or to Silent

Balancing state, depending on slp_bal_conf bit and balancing state.

DS13636 - Rev 3

page 16/184

A Soft RESET command received when in Normal state clears all registers except CommTimeout. The device is kept in Normal and doesn’t move to Reset state.

4.1.4 Power up sequence

Final Normal state is reached through a power up sequence, which involves the turn ON of all regulators. The following power up sequence is performed correctly if VBAT pin voltage lays in the operating range (refer to

Table 3):

• VREG is the first regulator to turn ON

• As soon as VREG reaches enough voltage dynamic (> 3V), also VANA regulator starts to turn ON

• When VANA regulator voltage reaches V T

VTREF_DELAY

• After T connected to VREG, CAP1 to GND)

• After T

Normally, the power up sequence lasts T back to a low power state (Sleep or Silent Balancing, depending on the previous state). The following timeouts

are implemented:

• timeout_VCOM_UP_first, valid only for the first power up

• timeout_VCOM_UP, valid for each wake up

• timeout_OSCI_MAIN, valid for each wake up

During power down:

• VCOM, VTREF and Bootstrap are turned off at the same time

• VREG is turned off after T

• When VREG falls below 4 V (typical value), VANA starts falling along with VREG.

expires, VTREF regulator is turned ON

BOOT_DELAY

VCOM_DELAY

Device functional state

VANA_UV

threshold and related digital filter time T

POR_FILT

in respect to VTREF enable, Bootstrap circuit is enabled in charge phase (CAP2

in respect to VTREF enable, VCOM regulator is turned ON

WAKEUP

VREG_OFF

. In case it lasts longer than a specific timeout, the device moves

L9963E

Figure 8. Power up Sequence

DS13636 - Rev 3

page 17/184

The device is still able to communicate if VTREF and Bootstrap power up fails: VCOM regulator is started anyway. It is not recommended to send any SPI frame to the device before T

L9963E is still performing the power up routine might be discarded.

4.1.5 Silent Balancing state

There is the possibility to perform the balancing of one (or more) cells with a reduced current consumption with respect to doing that in Normal mode: this state is called Silent Balancing.

In Silent_Bal the same resources as in Sleep state are active, in addition to the balance predrivers and the necessary bias circuitry.

To enter in Silent Balancing state from Normal state, the following conditions shall be verified:

1. Cell balancing must be ON

2. The slp_bal_conf flag shall be set to ‘1’

3. A “go to sleep” condition shall be verified (either an explicit GO2SLP command or communication timeout expiration)

If a cell balancing is previously demanded in Normal mode and the slp_bal_conf flag is set to 1, when a condition to go to sleep (low consumption) occurs the device enters Silent Balancing, not Sleep state and the required cell-balancing starts (or continues).

3 possible leaving ways from Silent Balancing mode:

• any wake up signal on communication or FAULT Line can force the chip to stop the balancing and then go back to the Normal state. Any protocol frame recognized as electrically consistent will wake up the device. However, the command will not be interpreted and thus no execution takes place.

• An external Fault must bring the device to Normal state and stop the balancing.

• As soon as the required balancing target is finished, the EOB (End of Balancing) bit is set to one and the chip enters the Sleep state.

• If the Cyclic signal is raised the device goes to Cyclic_Wup state, runs the diagnosis then it goes back to Silent Balancing (if slp_bal_conf flag = 1) where the balancing resumes

WAKEUP

L9963E

Device functional state

expires. Any incoming frame while

4.1.5.1 Operations in Silent Balancing state

Here below a list of operations the device can perform during Silent Balancing state.

Table 9. Opeations in Silent Balancing state

Operation Timing mode Functions involved

Balancing low power Always ON Balancing timer, Drivers ON, Balance short comparators

Wakeup management Always ON Wakeup logic and wakeup sources interfaces ON

4.1.6 Cyclic wake up state

From both Sleep and Silent Balancing states, the device moves periodically (once every t Cyclic_Wup state in order to perform a fault monitoring.

Diagnostic checks are done in this state as well as always-on monitorings. ADC must be ON to check possible critical battery conditions. Any detected fault moves the device to the Normal state.

An “On-demand” operation is only possible once the device has moved to Normal in case of any detected fault

Possible ways to leave this state:

• Any fault detected during this mode moves the device to the Normal state.

• A wake up from Fault line or Comm lines moves the device to the Normal state. Any protocol frame recognized as electrically consistent will wakeup the device. However, the command will not be interpreted and thus no execution takes place

• If the defined monitoring tasks are finished, the device can move to the SLEEP or SILENT BALANCING states automatically based on the state before Cyclic Conversions (slp_bal_conf flag).

CYCLIC_SLEEP

) to

4.1.6.1 Operations in Cyclic wake up state

Here below a list of operations the device can perform during Cyclic wake up state.

DS13636 - Rev 3

page 18/184

L9963E

Device functional state

Table 10. Operations in Cyclic Wakeup state

Operation Timing mode Functions involved

Battery fast OV/UV Always ON Threshold Comparator

Battery OV/UV Once ADCV measurements vs. threshold

Cells OV/UV Once ADCV measurements vs. threshold

GPIO OT/UT Once ADCV measurements vs. threshold

OC Monitor Always ON ADCC measurements vs. threshold

OT Monitor Always ON ADCT measurements vs. threshold

GPO Short Detection Always ON Logical Comparison

Clock Monitor Always ON Frequency comparison to secondaty monitor

Downward Fault Signalling Always Receivers and Transmitters

Cell Open Once ADCV measurements vs. threshold

Balancing Open Once Voltage Comparator, Timer

Wake up Management Always ON Wake up logic and wakeup sources interfaces ON

Cyclic operations have their own periods written by MCU in specific SPI registers.

In case the “On-demand” and “cyclic” timing modes are both possible, an “on-demand” command starts a single operation immediately, breaking the cyclic period, and resets the cyclic counter.

In GPIO short detection the detection is guaranteed only in the duty phase, if the pin is configured as an output.

4.1.7 Sleep parameters

All parameters are tested and guaranteed in the following conditions, unless otherwise noted:

9.6 V < VBAT < 64 V; -40 °C < Tambient < 105 °C

Symbol Parameter Test conditions Min. Typ. Max. Unit

GPIO7_WAKEUP

UV_SHORT_DELAY

WAKEUP

t_SHUT Tested by SCAN 60 s

t_SLEEP_00

t_SLEEP_01

t_SLEEP_10

t_SLEEP_11

CYCLIC_SLEEP_000

CYCLIC_SLEEP_001

CYCLIC_SLEEP_010

Table 11. Sleep parameters

GPIO7 deglitch filter when used as Wakeup Source

Delay after POR. Used to latch VCOM_UV and VTREF_UV

Time necessary to complete Wake up from SLEEP mode (between Wake up source and VCOM out of UV condition)

Communication Timeout

CommTimeout = 00

Communication Timeout

CommTimeout = 01

Communication Timeout

CommTimeout = 10

Communication Timeout

CommTimeout = 11

Tested by SCAN 150 μs

Tested by SCAN 40 μs

2 ms

Tested by SCAN 32 ms

Tested by SCAN 256 ms

Tested by SCAN 1024 ms

Tested by SCAN 2048 ms

Tested by SCAN 100 ms

Tested by SCAN 200 ms

Tested by SCAN 400 ms

DS13636 - Rev 3

page 19/184

L9963E

Serial communication interface

Symbol Parameter Test conditions Min. Typ. Max. Unit

CYCLIC_SLEEP_011

CYCLIC_SLEEP_100

CYCLIC_SLEEP_101

CYCLIC_SLEEP_110

CYCLIC_SLEEP_111

VREG_OFF

FMAIN_OSC_stby Internal standby Oscillator frequency 20 32 45 KHz

FAUX_OSC_stby Internal standby redundant Oscillator frequency 20 32 45 KHz

timeout_VCOM_UP_first

timeout_VCOM_UP

Timeout at first power up. From wakeup event to VCOM_UV release

Default power up timeout. From wakeup event to VCOM_UV release

timeout_OSCI_MAIN From wakeup event to main oscillator stable Tested by SCAN 10 ms

timeout_POR_MAIN VANA settling time timeout Tested by SCAN 1.5 ms

BOOT_DELAY

VTREF_DELAY

VCOM_DELAY

WAKEUP_TIMEOUT_ISO

WAKEUP_TIMEOUT_SPI

WAKEUP_NCS_HIGH

Delay between VTREF enable and Bootstrap enable

Delay between VANA_UV release (POR_STBY asserted after T

POR_FILT

) and VTREF enable

Delay between VTREF enable and VCOM enable

Timeout of the pulse counter for wakeup detection (isolated SPI)

Timeout of the pulse counter for wakeup detection (SPI)

Minimum NCS high time before sending SPI wake up frame

Tested by SCAN 800 ms

Tested by SCAN 1600 ms

Tested by SCAN 3200 ms

Tested by SCAN 6400 Ms

Tested by SCAN

1280

Tested by SCAN 500 μs

Tested by SCAN 8 ms

Tested by SCAN 4 ms

Tested by SCAN 200 μs

Tested by SCAN 630 μs

Tested by SCAN 400 μs

Tested by SCAN 282 μs

Tested by SCAN 84 138 μs

Tested by SCAN 400 μs

4.2 Serial communication interface

Two types of serial communication ports are included in L9963E: SPI and isolated interface:

• SPI can be used for the local communication between MCU and the closest L9963E

• Isolated SPI can be used for the global communication between several L9963E stacked in a daisy chain

Refer to Section 6.11 Communication architectures for all the different application scenarios.

The frequencies on the 2 communication interfaces are different and not related.

From micro-controller point of view a daisy chain of many L9963E devices is controlled as a single device addressable by using both the device ID and the device’s internal register addresses.

4.2.1 Communication interface selection

Two communication ports are available:

• Port H: implemented via the ISOHp and ISOHm pins. It always works as Isolated SPI interface. It can be enabled by setting isotx_en_h = 1

• Port L: implemented via the ISOLp_SDI, ISOLm_NCS, GPIO8_SCK, GPIO9_SDO pins. It is always enabled and its configuration is latched upon first powe up and depends on the SPIEN pin

DS13636 - Rev 3

page 20/184

L9963E

Serial communication interface

Table 12. Port L configuration determination

Electrical condition Latched when Configuration Wake up source

SPIEN = 1

SPIEN = 0 (default

condition if pin is left

floating)

Upon VCOM_UV release

In case the first power up fails and L9963E comes back to Sleep state without having latched the PORT L operating mode, both wake up sources will be kept active in order to allow subsequent power up trigger in both operating configurations.

When first power up completes successfully, only the wake up source related to the units with SPIEN = 1 are Master units of the daisy chain. A Master Unit differs from the Slave ones (SPIEN = 0) because:

• It manages the asynchronicity between SPI CLK and the programmable bit-rate on the isolated line;

• It exploits an internal buffer to store answers received from the slaves on ISOH port;

• It implements timeout mechanisms and frame error checks described in Section 4.2.4.4 Special frames;

• It forwards commands only if they are addressing Slave units. Any command addressed to the Master unit is not propagated on the ISOH port;

• In case Master Unit has port H disabled (isotx_en_h = 0), trying to communicate with a Slave unit will return the corresponding Master’s register content;

Interaction between Port H and Port L is managed by L9963E. The IC is capable of converting analog signals incoming on the isolated twisted pair to digital signals suitable for SPI, and viceversa. Passing a signal through a single unit takes a single pulse period (2*T

programmed operating frequency), which can be used to account for the insertion delay of an L9963E in the daisy chain.

Port L configured as SPI. Master Unit. SPIEN must be connected to VCOM

Port L configured as isolated SPI. Slave Unit. SPIEN must be connected to AGND

BIT_HIGH_LOW_FAST

or 2*T

BIT_HIGH_LOW_SLOW

SPI wake up logic

ISOL wake up

comparator

, depending on the

4.2.1.1 Wake up via communications interface

To wake up the device from low power modes, any communication frame in low frequency (F

ISO_SLOW

) can be

sent:

• If port L is configured in SPI mode, a sequence of at least 37 clock pulses on SCK line with active low chip select NCS will wake up the device. Pulses must be received within T

WAKEUP_TIMEOUT_SPI

timeout starting

from the NCS assertion. Before sending the wake up frame, NCS must have been set high for at least T

WAKEUP_NCS_HIGH.

• If port L is configured in isolated SPI mode, a sequence of at least 37 differential pulses on ISOLP/ISOLM pins, whose minimum duration is T

DET_MIN_WU

up the device. Pulses must be received within T

and whose amplitude is greater than Wakeup_thr will wake

WAKEUP_TIMEOUT_ISO

timeout starting from the first valid

pulse.

• If port H is enabled, a sequence of at least 37 differential pulses, whose minimum duration is T

DET_MIN_WU

and whose amplitude is greater than Wakeup_thr will wake up the device. Pulses must be received within T

WAKEUP_TIMEOUT_ISO

timeout starting from the first valid pulse.

Note: Depending on pulses re-synchronization uncertainty with the internal standby oscillator, the wake up event may

occur even if COM pulses are less than 37 (min. number of pulses in the best case is 8). However, 37 pulses will always guarantee a correct wake up.

In case first power up fails and SPIEN value is not correctly latched, port L will listen to both wake up sources, until a correct power up sequence is achieved and port L configuration is determined.

4.2.2 Serial Peripheral Interface (SPI)

The SPI pinout is listed in the following table:

DS13636 - Rev 3

Table 13. L9963E pin used as SPI

L9963E pin SPI function Configuration

ISOLp_SDI Serial Data Input (SDI) Digital input

page 21/184

L9963E pin SPI function Configuration

ISOLm_NCS Chip Select (CS) Digital input. Active low.

GPIO8_SCK Serial Clock (SCK) Digital input.

GPIO9_SDO Serial Data Out (SDO) Digital output

A 40-bit frame is used including a 7-bit CRC.

Refer to Section 4.2.4 SPI protocol details for further details about the protocol.

Table 14. SPI interface quick look

Parameter Description

Protocol Out of frame

Single Frame Length 40 bit

Addressable Devices 15

Frame protection 7 bit CRC

Max. Frequency 5 MHz

CPOL 0

CPHA 0

Master/Slave configuration MCU Master / L9963E Slave

L9963E

Serial communication interface

4.2.3 Isolated Serial Peripheral Interface

The Isolated SPI interface allows units with different ground levels and on different boards to communicate with each other. Physically the interface is based on twisted-pair wire with transformer isolators.

The isolated SPI pinout is listed in the following table:

Pin SPI Function Configuration

ISOLp_SDI Port L positive differential input/output Analog input/output

ISOLm_NCS Port L negative differential input/output Analog input/output

ISOHp Port H positive differential input/output Analog input/output

ISOHm Port H negative differential input/output Analog input/output

Table 15. Isolated SPI pinout

DS13636 - Rev 3

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Figure 9. Isolated SPI interface

L9963E

Serial communication interface

Table 16. Isolated SPI quick look

Parameter

Protocol Half-Duplex / Out of frame

Single Frame Length 40 bit

Addressable Devices 31

Frame protection 6 bit CRC

Max. Bit-rate

Master/Slave configuration L9963E Slave

2.66 Mbps (high speed configuration)

333 kbps (low speed configuration, default)

Description

The transmission line on the isolated SPI exploits a single twisted pair. Communication data is transmitted/ received over a pulse-shaped signal, in a half-duplex protocol.

Line bit-rate can be selected by programming the iso_freq_sel bit via SPI. A single bit is made of a pulse time (T

• T

) followed by two pause slices (2T

PULSE

= 2T

PULSE

BIT_HIGH_LOW_FAST

= 2T

BIT_HIGH_LOW_SLOW

).:

PULSE

for the high speed configuration

for the low speed configuration

Once the operating frequency has been programmed and the ISOH port has been enabled/disabled, it is possible to lock these settings by writing the Lock_isoh_isofreq bit to ‘1’, to avoid unwanted changes due to wrong MCU write frame.

Lock_isoh_isofreq is added to the reg map into a separate register in respect to isotx_en_h and iso_freq_sel, in order to avoid that a single frame can both unlock and write fields

Lock_isoh_isofreq bit (default 0) is reset every time the device goes to a low power mode. When Lock_isoh_isofreq is set to ‘1’, isotx_en_h and iso_freq_sel bits are write protected

Architecture and MCU command’s time constraints are specified taking into account signal propagation delay over the communication bus. Refer to Inter-frame delay for further details.

DS13636 - Rev 3

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Serial communication interface

Figure 10. Isolated SPI pulse shape and logical meaning

L9963E

4.2.3.1 ISO communicator receiver and transmitter

An isolated receiver and transmitter are connected to the couple of pins ISOLP/M and ISOHP/M. Depending on the communication phase, they can be enabled or disabled.

4.2.3.1.1 ISO communicator receiver

The receiver is able to convert a differential input signal into a single ended signal that is provided to the logic.

In order to guarantee a correct communication and guarantee Wake up via Communication Interface the input common mode must be included into range V

At power up by default the device is configured for a low frequency communication (F F

ISO_FAST

can be configured by acting on the iso_freq_sel bit.

4.2.3.1.2 ISO communicator transmitter

The transmitter is able to force as differential output the single ended signal that is provided by the logic.

Transmitter output impedance can be programmed via out_res_tx_iso (R

Table 18. It affects differential pulse amplitude. In order to guarantee a correct communication in case of high

frequency configuration the bit length must be at least T a single bit into a period T

BIT_LENGTH_FAST

In case of low frequency configuration T

must be T

BIT_LENGTH_SLOW

4.2.3.2 Dual access ring

L9963E supports dual access ring topology (refer to Section 6.11.3 Dual access ring for the application scenario). The device accepts commands from both ports (ISOL/SPI and ISOH ports) and generates answers in both directions.

This kind of functionality is present by default and can not be disabled.

In the typical application scenario featuring a number of N devices (referred to as bottom and top Masters), while the remaining are configured as isolated SPI slaves (refer

to Section 4.2.1 Communication interface selection for Master and Slave behavior).

Referring to Figure 51, the Section 4.1.2.2 Addressing procedure follows the standard approach, except for the top Master, that must be initialized through its own SPI interface.

Once the initialization is complete, MCU is able to communicate with any Slave through any of the 2 Masters SPI interface. It is also possible to verify the loop integrity, accessing one Master through the opposite one.

In case the access to a Slave is performed exploiting the bottom Master, the corresponding answer must be retrieved through the bottom Master itself (the same applies for the dual case of the top Master).

CM_ISO_IN

BIT_LENGTH_FAST

BIT_HIGH_LOW_FAST

and T

BIT_HIGH_LOW_SLOW

DEVICES

L9963E, two of them are configured as SPI

ISO_SLOW

DIFF_ISO_OUT1…3

); higher frequency

), as described in

and the duration of high and low level of .

are valid.

DS13636 - Rev 3

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4.2.3.3 Electrical parameters

4.2.3.3.1 Receiver

All parameters are tested and guaranteed in the following conditions, unless otherwise noted:

9.6 V < VBAT <64 V; -40 °C < Tambient < 105 °C

Symbol Parameter Test conditions Min. Typ. Max. Unit

DIFF_ISO_IN3

CM_ISO_IN

ISO_DIFF

ISO_EXT

ISO_LEAK

DET_MIN_WU

Wakeup_thr Wake up comparator threshold 80 200 320 mV

Differential input voltage threshold |V(ISOP) – V(ISOM)| 100 250 400 mV

Input voltage common mode range

Differential input resistance

External termination resistance connected between ISOxP and ISOxM pins

ISO input leakage current 0 V < ISOHP/M, ISOLP/M < VCOM 5 μA

Minimum pulse duration to be detected

Table 17. Isolated receiver electrical parameters

|V(ISOP) + V(ISOM)| /2

Design info

VIF enabled, no communication Resistance measured between ISOP and ISOM pins

Info only, not tested 120 Ω

Application info 400 ns

L9963E

Serial communication interface

0 1.9 V

5 15 kΩ

4.2.3.3.2 Transmitter

All parameters are tested and guaranteed in the following conditions, unless otherwise noted:

9.6 V < VBAT < 64 V; -40 °C < Tambient < 105 °C

Symbol Parameter Test conditions Min. Typ. Max. Unit

DIFF_ISO_OUT1

DIFF_ISO_OUT2

DIFF_ISO_OUT3

CM_ISO_OUT

BIT_HIGH_LOW_FAST

BIT_HIGH_LOW_SLOW

BIT_LENGTH_FAST

BIT_LENGTH_SLOW

ISO_FAST

Table 18. Isolated transmitter electrical parameters

measured with

pullup

Total output resistance: sum of pullup and pulldown resistance contribution

Output voltage common mode |V(ISOP) + V(ISOM)|/2 1 1.4 V

High/low level bit duration into a whole period in case of high frequency configuration

High/low level bit duration into a whole period in case of low frequency configuration

Bit duration with high frequency configured

Bit duration with low frequency configured

Isolated Communication Rate

V(ISOHL/MP) = 1.5 V

pulldown

measured with

310 440 570 Ω

V(ISOHL/MP) = 0.9 V (out_res_tx_iso = 00, default)

(out_res_tx_iso = 01) 220 314 410 Ω

(out_res_tx_iso = 11) 170 244 310 Ω

Application info

iso_freq_sel = 11

Application info

iso_freq_sel = 00

Guarantee by SCAN

iso_freq_sel = 11

Guarantee by SCAN

iso_freq_sel = 00

High frequency communication

Application info

62.5 ns

500 ns

375 ns

3 μs

2.66 Mbps

DS13636 - Rev 3

page 25/184

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISO_SLOW

ANSWER_DELAY_FAST

TANSWER_DELAY_SLOW

Isolated Communication Rate

Delay between receival of a command and generation of the answer

For terminals ISOHP/M, and ISOLP/M

iso_freq_sel = 11

Low frequency communication

Application info

For terminals ISOHP/M, and ISOLP/M

iso_freq_sel = 00

High speed mode Guarantee by SCAN

iso_freq_sel = 11

Low speed mode Guarantee by SCAN

iso_freq_sel = 00

L9963E

Serial communication interface

333.3 Kbps

4.5 μs

9 μs

DS13636 - Rev 3

page 26/184

4.2.4 SPI protocol details

The protocol is out-of-frame in order to manage the propagation delay of the commands sent by MCU and the answers generated by the L9963E stacked in the vertical interface. A command sent at the N-th frame will receive its feedback at the (N+1)th frame.

MCU can access the devices in different ways.

4.2.4.1 Single access

The single access behavior is based on a Write and Read approach.

The execution of each WRITE command sent by MCU can be immediately verified by interpreting the answer incoming from the addressed device. Any reply is buffered into L9963E Master unit, which passes it to the MCU on its next command.

L9963E

Serial communication interface

Figure 11. Out of frame protocol description

Table 19. SPI protocol: single access addressed frame (write and read)

393837363534333231302928272625

Dev ID Address

P.A.=1

P.A.=0

R/W

Dev ID Address feedback

Burst = 0

MOSI

MISO

Figure 12. Write and read access

24232221201918171615141312

GSW

DATA WRITE CRC

DATA READ CRC

987654321

DS13636 - Rev 3

READ commands require the same inter-frame time as the WRITE ones. Any reply is buffered into L9963E Master unit, which passes it to the MCU on its next command.

page 27/184

Figure 13. Single read access

Frame fields are described in the table below:

Table 20. Single access frames field description

L9963E

Serial communication interface

Field Length Value Description

P.A. 1 bit

R/W 1 bit

Dev ID 5 bit From 0x1 to 0x1F Identifies the x-th L9963E unit in a daisy chain

Address

feedback

GSW 2 bit From 0x0 to 0x3 Refer to Section 4.2.4.5 Global Status Word (GSW)

DATA WRITE 18 bit Depends on the register

CRC 6 bit From 0x00 to 0x3F

Burst 1 bit 0 Answer to a single access command

DATA READ 18 bit Depends on the register

0 Answer sent by any Slave unit (MISO)

1 Command sent by Master unit (MOSI)

0 Read

1 Write

7 bit From 0x00 to 0x5F Identifies the y-th register of the device

Data to be written in the y-th register of the x-th device. It is discarded in case of READ command.

CRC calculated on the [39-7] field of the frame. Refer to

Section 4.2.4.6 CRC calculation

Answer containing the data read from the y-th register of the y-th device

DS13636 - Rev 3

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4.2.4.2 Burst access

MOSI

Dummy Frames (all zeroes) Last MOSI

MISO

Burst Answer

NCS

SCK

MOSI

MISO

WAIT

The Burst Access supports only READ commands. It can be used to reduce the time needed to readout long data series from a single unit. The addressed unit receives the Burst command and starts replying the requested data frame by frame towards the MCU. Any reply is buffered into L9963E Master unit, which passes it to the MCU on its next command.

L9963E

Serial communication interface

Figure 14. Burst access

Table 21

describes the burst frame sequence.

• In case L9963E is configured in SPI mode, its internal buffer will store answers incoming from upper units. Apply the following strategy to download the burst data:

– First frame (sent with a single NCS window as a normal command)

◦ First MOSI contains the corresponding Burst command (see Table 23 for available commands)

◦ First MISO stores the answer to the previous MCU command, as per out-of-frame behavior

– Wait for burst answer to come back to the Master unit

◦ 400 μs (in case iso_freq_sel = 11)

◦ 3 ms (in case iso_freq_sel = 00)

– Intermediate frames (all downloaded keeping NCS low)

◦ Intermediate MOSI can be dummy commands (e.g. all zeroes). They are not interpreted by the

L9963E SPI logic

◦ Intermediate MISO contain burst data formatted as in Table 21

– Last frame (attached to intermediate frames, keeping NCS low)

◦ Last MOSI must be a valid command, because it will be interpreted by L9963E SPI logic

◦ Last MISO contains last burst data register (MISOn) as shown in Table 21

• In case L9963E transceiver is interposed between MCU and L9963E, refer to the L9963T datasheet. The Application Information section hosts a paragraph explaining how to handle burst commands.

Table 21. SPI protocol: answer to a burst read request

987654321

393837363534333231302928272625242322212019181716151413

DS13636 - Rev 3

MOSI

P.A.=1

P.A.=0

MISO1

P.A.=0

MISO2

Dev ID

R/W=0

Dev ID Command feedback

Burst = 1

Dev ID 1 1

Burst = 1

Command

Frame Num

GSW

(00010)

GSW

Unused (Any Data Is Possible) CRC

DATA READ CRC

page 29/184

L9963E

Serial communication interface

393837363534333231302928272625242322212019181716151413

Frame Num

(00011)

Frame Num

….

Frame Num

….

Frame Num

(10011)

GSW

P.A.=0

MISO3

P.A.=0

MISO4

P.A.=0

MISOn

P.A.=0

MISO20

Dev ID 1 1

Burst = 1

Dev ID 1 1

Burst = 1

Dev ID 1 1

Burst = 1

Dev ID 1 1

Burst = 1

Frame fields related to the burst access are described in the table below:

Table 22. Burst access special frame fields

121110

DATA READ CRC

987654321

Field

P.A. 1 bit

R/W 1 bit

Dev ID 5 bit From 0x1 to 0x1F Identifies the x-th L9963E unit in a daisy chain

Command

feedback

GSW 2 bit From 0x0 to 0x3 Refer to Section 4.2.4.5 Global Status Word (GSW)

CRC 6 bit From 0x00 to 0x3F

Burst 1 bit 1 Identifies the frame being part of a burst

DATA READ 18 bit

Frame Num 5 bit From 0x02 to 0x14

Length Value Description

0 Answer sent by any Slave unit (MISO)

1 Command sent by Master unit (MOSI)

0 Read

1 Write

7 bit From 0x78 to 0x7D Identifies a set of registers to be read out of the device

CRC calculated on the [39-7] field of the frame. Refer to

Section 4.2.4.6 CRC calculation

Depends on the register

Answer containing the data read from the y-th register of the y-th device

Identifies the n-th frame of a burst answer. In the first frame it is replaced by the Command feedback.

Several burst commands are available:

Table 23. Available burst commands

DS13636 - Rev 3

Command

code

0x78

Description Reference

All cells voltage, Sum of cells, Stack Voltage divider, Instantaneous Current, Balancing status. This command clears the measurement data_ready bit (refer to Section 4.4 Cell voltage

measurement)

Table 24

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