STMicroelectronics L6599AT, L6599ATD, L6599ATDTR User guide

L6599AT

Improved high-voltage resonant controller

Datasheet - production data

Applications

• LCD and PDP TV

• Desktop PC, entry-level server

• Telecom SMPS

• High efficiency industrial SMPS

SO16N

• AC-DC adapter, open frame SMPS

Features

•50% duty cycle, variable frequency control of resonant half bridge

•High-accuracy oscillator

•Up to 500 kHz operating frequency

•Two-level OCP: frequency-shift and latched shutdown

•Interface with PFC controller

•Latched disable input

•Burst mode operation at light load

•Input for power-ON/OFF sequencing or brownout protection

•Non-linear soft-start for monotonic output voltage rise

•600 V-rail compatible high-side gate driver with integrated bootstrap diode and high dv/dt immunity

•-300/700 mA high-side and low-side gate drivers with UVLO pull-down

•Guaranteed for extreme temperature ranges

Table 1. Device summary

	Order code	Package	Packaging
	L6599ATD	SO16N	Tube
	L6599ATDTR		Tape and reel
	March 2013	DocID15534 Rev 4	1/31

This is information on a product in full production.

www.st.com

Contents	L6599AT

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
2	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		4
3	Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
4	Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	4.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	4.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
6	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12

6.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 Current sense, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5 Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7 Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30

2/31	DocID15534 Rev 4

L6599AT	Description

1 Description

The L6599AT is an improved revision of the previous L6599A. It is a double-ended controller specific to series-resonant half bridge topology. It provides 50% complementary duty cycle: the high-side switch and the low-side switch are driven ON/OFF 180° out-of-phase for exactly the same time. Output voltage regulation is obtained by modulating the operating frequency. A fixed deadtime inserted between the turn-off of one switch and the turn-on of the other guarantees soft-switching and enables high-frequency operation.

To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage floating structure able to withstand more than 600 V with a synchronous-driven high-voltage DMOS that replaces the external fast-recovery bootstrap diode.

The IC enables the designer to set the operating frequency range of the converter by means of an externally programmable oscillator.

At startup, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. This frequency shift is non-linear to minimize output voltage overshoots; its duration is programmable as well.

At light load the IC may enter a controlled burst mode operation that keeps the converter input consumption to a minimum.

IC functions include a not-latched active-low disable input with current hysteresis useful for power sequencing or for brownout protection, a current sense input for OCP with frequency shift and delayed shutdown with automatic restart. A higher level OCP latches off the IC if the first-level protection is not sufficient to control the primary current. Their combination offers complete protection against overload and short-circuits. An additional latched disable input (DIS) allows easy implementation of OTP and/or OVP.

An interface with the PFC controller is provided that enables the pre-regulator to be switched off during fault conditions, such as OCP shutdown and DIS high, or during burst mode operation.

DocID15534 Rev 4

3/31

<![if ! IE]> <![endif]>4/31

<![if ! IE]> <![endif]>2

<![if ! IE]> <![endif]>Block

<![if ! IE]> <![endif]>Block

<![if ! IE]> <![endif]>diagram

9FF

+9

<![if ! IE]> <![endif]>diagram

',6

',6$%/(

9%227

64

',6

89

+9*

9

9

+9*

&%227

5

6<1&+521286

89/2

'(7(&7,21

'5,9(5

%227675',2'($3

67%<

89/2

287

<![if ! IE]> <![endif]>DocID15534

67$1'%<

/&.7$1

/(9(/

9

9 FF

&,5&8,7

<![if ! IE]> <![endif]>.1 Figure

'5,9,1*

6+,)7(5

,IPLQ

'($'

/2*,&

/9*'5,9(5

/9*

9

7,0(

5)PLQ

<![if ! IE]> <![endif]>4 Rev

<![if ! IE]> <![endif]>Block

,6(1B',6

46

*1'

9

5

89/2

&VV

,6(1

<![if ! IE]> <![endif]>diagram

&21752/

2&3

9

/2*,&

/,1(B2.

3)&B6723

9

&)

9

9&2

,6(1B',6

',6

$

67$1'%<

'(/$<

/,1(

<![if ! IE]> <![endif]>V-!

<![if ! IE]> <![endif]>L6599AT

L6599AT	Pin connection

3 Pin connection

Figure 2. Pin connection (top view)

#SS					6"//4
$%,!9
					(6'
#&
					/54
2&MIN
					. #
34"9					6CC
)3%.
					,6'
,).%
					'.$
$)3					0?34/0

!-V

			Table 2. Pin description
	Pin N#	Type	Function
			Soft-start. This pin connects an external capacitor to GND and a resistor to
			RFmin (pin 4) that set both the maximum oscillator frequency and the time
			constant for the frequency shift that occurs as the chip starts up (soft-start).
	1	Css	An internal switch discharges this capacitor every time the chip turns off
			(Vcc < UVLO, LINE < 1.24 V or > 6 V, DIS > 1.85 V, ISEN > 1.5 V, DELAY
			> 2 V) to make sure it is soft-started next, and when the voltage on the
			current sense pin (ISEN) exceeds 0.8 V, as long as it stays above 0.75 V.
			Delayed shutdown upon overcurrent. A capacitor and a resistor are
			connected from this pin to GND to set the maximum duration of an
			overcurrent condition before the IC stops switching and the delay after
			which the IC restarts switching. Every time the voltage on the ISEN pin
			exceeds 0.8 V, the capacitor is charged by an internal 150 µA current
	2	DELAY	generator and is slowly discharged by the external resistor. If the voltage
			on the pin reaches 2 V, the soft-start capacitor is completely discharged so
			that the switching frequency is pushed to its maximum value and the 150
			µA is kept always on. As the voltage on the pin exceeds 3.5 V the IC stops
			switching and the internal generator is turned off, so that the voltage on the
			pin decays because of the external resistor. The IC is soft-restarted as the
			voltage drops below 0.3 V. In this way, under short-circuit conditions, the
			converter works intermittently with very low input average power.
			Timing capacitor. A capacitor connected from this pin to GND is charged
	3	CF	and discharged by internal current generators programmed by the external
			network connected to pin 4 (RFmin) and determines the switching
			frequency of the converter.
			Minimum oscillator frequency setting. This pin provides a precise 2 V
			reference and a resistor connected from this pin to GND defines a current
			that is used to set the minimum oscillator frequency. To close the feedback
	4	RFmin	loop that regulates the converter output voltage by modulating the
			oscillator frequency, the phototransistor of an optocoupler is connected to
			this pin through a resistor. The value of this resistor sets the maximum
			operating frequency. An R-C series connected from this pin to GND sets
			frequency shift at startup to prevent excessive energy inrush (soft-start).

DocID15534 Rev 4

5/31

Pin connection			L6599AT
			Table 2. Pin description (continued)
	Pin N#	Type	Function
			Burst mode operation threshold. The pin senses some voltage related to
			the feedback control, which is compared to an internal reference (1.24 V).
			If the voltage on the pin is lower than the reference, the IC enters an idle
			state and its quiescent current is reduced. The chip restarts switching as
	5	STBY	the voltage exceeds the reference by 50 mV. Soft-start is not invoked. This
			function realizes burst mode operation when the load falls below a level
			that can be programmed by properly choosing the resistor connecting the
			optocoupler to pin RFmin (see block diagram). Tie the pin to RFmin if burst
			mode is not used.
			Current sense input. The pin senses the primary current though a sense
			resistor or a capacitive divider for lossless sensing. This input is not
			intended for a cycle-by-cycle control; therefore the voltage signal must be
			filtered to get average current information. As the voltage exceeds a 0.8 V
			threshold (with 50 mV hysteresis), the soft-start capacitor connected to pin
			1 is internally discharged: the frequency increases, so limiting the power
	6	ISEN	throughput. Under output short-circuit, this normally results in a nearly
			constant peak primary current. This condition is allowed for a maximum
			time set at pin 2. If the current keeps on building up despite this frequency
			increase, a second comparator referenced at 1.5 V latches the device off
			and brings its consumption almost to a “before startup” level. The
			information is latched and it is necessary to recycle the supply voltage of
			the IC to enable it to restart: the latch is removed as the voltage on the Vcc
			pin goes below the UVLO threshold. Tie the pin to GND if the function is
			not used.
			Line sensing input. The pin is to be connected to the high-voltage input bus
			with a resistor divider to perform either AC or DC (in systems with PFC)
			brownout protection. A voltage below 1.24 V shuts down (not latched) the
			IC, lowers its consumption and discharges the soft-start capacitor. IC
	7	LINE	operation is re-enabled (soft-started) as the voltage exceeds 1.24 V. The
			comparator is provided with current hysteresis: an internal 13 µA current
			generator is ON as long as the voltage applied at the pin is below 1.24 V
			and is OFF if this value is exceeded. Bypass the pin with a capacitor to
			GND to reduce noise pick-up. The voltage on the pin is top-limited by an
			internal Zener. Activating the Zener causes the IC to shut down (not
			latched). Bias the pin between 1.24 and 6 V if the function is not used.
			Latched device shutdown. Internally, the pin connects a comparator that,
			when the voltage on the pin exceeds 1.85 V, shuts the IC down and brings
	8	DIS	its consumption almost to a “before startup” level. The information is
			latched and it is necessary to recycle the supply voltage of the IC to enable
			it to restart: the latch is removed as the voltage on the VCC pin goes below
			the UVLO threshold. Tie the pin to GND if the function is not used.
			Open-drain ON/OFF control of PFC controller. This pin, normally open, is
			intended for stopping the PFC controller, for protection purposes or during
			burst mode operation. It goes low when the IC is shut down by DIS>1.85 V,
	9	PFC_STOP	ISEN > 1.5 V, LINE > 6 V and STBY < 1.24 V. The pin is pulled low also
			when the voltage on the DELAY exceeds 2 V and goes back open as the
			voltage falls below 0.3 V. During UVLO, it is open. Leave the pin
			unconnected if not used.

6/31	DocID15534 Rev 4

L6599AT			Pin connection
			Table 2. Pin description (continued)
	Pin N#	Type	Function
			Chip ground. Current return for both the low-side gate-drive current and
	10	GND	the bias current of the IC. All of the ground connections of the bias
			components should be tied to a track going to this pin and kept separate
			from any pulsed current return.
			Low-side gate-drive output. The driver is capable of 0.3 A min. source and
	11	LVG	0.7 A min. sink peak current to drive the lower MOSFET of the half bridge
			leg. The pin is actively pulled to GND during UVLO.
			Supply voltage of both the signal part of the IC and the low-side gate
	12	Vcc	driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND may be
			useful to get a clean bias voltage for the signal part of the IC.
			High-voltage spacer. The pin is not internally connected to isolate the high-
	13	N.C.	voltage pin and ease compliance with safety regulations (creepage
			distance) on the PCB.
			High-side gate-drive floating ground. Current return for the high-side gate-
	14	OUT	drive current. Layout carefully the connection of this pin to avoid too large
			spikes below ground.
			High-side floating gate-drive output. The driver is capable of 0.3 A min.
	15	HVG	source and 0.7 A min. sink peak current to drive the upper MOSFET of the
			half bridge leg. A resistor internally connected to pin 14 (OUT) ensures
			that the pin is not floating during UVLO.
			High-side gate-drive floating supply voltage. The bootstrap capacitor
	16	VBOOT	connected between this pin and pin 14 (OUT) is fed by an internal
			synchronous bootstrap diode driven in-phase with the low-side gate drive.
			This patented structure replaces the normally used external diode.

DocID15534 Rev 4

7/31

Electrical data	L6599AT

4 Electrical data

4.1Absolute maximum ratings

Table 3. Absolute maximum rating

	Symbol	Pin	Parameter	Value	Unit
	VBOOT	16	Floating supply voltage	-1 to 618	V
	HVG	15	HVG voltage	VOUT -0.3 to VBOOT +0.3	V
				-3 up to a value included
	VOUT	14	Floating ground voltage	in the range VBOOT -18	V
				and VBOOT
	dVOUT /dt	14	Floating ground max. slew rate	50	V/ns
	Vcc	12	IC supply voltage (Icc = 25 mA)	Self-limited	V
	LVG	11	LVG voltage	-0.3 to VCC +0.3	V
	VPFC_STOP	9	Maximum voltage (pin open)	-0.3 to Vcc	V
	IPFC_STOP	9	Maximum sink current (pin low)	Self-limited	A
	VLINEmax	7	Maximum pin voltage (Ipin ≤1 mA)	Self-limited	V
	IRFmin	4	Maximum source current	2	mA
	---	1 to 6, 8	Analog inputs and outputs	-0.3 to 5	V
	Ptot		Power dissipation @TA = 70 °C (DIP16)	1	W
			Power dissipation @TA = 50 °C (SO16)	0.83
	Tj		Junction temperature operating range	-40 to 150	°C
	Tstg		Storage temperature	-55 to 150	°C
Note:	ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 V.

4.2	Thermal data
		Table 4. Thermal data
	Symbol	Parameter	Value	Unit
	Rth(JA)	Max. thermal resistance junction-to-ambient (SO16)	120	°C/W

8/31	DocID15534 Rev 4

L6599AT	Electrical characteristics

5 Electrical characteristics

TJ = - 40 to 125 °C, Vcc = 15 V, VBOOT = 15 V, CHVG = CLVG = 1 nF; CF = 470 pF; RRFmin = 12 kΩ; unless otherwise specified.

Table 5. Electrical characteristics

Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
IC supply voltage
Vcc	Operating range	After device turn-on	8.85		16	V
VccOn	Turn-on threshold	Voltage rising	10	10.7	11.4	V
VccOff	Turn-off threshold	Voltage falling	7.45	8.15	8.85	V
Hys	Hysteresis			2.55		V
VZ	Vcc clamp voltage	Iclamp = 15 mA	16	17	17.9	V
Supply current
Istart-up	Startup current	Before device turn-on		200	250	µA
		Vcc = VccOn- 0.2 V
Iq	Quiescent current	Device on, VSTBY = 1 V		1.5	2	mA
Iop	Operating current	Device on, VSTBY = VRFmin		3.5	5	mA
Iq	Residual consumption	VDIS > 1.85 V or		300	400	µA
		VDELAY > 3.5 V or VLINE <
		1.24 V or VLINE = Vclamp
High-side floating gate-drive supply
ILKBOOT	VBOOT pin leakage current	VBOOT = 580 V			5	µA
ILKOUT	OUT pin leakage current	VOUT = 562 V			5	µA
RDS(on)	Synchronous bootstrap	VLVG = HIGH		150		Ω
	diode on-resistance
Overcurrent comparator
IISEN	Input bias current	VISEN = 0 to VISENdis			-1	µA
tLEB	Leading edge blanking	After VHVG and VLVG low-		250		ns
		to-high transition
V	Frequency shift threshold	Voltage rising (1)	0.76	0.8	0.84	V
ISENx
	Hysteresis	Voltage falling		50		mV
VISENdis	Latch-off threshold	Voltage rising (1)	1.44	1.5	1.56	V
td(H-L)	Delay to output			300	400	ns
Line sensing
Vth	Threshold voltage	Voltage rising or falling (1)	1.2	1.24	1.28	V
IHys	Current hysteresis	VLINE = 1.1 V	10	13	16	µA

DocID15534 Rev 4

9/31

Electrical characteristics								L6599AT
		Table 5. Electrical characteristics (continued)
	Symbol	Parameter		Test condition	Min.		Typ.	Max.	Unit
	Vclamp	Clamp level	ILINE = 1 mA		6			8	V
	Symbol	Parameter		Test condition	Min.		Typ.	Max.	Unit
	DIS function
	IDIS	Input bias current	VDIS = 0 to Vth					-1	µA
	Vth	Disable threshold	Voltage rising (1)		1.78		1.85	1.92	V
	Oscillator
	D	Output duty cycle	Both HVG and LVG		48		50	52	%
	fosc	Oscillation frequency			58.2		60	61.8	kHz
			RRFmin = 2.7 kΩ		240		250	260
	TD	Deadtime	Between HVG and LVG		0.2		0.3	0.4	µs
	VCFp	Peak value					3.9		V
	VCFv	Valley value					0.9		V
	VREF	Voltage reference at pin 4	(1)		1.93		2	2.07	V
			I	= -2 mA (1)	1.8		2	2.2
			REF
	KM	Current mirroring ratio					1		A/A
	PFC_STOP function
	Ileak	High level leakage current	VPFC_STOP = Vcc,					1	µA
			VDIS = 0 V
	RPFC_STOP	ON-state resistance	IPFC_STOP = 1 mA,				130	200	Ω
			VDIS = 1.5 V
	VL	Low saturation level	IPFC_STOP = 1 mA,					0.2	V
			VDIS = 1.5 V
	Soft-start function
	Ileak	Open-state current	V(Css) = 2 V					0.5	µA
	R	Discharge resistance	VISEN > VISENx				120		Ω
	Standby function
	IDIS	Input bias current	VDIS = 0 to Vth					-1	µA
	Vth	Disable threshold	Voltage falling (1)		1.2		1.24	1.28	V
	Hys	Hysteresis	Voltage rising				50		mV
	Delayed shutdown function
	Ileak	Open-state current	V(DELAY) = 0					0.5	µA
	ICHARGE	Charge current	VDELAY = 1 V,		100		150	200	µA
			VISEN = 0.85 V

10/31

DocID15534 Rev 4