L6258E
Fi
PWM CONTROLLED - HIGH CURRENT
DMOS UNIVERSAL MOTOR DRIVER
NOT FOR NEW DESIGN
1 FEATURES
■ ABLE TO DRIVE BOTH WINDINGS OF A
BIPOLAR STEPPER MOTOR OR TWO DC
MOTORS
■ OUTPUT CURRENT UP TO 1.2A EACH
WINDING
■ WIDE VOLTAGE RANGE: 12V TO 40V
■ FOUR QUADRANT CURRENT CONTROL,
IDEAL FOR MICROSTEPPING AND DC
MOTOR CONTROL
■ PRECISION PWM CONTROL
■ NO NEED FOR RECIRCULATION DIODES
■ TTL/CMOS COMPATIBLE INPUTS
■ CROSS CONDUCTION PROTECTION
■ THERMAL SHUTDOW
2 DESCRIPTION
L6258E is a dual full bridge for mot or control appl ications realized in BCD technology, with the capability
of driving both windings of a bipolar s tepper motor or
bidirectionally control two DC motors.
L6258E and a few external components form a com-
Figure 2. Block Diagram
INPUT
&
SENSE
AMP
INPUT
&
SENSE
AMP
EA_IN1 EA_OUT1VCP2
THERMAL
EA_IN2 EA_OUT2GND
PROT.
VDD(5V)
VCP1
VREF1
PH_1
VREF1
PH_2
TRI_CAP
C
FREF
I3_1
I2_1
I1_1
I0_1
I3_2
I2_2
I1_2
I0_2
C
CHARGE
PUMP
DAC
VR GEN
DAC
TRIANGLE
GENERATOR
P
VR (VDD/2)
TRI_0
TRI_180
gure 1. Package
PowerSO36
Table 1. Order Codes
Part Number Package
L6258E
PowerSO36
(Replaced by L6258EX)
plete control and drive circuit. It has high efficiency
phase shift chopping that allows a very low current
ripple at the lowest current contr ol lev els , and ma kes
this device ideal for steppers as well as for DC motors.The power stage is a dual DMOS full bridge capable of sustaining up to 40V, and includes the
diodes for current recirculation.The o utput current capability is 1.2A per winding in continuous mode, with
peak start-up current up to 1.5A. A thermal protectio n
circuitry disables the outputs if the chip temperature
exceeds the safe limits.
R
1M
1
C
C1
R
C1
TRI_0
+
C
TRI_180
C2
TRI_0
TRI_180
-
+
C
-
+
C
-
+
C
-
ERROR
V
R
AMP
+
-
ERROR
V
R
AMP
+
-
R
C2
C
R
1M
2
VS
POWER
BRIDGE
C
1
POWER
BRIDGE
2
BOOT
VBOOT
D96IN430D
OUT1A
OUT1B
SENSE1B
SENSE1A
DISABLE
VS
OUT2A
OUT2B
SENSE2B
SENSE2A
R
s
R
s
September 2004
Rev. 7
1/24
L6258E
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
V
V
DD
V
ref1/Vref2
I
O
I
O
V
V
boot
V
boot
T
T
stg
in
Supply Voltage 45 V
s
Logic Supply Voltage 7 V
Reference Voltage 2.5 V
Output Current (peak) 1.5 A
Output Current (continuous) 1.2 A
Logic Input Voltage Range -0.3 to 7 V
Bootstrap Supply 60 V
- VsMaximum Vgate applicable 15 V
Junction Temperature 150 °C
j
Storage Temperature Range -55 to 150 °C
Figure 3. Pin Connection (Top view)
PWR_GND
PH_1
I1_1
I0_1
OUT1A
DISABLE
TRI_CAP
V
GND
VCP1
VCP2
VBOOT
OUT2A
I0_2
I1_2
PH_2
PWR_GND
VS
1
2
3
4
5
6
7
DD
8
9
10
11
12
13 24
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
23
22
21
20
19
PWR_GND
SENSE1
OUT1B
I3_1
I2_1
VS
EA_OUT1
EA_IN1
VREF1
SIG_GND
VREF2
EA_IN2
EA_OUT2
I2_2
I3_2
OUT2B
SENSE2
PWR_GND
2/24
D96IN432E
Table 3. Pins Function
Pin # Name Description
1, 36 PWR_GND Ground connection (1). They also conduct heat from die to printed circuit copper.
2, 17 PH_1, PH_2 These TTL compatible logic inputs set the direction of current flow through the load. A
3I
4I
1_1
0_1
5 OUT1A Bridge output connection (1)
6 DISABLE Disables the bridges for additional safety during switching. When not connected the
7 TRI_cap Triangular wa v e gen er ati on ci rc uit ca pac ito r. The value of thi s ca paci tor def ine s th e ou tput
8V
(5V) Supply Voltage Input for logic circuitry
DD
9 GND Power Ground connection of the internal charge pump circuit
10 V
11 V
12 V
13, 31 V
CP1
CP2
BOOT
S
14 OUT2A Bridge output connection (2)
15 I
16 I
0_2
1_2
18, 19 PWR_GND Ground connection. They also conduct heat from die to printed circuit copper
20, 35 SENSE2,
SENSE1
21 OUT2B Bridge output connection and positive input of the tranconductance (2)
22 I
23 I
3_2
2_2
24 EA_OUT_2 Error amplifier output (2)
25 EA_IN_2 Negative input of error amplifier (2)
26, 28 V
REF2
, V
27 SIG_GND Signal ground connection
29 EA_IN_1 Negative input of error amplifier (1)
30 EA_OUT_1 Error amplifier output (1)
32 I
33 I
2_1
3_1
34 OUT1B Bridge output connection and positive input of the tranconductance (1)
Note: The number in parenthesis shows the relevant Power Bridge of the circuit. Pins 18, 19, 1 and 36 are connected together.
high level causes current to flow from OUTPUT A to OUTPUT B.
Logic input of the internal DAC (1). The output voltage of the DAC is a percentage of the
Vref voltage applied according to the thruth table of page 7
See pin 3
bridges are enabled
switching frequency
Charge pump oscillator output
Input for external charge pump capacitor
Overvoltage input for driving of the upper DMOS
Supply voltage input for output stage. They are shorted intern ally
Logic input of the internal DAC (2). The output voltage of the DAC is a percentage of the
VRef voltage applied accordin g to the tr uth table of page 7
See pin 15
Negative input of the transconductance input amplifier (2, 1)
See pin 15
See pin 15
Reference voltages for the internal DACs, determining the output current value. Output
REF1
current also depends on the logic inputs of the DAC and on the sensing resistor value
See pin 3
See pin 3
L6258E
3/24
L6258E
Figure 4. Thermal Characteristics
Conditions
pad layout + ground layers + 16 via hol
PCB ref.: 4 LAYER cm 12 x 12
pad layout + ground layers
PCB ref.: 4 LAYER cm 12 x 12
pad layout + 6cm2 on board heat sink
PCB ref.: 2 LAYER cm 12 x 12
12
10
8
20˚C/W
6
4
Power Dissipated (W)
2
Power Dissipated
(W)
5.3 70 15
4.0 70 20
2.3 70 35
15˚C/W
35˚C/W
T Ambient
(˚C)
Thermal J-A resistance
(˚C/W)
D02IN1370
4/24
0
0
20 40 60 80 100 120 140 160
Ambient Temperature (˚C)
D02IN1371
L6258E
Table 4. Electrical Characteristics (VS = 40V; VDD = 5V; Tj = 25°; unless otherwise specif ied .)
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
Supply Voltage 12 40 V
S
V
V
BOOT
V
Sense
V
S(off)
V
DD(off)
I
S(on)
I
S(off)
I
∆T
T
f
TRANSISTORS
I
DSS
R
ds(on)
CONTROL LOGIC
V
V
I
V
ref1/ref2
I
FI =
V
ref/Vsense
V
V
offset
SENSE AMPLIFIER
V
I
ERROR AMPLIFIER
G
SR Output Slew Rate Open Loop 0.2 V/µs
GBW Gain Bandwidth Product 400 kHz
Note 1: This is true for all the logic inputs except the disable input.
(*) Chopping frequency is twice fosc value.
Logic Supply Voltage 4.75 5.25 V
DD
Storage Voltage VS = 12 to 40V VS+6 VS+12 V
Max Drop Across Sense Resistor 1.25 V
Power off Reset Off Threshold 6 7.2 V
Power off Reset Off Threshold 3.3 4.1 V
VS Quiescent Current Both bridges ON, No Load 15 mA
VS Quiescent Current Both bridges OFF 7 mA
VDD Operative Current 15 mA
DD
Shut Down Hysteresis 25 °C
SD-H
Thermal shutdown 150 °C
SD
Triangular Oscillator Frequency
osc
(*)CFREF
= 1nF 12.5 15 18.5 KHz
Leakage Current OFF State 500 µA
On Resistance ON State 0.6 0.75 Ω
Flywheel diode Voltage If =1.0A 1 1.4 V
V
f
lnput Voltage All Inputs 2 V
in(H)
Input Voltage All Inputs 0 0.8 V
in(L)
Input Current (Note 1) 0 < Vin < 5V -150 +10 µA
I
in
Disable Pin Input Current -10 +150 µA
dis
Reference Voltage operating 0 2.5 V
V
ref
Terminal Input Current V
ref
= 1.25 -2 5 µA
ref
PWM Loop Transfer Ratio 2
DAC Full Scale Precision V
FS
Current Loop Offset V
= 2.5V I0/I1/I2/I3 = L 1.23 1.34 V
ref
= 2.5V I0/I1/I2/I3 = H -30 +30 mV
ref
DAC Factor Ratio Normalized @ Full scale Value -2 +2 %
lnput Common Mode Voltage
cm
-0.7 VS+0.7 V
Range
Input Bias sense1/sense2 -200 0 µA
inp
Open Loop Voltage Gain 70 dB
V
DD
V
5/24
L6258E
3 FUNCTIONAL DESCRIPTION
The circuit is intended to drive both windings of a bipolar stepper motor or two DC motors.
The current control is generated through a switch mode regulation.
With this system the direct ion and the ampl itud e of the load current are depending on the r el ation of phas e and
duty cycle between the two outputs of the current control loop.
The L6258E power stage is composed by power DMOS in bridge confi guration as it is shown in figure 5, wher e
the bridge outputs OUT_A and OUT_B are driven to V
driven to ground with a low level at the same inputs .
The zero current condition is obtained by driving the two half bridge us ing si gnals I N_A and IN_B with the same
phase and 50% of duty cycle.
In this case the outputs of the two half bridges are continuously switched between power supply (V
ground, but keeping the differential voltage across the load equal to zero.
In figure 5A is shown the timing diagram of the two outputs and the load current for this working condition.
Following we consider positive the current flowing into the load with a direction from OUT_A to OUT_B, while
we consider negative the current flowing into load with a direction from OUT_B to OUT_A.
Now just increasing the duty cycle of the IN_A signal and decreasi ng the duty c ycle of IN_B s ignal we driv e pos-
itive current into the load.
In this way the two outputs are not in phase, and the current can flow into the load trough the diagonal bridge
formed by T1 and T4 when the output OUT_A is driven to V
there will be a current r eci rculati on into the higher side of the bri dge, th rough T1 an d T2, when both the outputs
are at Vs and a current recir culation int o the l ower si de of the br idge, through T3 and T4, when both the outputs
are connected to ground.
Since the voltage applied to the load for r ecirculation is low, the res ulting current discharge time cons tant is higher than the current charging time cons tant dur ing the per iod in whi ch th e cur rent fl ows i nto the l oad thr ough th e
diagonal bridge formed by T1 and T4. In this way the load current will be positive with an average amplitude
depending on the difference in duty cycle of the two driving signals.
In figure 5B is shown the timing diagram in the case of positive load current
On the contrary, if we want to drive negative curr ent into the load is necessary to decrease the du ty cycle of th e
IN_A signal and increase the duty cycle of the IN_B signal. In this way we obtain a phase shift between the two
outputs such to have current flowing into the diagonal bridge formed by T2 and T3 when the output OUT_A is
driven to ground and output OUT_B is driven to V s, while we wi ll hav e the sam e current recirculati on condit ions
of the previous case when both the outputs are driven to Vs or to ground.
So, in this case the load current will be negativ e with an average ampl itude always depending by th e difference
in duty cycle of the two driving signals.
In figure 5C is shown the timing diagram in the case of negative load current .
Figure 6 shows the device block diagram of the complete current control loop.
with an high level a t the inpu ts IN_A and IN_B whi le ar e
s
) and
s
and the output OUT_B is driven to ground, while
s
3.1 Reference Voltage
The voltage applied to VREF pi n i s t he r efer ence for the i nternal DAC and, together with the sen se res istor val ue, defines the maximum current into the motor winding according to the following relation:
V
1
-----
--------------
⋅==
FI
REF
R
S
where R
6/24
= sense resistor value
s
I
MAX
0.5 V
⋅
REF
-------------------------- -
R
S
Figure 5. Power Bridge Configuration
L6258E
V
S
OUTA
OUTB
Iload
OUTA
IN_A IN_B
0
T1
OUT_A OUT_B
T3
LOAD
T2
T4
Fig. 1A
OUTB
Iload
OUTA
OUTB
Iload
Fig. 1B
0
Fig. 1C
0
D97IN624
7/24
L6258E
Figure 6. Current Control Loop Block Diagram
VREF
PH
INPUT TRANSCONDUCTANCE
I0
I1
I2
I3
DAC
VDAC
AMPL.
ia
+
-
Gin=1/Ra
ERROR AMPL.
V
R
+
ic
Rc
Cc
ib
VSENSE
+
Gs=1/Rb
SENSE TRANSCONDUCTANCE
AMPL.
Tri_0
Tri_180
-
+
-
+
POWER AMPL.
VS
VS
OUTA
OUTB
D97IN625
LOAD
R
L
L
L
R
S
3.2 Input Logic (I
- I1 - I2 - I3)
0
The current level in the motor winding is selected according to this table:
Table 5.
I3 I2 I1 I0
HHHH No Current
HHHL 9.5
HHLH 19.1
HHLL 28.6
HLHH 38.1
HLHL 47.6
HLLH 55.6
HLLL 63.5
LHHH 71.4
LHHL 77.8
LHLH 82.5
LHLL 88.9
LLHH 92.1
LLHL 95.2
LLLH 98.4
LLLL 100
Current level
% of IMAX
8/24
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