DMOS DUAL FULL BRIDGE DRIVER
■
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
■ 2.8A OUTPUT PEAK CURRENT (1.4A DC)
■ R
■ OPERATING FREQUENCY UP TO 100KHz
■ NON DISSIPATIVE OVERCURRENT
PROTECTION
■
PARALLE LED OPERATION
■ CROSS CONDUCTION PROTECTION
■ THERMAL SHUTDOWN
■ UNDER VOLTAGE LOCKOUT
■
INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS
■ BIPOLAR STEPPER MOTOR
■ DUAL OR QUAD DC MOTOR
DESCRIPTION
The L6225 is a DMOS Dual Full Bridge designed for
motor control applications, realized in MultiPower-
0.73Ω TYP. VALUE @ Tj = 25 °C
DS(ON)
L6225
PowerDIP20
(16+2+2)
BCD technology, which combines isolated DMOS
Power Transistors with CMOS and bipolar c ir cuits on
the same chip. Available in PowerDIP20 (16+2+2),
PowerSO20 and SO20(16+2+2) packages, the
L6225 features a non-dissipative protection of the
high side PowerMOSFETs and thermal shutdown.
PowerSO20
ORDERING NUMBERS:
L6225N (PowerDIP 20)
L6225PD (PowerSO20)
L6225D (SO20)
SO20
(16+2+2)
BLOCK DIAGRAM
VBOOT
VCP
EN
IN1
IN2
EN
IN1
IN2
A
A
A
B
B
B
V
BOOT
CHARGE
PUMP
VOLTAGE
REGULA TOR
OCD
THERMAL
PROTECTION
10V
5V
OCD
VS
V
BOOT
OVER
A
B
CURRENT
DETECTION
GA TE
LOGIC
OVER
CURRENT
DETECTION
GA TE
LOGIC
10V 10V
V
BOOT
BRIDGE A
BRIDGE B
A
OUT1
OUT2
SENSE
V
S
B
OUT1
OUT2
SENSE
A
A
A
B
B
B
September 2003
D99IN1091A
1/20
L6225
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Test conditions Value Unit
V
S
V
OD
V
BOOT
V
IN,VEN
V
SENSEA,
V
SENSEB
I
S(peak)
Supply Voltage
Differential Voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSE
Bootstrap Peak Voltage
Input and Enable Voltage Range -0.3 to +7 V
Voltage Range at pins SENSEA
and SENSE
B
Pulsed Supply Current (for each
pin), internally limited by the
V
S
VSA =
VSB = V
VSA =
VSB = VS = 60V;
V
SENSEA
B
VSA =
VSB = V
= V
S
SENSEB
S
= GND
60 V
60 V
VS + 10 V
-1 to +4 V
VSA =
t
PULSE
VSB = VS;
< 1ms
3.55 A
overcurrent protection
I
S
, T
T
stg
RMS Supply Current (for each
pin)
V
S
Storage and Operating
OP
VSA =
VSB = V
S
1.4 A
-40 to 150 °C
Temperature Range
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Test Conditions MIN MAX Unit
V
V
OD
V
SENSEA,
V
SENSEB
I
OUT
T
f
sw
Supply Voltage
S
Differential Voltage Between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSE
Voltage Range at pins SENSEA
and SENSE
B
VSA =
VSA =
V
SENSEA
B
(pulsed tW < trr)
(DC)
VSB = V
VSB = VS;
= V
SENSEB
S
852V
-6
-1
RMS Output Current 1.4 A
Operating Junction Temperature -25 +125 °C
j
Switching Frequency 100 KHz
52 V
6
1
V
V
2/20
L6225
THERMA L D ATA
Symbol Description PowerDIP20 SO20 PowerSO20 Unit
R
th-j-pins
R
th-j-case
R
th-j-amb1
R
th-j-amb1
R
th-j-amb1
R
th-j-amb2
(1) Mounted on a multi-layer FR4 PCB with a dissipati ng copper surface on the bottom side of 6cm2 (with a thickness of 35µm).
(2) Mounted on a multi-layer FR4 PCB with a dissipati ng copper surface on the top side of 6cm2 (with a thic kness of 35µm ).
(3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm), 16 via holes
and a groun d l ayer.
(4) Mounted on a multi-layer FR4 PCB without any hea t s i nking surfac e on the board.
PIN CONNECTIONS (Top View)
MaximumThermal Resistance Junction-Pins 13 15 - °C/W
Maximum Thermal Resistance Junction-Case - - 2 °C/W
MaximumThermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
MaximumThermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
1
2
3
4
41 52 - °C/W
--36°C/W
--16°C/W
57 78 63 °C/W
IN1
IN2
SENSE
OUT1
GND GND
GND
OUT1
SENSE
IN1
IN2
1
A
2
A
3
A
4
A
5
6
7
B
8
B
9
B
10
B
D99IN1093A
20
19
18
17
16
14
13
12
11
EN
A
VCP
OUT2
VS
A
GND15
VS
B
OUT2
VBOOT
EN
B
GND GND
VS
A
OUT2
VCP
EN
IN1
IN2
B
SENSE
OUT1
GND
PowerDIP20/SO20
(5) The slug is internally connected to pins 1,10,11 and 20 (GND pins).
1
A
A
2
3
4
A
A
A
A
A
5
6
7
8
9
D99IN1092A
PowerSO20
(5)
20
19
18
17
16
15
14
13
12
11
VS
B
OUT2
VBOOT
EN
B
IN2
B
IN1
B
SENSE
OUT1
GND10
B
B
B
3/20
L6225
PIN DESCRIPTION
PACKA GE
SO20/
PowerDIP20
PowerSO20
Name Type Function
PIN # PIN #
1 6 IN1
2 7 IN2
3 8 SENSE
A
A
Logic Input Bridge A Logic Input 1.
Logic Input Bridge A Logic Input 2.
Power Supply Bridge A Source Pin. This pin must be connected to Power
A
Ground directly or through a sensing power resistor.
4 9 OUT1
5, 6, 15, 16 1, 10, 11,
20
GND GND Signal Ground terminals. In PowerDIP and SO packages,
Power Output Bridge A Output 1.
A
these pins are also used for heat dissipation toward the
PCB.
7 12 OUT1
8 13 SENSE
Power Output Bridge B Output 1.
B
Power Supply Bridge B Source Pin. This pin must be connected to Power
B
Ground directly or through a sensing power resistor.
9 14 IN1
10 15 IN2
11 16 EN
B
B
B
Logic Input Bridge B Logic Input 1.
Logic Input Bridge B Logic Input 2.
(6)
Logic Input
Bridge B Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge B. This pin is also connected to the
collector of the Overcurrent and Thermal Protection
transistor to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
12 17 VBOOT Supply
Voltage
13 18 OUT2
14 19 VS
Power Output Bridge B Output 2.
B
Power Supply Bridge B Power Supply Voltage. It must be connected to
B
Bootstrap Voltage needed for driving the upper
PowerMOSFETs of both Bridge A and Bridge B.
the supply voltage together with pin VS
17 2 VS
Power Supply Bridge A Power Supply Voltage. It must be connected to
A
the supply voltage together with pin VS
18 3 OUT2
Power Output Bridge A Output 2.
A
19 4 VCP Output Charge Pump Oscillator Output.
20 5 EN
A
Logic Input
(6)
Bridge A Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge A. This pin is also connected to the
collector of the Overcurrent and Thermal Protection
transistor to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
.
A
.
B
(6) Also connect ed at the output dra i n o f the Overcurren t and Thermal prot ection MOSF E T . Therefore, it has to be driven putting in series a
resistor with a value in the range of 2.2kΩ - 180K Ω , recommend e d 100kΩ
4/20
L6225
ELECTRICAL CHARACTERISTICS
(T
= 25 °C, Vs = 48V, unless otherwise specified)
amb
Symbol Parameter Test Conditions Min Typ Max Unit
V
Sth(ON)
V
Sth(OFF)
T
j(OFF)
Turn-on Threshold 5.8 6.3 6.8 V
Turn-off Threshold 5 5.5 6 V
I
Quiescent Supply Current All Bridges OFF;
S
Thermal Shutdown Temperature 165 °C
Output DMOS Transistors
R
DS(ON)
High-Side + Low-Side Switch ON
Resistance
I
DSS
Leakage Current EN = Low; OUT = V
Source Drain Diodes
V
Forward ON Voltage ISD = 1.4A, EN = LOW 1.15 1.3 V
SD
t
Reverse Recovery Time If = 1.4A 300 ns
rr
Forward Recovery Time 200 ns
t
fr
Logic Input
V
Low level logic input voltage -0.3 0.8 V
IL
= -25°C to 125°C
T
j
(7)
Tj = 25 °C 1.47 1.69 Ω
510mA
=125 °C
T
j
(7)
S
2.35 2.70 Ω
2mA
EN = Low; OUT = GND -0.3 mA
V
V
th(ON)
V
th(OFF)
V
th(HYS)
High level logic input voltage 2 7 V
IH
I
Low Level Logic Input Current GND Logic Input Voltage -10 µA
IL
I
High Level Logic Input Current 7V Logic Input Voltage 10 µA
IH
Turn-on Input Threshold 1.8 2.0 V
Turn-off Input Threshold 0.8 1.3 V
Input Threshold Hysteresis 0.25 0.5 V
Switching Characteristics
t
D(on)EN
t
D(on)IN
t
RISE
t
D(off)EN
t
D(off)IN
t
FALL
Enable to out turn ON delay time
Input to out turn ON delay time I
Output rise time
Enable to out turn OFF delay time
Input to out turn OFF delay time
Output Fall Time
(8)
(8)
(8)
I
=1.4A, Resistive Load 500 800 ns
LOAD
=1.4A, Resistive Load
LOAD
(dead time included)
I
=1.4A, Resistive Load 40 250 ns
LOAD
(8)
I
=1.4A, Resistive Load 500 800 1000 ns
LOAD
I
=1.4A, Resistive Load 500 800 1000 ns
LOAD
I
=1.4A, Resistive Load 40 250 ns
LOAD
1.9 µs
5/20
L6225
ELECTRICAL CHARACTERISTICS (continued)
(T
= 25 °C, Vs = 48V, unless otherwise specified)
amb
Symbol Parameter Test Conditions Min Typ Max Unit
t
Dead Time Protection 0.5 1 µs
dt
f
CP
Charge pump frequency
-25°C<Tj <125°C 0.6 1 MHz
Over Current Protection
I
SOVER
R
OPDR
t
OCD(ON)
t
OCD(OFF)
(7) Tested at 25°C in a restricted range and guaranteed by characterization.
(8) See Fig. 1.
(9) See Fig. 2.
Input Supply Overcurrent
Protection Threshold
= -25°C to 125°C
T
j
Open Drain ON Resistance I = 4mA 40 60 Ω
OCD Turn-on Delay Time (9) I = 4mA; CEN < 100pF 200 ns
OCD Turn-off Delay Time (9) I = 4mA; CEN < 100pF 100 ns
Figure 1. Switching Characteristic Definition
EN
V
th(ON)
V
th(OFF)
I
OUT
(7)
2 2.8 3.55 A
t
6/20
90%
10%
D01IN1316
t
D(OFF)EN
t
FALL
t
D(ON)EN
t
RISE
t
Figure 2. Ove rcurrent Detect i on Timi ng Definition
I
OUT
I
SOVER
ON
BRIDGE
OFF
V
EN
90%
10%
L6225
t
OCD(ON)
t
OCD(OFF)
D02IN1399
7/20
L6225
9
0
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6225 integrates two independent Power MOS
Full Bridges. Each Power MOS has an Rdson=0.73ohm (typical value @25°C), with intrinsic
fast freewheeling diode. Cross conduction protection
is achieved using a dead time (td = 1
tween the switch off and swi tch on of two P ower MOS
in one leg of a bridge.
Using N Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above
the power supply voltage. The Bootstrapped (Vboot)
supply is obtained through an internal Oscillator and
few external components to realize a charge pump
circuit as shown in Figure 3. The oscillator output
(VCP) is a square wave at 600kHz (typical) with 10V
amplitude. Recommended values/part numbers for
the charge pump circuit are shown in Table1.
Table 1. Charge Pump External Components
Values
C
BOOT
C
P
R
P
D1 1N4148
D2 1N4148
220nF
10nF
100Ω
Figure 3. Char ge Pump Circu it
D1
R
C
VCP VBOOT VS
C
D2
P
P
BOOT
VS
A
LOGIC INPUTS
Pins IN1A, IN2A, IN1B and IN2B are TTL/CMOS and
µ
C compatible logic inputs. The internal structure is
shown in Fig. 4. Typical value for tur n-on and turn- off
thresholds are respectively Vthon=1.8V and
Vthoff=1.3V.
Pins EN
and ENB have identical input structure w ith
A
the exception that the drains of the Overcurrent and
thermal protection MOSFETs (one for the Bridge A
and one for the Bridge B) are also c onnected to these
pins. Due to these connections some care needs to
be taken in driving these pins. The EN
puts may be driven in one of two configurations as
shown in figures 5 or 6. If driven by an open drain
B
µ
s typical) be-
V
S
D01IN1328
and ENB in-
A
(collector) structure, a pull-up resistor R
pacitor C
are connected as shown in Fig. 5. If the
EN
and a ca-
EN
driver is a standard Push-Pull structure the resistor
R
and the capacitor CEN are connected as shown
EN
in Fig. 6. The resistor R
Ω
range from 2.2k
for R
and CEN are respectively 100KΩ and 5.6nF.
EN
to 180KΩ. Recommended values
should be chosen in the
EN
More information on selecting the values is found in
the Overcurrent Protection section.
Figure 4. Logi c Inp ut s I nte rn a l St ructure
5V
ESD
PROTECTION
D01IN1329
Figure 5. EN
and ENB Pins Open Collector
A
Driving
5V
5V
D02IN134
5V
D02IN135
OPEN
COLLECTOR
OUTPUT
Figure 6. EN
PUSH-PULL
OUTPUT
R
EN
ENA or EN
B
C
EN
and ENB Pins Push-Pull Driving
A
R
EN
ENA or EN
B
C
EN
TRUTH TABLE
INPUTS OUTPUTS
EN IN1 IN2 OUT1 OUT2
L X X High Z High Z
H L L GND GND
H H L Vs GND
HLHGNDVs
HHHVsVs
X = Don't care
High Z = High Impedance Output
8/20
L6225
NON-DISSIPATIVE OVERCURRENT PROTECTION
The L6225 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short
circuit to ground or between two phases of the bridge. With this internal over c urrent detection, the external cur rent sense resistor normally used and its assoc iated power dissipation ar e elimi nated. Figure 7 shows a sim plified schematic of the overcurrent detection circuit.
To implement the over current detection, a sensing element that deli ver s a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference current I
OCD comparator signals a fault condi tion. When a fault condition is detec ted, the EN pin is pulled belo w the turn
off threshold (1.3V typical) by an internal open drain MOS with a pull down capability of 4mA. By using an external R-C on the EN pin, the off time before recovering normal operation can be easily programmed by means
of the accurate thresholds of the logic inputs.
Figure 7. Overcurrent Protection Simplified Schematic
. When the output current in one bridge reaches the detection threshold (typically 2.8A) the relative
REF
OUT2
VS
OUT1
µC or LOGIC
+5V
RENEN
C
EN
A
TO GATE
R
DS(ON)
40Ω TYP.
LOGIC
INTERNAL
OPEN-DRAIN
POWER SENSE
1 cell
OCD
COMPARATOR
A
I
POWER DMOS
n cells
I
/ n
1A
(I1A+I2A) / n
I
REF
OVER TEMPERATURE
1A I2A
A
+
A
POWER DMOS
n cells
I
/ n
2A
HIGH SIDE DMOSs OF
THE BRIDGE A
POWER SENSE
1 cell
D02IN1353
Figure 8 sho ws th e O v erc urrent D et ec t io n o pe ration. T he D i sa bl e T im e t
DISABLE
before r e co ve ring norm al op er a tion can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by
C
and REN values and its magnitude is reported in Figure 9. The Delay Time t
EN
when an overcurrent has been detected depends only by C
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
C
EN
value. Its magnitude is re ported in Fi gure 10.
EN
before t urnin g off th e bridge
DELAY
EN
should be chosen as big as possi ble acc or ding to the maximum tolerable D elay Time and th e REN value should
be chosen according to the desired Disable Time.
The resistor R
should be chosen in the range from 2.2KΩ to 180KΩ. Recommended values for REN and C
EN
EN
are respectively 100KΩ and 5.6nF that allow obtaining 200µs Disable Time.
9/20
L6225
Figure 8. Overcurrent Protection Wavefor ms
I
OUT
I
SOVER
V
EN
V
DD
V
th(ON)
V
th(OFF)
ON
OCD
OFF
V
EN(LOW)
ON
BRIDGE
OFF
t
OCD(ON)
t
DELAY
t
EN(FALL)
t
D(OFF)EN
t
OCD(OFF)
t
DISABLE
t
EN(RISE)
t
D(ON)EN
D02IN1400
10/20
L6225
Figure 9. t
Figure 10. t
DISABLE
DELAY
vers u s CEN and R
3
3
1.10
1.10
100
100
[µs]
[µs]
DISABLE
DISABLE
t
t
10
10
1
1
1 10 100
1 10 100
versus C
EN (VDD
EN (VDD
= 5V).
= 5V).
REN= 220 k
REN= 220 k
CEN[nF ]
CEN[nF]
Ω
Ω
REN= 100 k
REN= 100 k
Ω
Ω
R
R
R
R
R
R
EN
EN
EN
EN
EN
EN
= 47 k
= 47 k
= 33 k
= 33 k
= 10 k
= 10 k
Ω
Ω
Ω
Ω
Ω
Ω
10
s]
µ
1
tdelay [
0.1
1 10 100
Cen [nF]
THERMAL PROTECTION
In addition to the Ovecurrent Protection, the L6225 integrates a Thermal Protection for preventing the device
destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible
element integrated in the die. The device switch-off when the junction temperature reaches 165°C (typ. value)
with 15°C hysteresis (typ. value).
11/20
L6225
APPLICATION INFORMATION
A typical application using L6225 is shown in Fig. 11. Typical component values for the application are shown
in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power
pins (VS
reduce high frequency transients ge nerate d by the switchi ng. The capaci t ors connected from the EN
inputs to ground set the shut down time for the Brgidge A and Bridge B respectively when an over current is
detected (see Overcurrent Protection). The two current sources (SENSE
to Power Ground with a trac e length as short as possible in th e layout. To increase noise immunity, unused logic
pins (except EN
description). It is recommended to keep Power Ground and Signal Ground separated on PCB.
Table 2. Component Values for Typical Application
C
C
C
C
C
C
and VSB) and ground near the L6225 to improve the high frequenc y fil t ering on the power supply and
A
and SENSEB) should be connected
A
and ENB) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin
A
1
2
BOOT
P
ENA
ENB
100uF D
100nF D
220nF R
10nF R
5.6nF R
5.6nF
1
2
ENA
ENB
P
1N4148
1N4148
100KΩ
100KΩ
100Ω
and EN
A
B
Figure 11. Typical Application
+
VS
8-52V
DC
POWER
GROUND
-
SIGNAL
GROUND
C
1
C
2
C
BOOT
D
1
LOAD
LOAD
VS
A
17
VS
B
14
R
VCP
P
C
D
A
B
P
2
VBOOT
SENSE
SENSE
OUT1
OUT2
OUT1
OUT2
19
12
A
3
B
8
A
4
A
18
B
B
13
20
11
9
10
1
2
16
157
6
5
D02IN1345
EN
EN
IN1
IN2
IN1
IN2
GND
GND
GND
GND
R
ENA
A
C
ENA
R
ENB
B
C
ENB
B
B
A
A
ENABLE
ENABLE
IN1
B
IN2
B
IN1
A
IN2
A
A
B
12/20
L6225
PARALLELED OPERATION
The outputs of the L6225 can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond connections
from the die to the power o r sense pins of the package must ca rry curr ent in both of the as sociated half bri dges.
When the two halves of one full bridge (for example OUT1
current rating is not increased since the total current must still flow through one bond wire on the power supply
or sense pin. In addition, the over current detection senses the sum of the current in the upper devices of each
bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detection threshold.
For most applications the recommended configuration is Half Bridge 1 of Bridge A paralleled with the Half Bridge
1 of the Bridge B, and the same for the Half Bridges 2 as shown in Figure 12. The current in the two devices
connected in parallel will share very well since the R
DS(ON)
In this configuration the resulting Bridge has the following characteristics.
- Equivalent Device: FULL BRIDGE
- R
0.37Ω Typ. Value @ TJ = 25°C
DS(ON)
- 2.8A max RMS Load Current
- 5.6A OCD Threshold
Figure 12. Parallel connection for higher current
VS
VS
8-52V
+
DC
POWER
GROUND
-
SIGNAL
GROUND
LOAD
C
2
D
1
R
P
BOOT
D
2
C
C
1
VS
VCP
C
P
VBOOT
SENSE
SENSE
OUT1
OUT2
OUT1
A
B
A
B
A
A
B
B
and OUT2A) are connected in parallel, the peak
A
of the devices on the same die is well matched.
17
14
19
12
3
8
4
18
7
13
EN
11
10
16
15
B
EN
IN1
1
IN2
2
IN1
9
IN2
GND
GND
GND
6
GNDOUT2
5
R
C
EN
EN
D02IN1359
A
A
A
B
B
EN20
IN1
IN2
To operate the device in parallel and maintain a lower over current threshold, Half Bridge 1 and the Half Bridge
2 of the Bridge A can be connected in parallel and the same done for the B ridge B as shown in Figure 13. In
this configuration, the pe ak c urrent for eac h hal f bridge is stil l l imited by the bond wi res for the s upply and s ense
pins so the dissipation in the device will be reduced, but the peak current rating is not increased. This configuration, the resulting bridge has the following characteristics.
- Equivalent Device: FULL BRIDGE
- R
0.37Ω Typ. Value @ TJ = 25°C
DS(ON)
- 1.4A max RMS Load Current
- 2.8A OCD Threshold
13/20
L6225
Figure 13. Parallel connection with lower Over current Threshold
VS
A
VS
8-52V
+
DC
POWER
GROUND
-
SIGNAL
GROUND
LOAD
C
1
C
2
D
1
R
P
C
C
BOOT
D
P
2
VBOOT
SENSE
SENSE
OUT1
OUT2
OUT1
OUT2
VS
VCP
17
B
14
19
12
A
3
B
8
A
4
A
18
B
B
13
EN
20
10
16
157
A
EN
IN1
1
IN2
2
IN1
9
IN2
R
EN
B
C
A
A
B
B
EN11
EN
IN
A
IN
B
GND
GND
GND
6
GND
5
D02IN1360
It is also possible to parallel the four Half Bridges to obtain a simple Half Bridge as show n in Fig. 14 The resulting
half bridge has the following characteristics.
- Equivalent Device: HALF BRIDGE
- R
0.18Ω Typ. Value @ TJ = 25°C
DS(ON)
- 2.8A max RMS Load Current
- 5.6A OCD Threshold
Figure 14. Paralleling the four Half Bridges
VS
VS
8-52V
+
DC
POWER
GROUND
-
SIGNAL
GROUND
C
1
C
2
D
1
R
P
C
BOOT
D
2
LOAD
VS
VCP
C
P
VBOOT
SENSE
SENSE
OUT1
OUT2
OUT1
OUT2
A
17
B
19
12
A
3
B
8
A
4
A
18
B
7
B
13
EN
1114
10
16
15
B
EN
IN1
1
IN2
2
IN1
9
IN2
R
A
A
A
B
B
EN
C
EN
EN20
IN
GND
GND
GND
6
GND
5
D02IN1366
14/20
L6225
OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION
In Fig. 15 and Fig. 16 are show n the approxi mate relation between the output current and the IC power dis sipation using PWM current control driving two loads, for two different driving types:
– One Full Bridge ON at a time (Fig. 15) in which only one load at a time is energized.
– Two Full Bridges ON at the same time (Fig. 16) in which two loads at the same time are energized.
For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to
establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125°C maximum).
Figure 15. IC Power Dissipation versus Output Curr ent with One Full Bridge ON at a time.
ONE FULL BRIDGE ON AT A TIME
PD [W]
10
8
6
4
2
0
0 0.25 0.5 0.75 1 1.25 1.5
[A]
I
OUT
I
A
I
B
I
OUT
I
OUT
Test Conditions:
Supply Voltage = 24V
No PWM
f
= 30 kHz (slow decay)
SW
Figure 16. IC Power Dissipation versus Output Current with Two Full Bridges ON at the same time.
TWO FULL BRIDGES ON AT THE SAME TIME
10
8
6
PD [W]
4
2
0
0 0.25 0.5 0.75 1 1.25 1.5
[A]
I
OUT
I
A
I
B
I
OUT
I
OUT
Test Conditions:
Supply Voltage = 24 V
No PWM
= 30 kHz (slow decay)
f
SW
THERMAL MANAGEMENT
In most applic ations the power dissipat i on in the IC is the main factor that set s the maximum current that can be deliver by the device in a safe operating condition. Therefore, it has to be taken i nto account very carefully. Besides the
available space on the PCB, the righ t package shoul d be chose n considering t he power dissipation. Heat sinking can
be achieved using copper on the PCB with proper area and thickness. Figures 18, 19 and 20 show the Junction-toAmbient Thermal Resistance values for the PowerSO20, PowerDIP20 and SO20 packages.
For instance, using a PowerSO package with copper slug soldered on a 1.5 mm copper thickness FR4 board
with 6cm
2
dissipating footprint (cop per thicknes s of 35µm), the R
is about 35°C/W. Fig. 17 shows mount-
th j-amb
ing methods for this package. Using a multi- layer board wi th vias to a ground plane, thermal impeda nce can be
reduced down to 15°C/W.
15/20
L6225
Figure 17. Mounting the PowerSO pack age.
Slug soldered
to PCB with
dissipating area
Slug soldered
to PCB with
dissipating area
plus ground layer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
Figure 18. PowerSO20 Junction -Am bient thermal resi stance versus on-bo ard co pper area.
ºC / W
43
38
33
28
23
18
13
12345678910111213
Without Ground Layer
With Ground Layer
With Ground Layer+16 via
Holes
sq. cm
On-Board Copper Area
Figure 19. PowerDIP20 Junction-Ambient thermal resistance versus on-board copper area.
ºC / W
42
41
40
39
38
37
36
35
34
33
123456789101112
Copper Area is on Bottom Side
Copper Area is on Top Side
sq . cm
On-Board Copper Area
Figure 20. SO20 Junction-Ambient thermal resi stance versus on-bo ard copp er area.
16/20
ºC / W
68
66
64
62
60
58
56
54
52
50
48
123456789101112
Copper Area is on Top Side
sq. cm
On-Board Copper Area
L6225
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
mm inch
A 3.6 0.142
a1 0.1 0.3 0.004 0.012
a2 3.3 0.130
a3 0 0.1 0.000 0.004
b 0.4 0.53 0.016 0.021
c 0.23 0.32 0.009 0.013
D (1) 15.8 16 0.622 0.630
D1 9.4 9.8 0.370 0.386
E 13.9 14.5 0.547 0.570
e 1.27 0.050
e3 11.43 0.450
E1 (1) 10.9 11.1 0.429 0.437
E2 2.9 0.114
E3 5.8 6.2 0.228 0.244
G 0 0.1 0.000 0.004
H 15.5 15.9 0.610 0.626
h 1.1 0.043
L 0.8 1.1 0.031 0.043
N 8˚ (typ.)
S 8˚ (max.)
T 1 0 0.394
(1) “D and E1” do not include mold flash or protusions.
- Mold flash or protusio ns shall not ex ceed 0.15mm (0.006”)
- Critical dimensions: “E”, “G” and “a3”.
OUTLINE AND
MECH AN ICAL DAT A
Weight:
1.9gr
JEDEC MO-166
PowerSO20
E2
NN
a2
b
h x 45
DETAIL A
e3
H
D
T
110
e
1120
E1
A
DETAIL B
PSO20MEC
R
lead
a3
Gage Plane
BOTTOM VIEW
E
DETAIL B
0.35
S
D1
a1
L
c
DETAIL A
slug
- C -
SEATING PLANE
GC
(COPLANARITY)
E3
0056635
17/20
L6225
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.85 1.40 0.033 0.055
b 0.50 0.020
b1 0.38 0.50 0.015 0.020
D 24.80 0.976
E 8.80 0.346
e 2.54 0.100
e3 22.86 0.900
F 7.10 0.280
I 5.10 0.201
L 3.30 0.130
Z 1.27 0.050
mm inch
OUTLINE AND
MECHANICAL DATA
Powerdip 20
18/20
L6225
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.35 2.65 0.093 0.104
A1 0.1 0.3 0.004 0.012
B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 12.6 13 0.496 0.512
E 7.4 7.6 0.291 0.299
e 1.27 0.050
H 10 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.4 1.27 0.016 0.050
K 0˚ (m in.)8˚ (m ax.)
mm inch
OUTLINE AND
MECHANICAL DATA
SO20
B
e
D
1120
110
L
h x 45˚
A
K
A1
C
H
E
SO20MEC
19/20
L6225
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent r i ght s of STMi croelectr oni cs. Spec i fications mentioned i n this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approva l of STMicroel ectronics.
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All other n am es are the property of th ei r respectiv e owners
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20/20
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