Features
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rd
■ 3
order high resolution sigma delta converter
for MPX sampling
■ Digital decimation and filtering stages
■ Demodulation of european radio data system
(RDS)
■ Demodulation of USA radio broadcast data
system (RBDS)
■ Automatic group and block synchronization
with flywheel mechanism
■ Error detection and correction
■ RAM buffer with a storage capacity of 24 RDS
blocks and related status information
■ Programmable interrupt source (RDS block
TA)
2
■ I
C/SPI bus interface
■ Common quartz frequency 8.55 MHz or
8.664 MHz
■ 3.3 V power supply, 0.35 µm CMOS
technology
TDA7333
RDS/RBDS processor
TSSOP16
Description
The TDA7333 circuit is a RDS/RDBS signal
processor, intended for recovering the inaudible
RDS/RBDS informations which are transmitted on
most FM radio broadcasting stations.
Table 1. Device summary
Order code
E-TDA7333 -40 to +85 TSSOP16 Tube
E-TDA7333013TR -40 to +85 TSSOP16 Tape and reel
1. Devices in ECOPACK® package (see Section 5: Package information ).
(1)
Operating temp. range, °C Package Packing
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June 2008 Rev 1 1/26
www.st.com
1
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Contents TDA7333
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Quick reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Sigma delta converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Sinc4/16 decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 RDS bandpass filter and interpolator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6 Group and block synchronization module . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7 Programming through serial bus interface . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.1 rds_int register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7.2 rds_qu register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7.3 rds_corrp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.4 rds_bd_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.5 rds_bd_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7.6 rds_bd_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8 I2C transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8.1 Write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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3.9 SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8.2 Read transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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TDA7333 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. External pins alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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List of figures TDA7333
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Transfer function of a 4
Figure 4. Magnitude response of sinc. 4/16 filter in RDS band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Transfer function of RDS bandpass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Phase response of the RDS bandpass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Demodulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Group and block synchronization block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. rds_int register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. rds_qu register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. rds_corrp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. rds_bd_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. rds_bd_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. rds_bd_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. I2C data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. I2C write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. I2C write operation example: write of rds_int and rds_bd_ctrl registers . . . . . . . . . . . . . . . 19
Figure 18. I2C read transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 19. I2C read access example 1: read of 5 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 20. I2C read access example 2: read of 1 byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 21. SPI data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 22. Write rds_int and rds_bd_ctrl registers in SPI mode, reading RDS data and related flags 21
Figure 23. Read out RDS data and related flags, no update of rds_int and rds_bd_ctrl registers. . . . 22
Figure 24. Write rds_int registers in SPI mode, reading 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. TSSOP16 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
th
order sinc. filter, decimation factor is 16. . . . . . . . . . . . . . . . . . . 11
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TDA7333 Block diagram and pin description
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
Cmpx
SCL_CLK
SDA_DATAIN
SA_DATAOUT
CSN
MPX
16
11
12
13
14
Cref Cref Cref
REF1
4 3 2
SIGMA DELTA
converter
REF3 REF2
TEST LOGIC
&
PIN MUX's
resetn
tm
8 6
TM RESETN
16pF
10
Cxto
BANDPASS
filter
VDDA
Cxti
16pF
XTI XTO
9 1 5 7
OSCILLATOR
SINC4
filter
sinc4reg
sdaout
sdain
I2C/SPI
sck
interface
spi
testreg
VSS
INTERPOLATOR
RDS
demodulator &
synchronisation
VDDD
MPX
MPX
INTN
15
INTN
1.2 Pin description
Figure 2. Pin connection (top view)
VDDA
1
REF3
2
REF2
3
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REF1
4
TDA7333
VSS
5
TM
6
7
RESETN
8
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MPX
16
INTN
15
CSN
14
SA_DATAOUT
13
SDA_DATAIN
12
SCL_CLK
11
XTO VDDD
10
XTI
9
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Block diagram and pin description TDA7333
Table 2. Pin description
Pin # Pin name Function
1 VDDA Analog supply voltage
2 REF3 Reference voltage 3 of A/D converter (2.65 V)
3 REF2 Reference voltage 2 of A/D converter (1.65 V)
4 REF1 Reference voltage 1 of A/D converter (0.65 V)
5 VSS Common ground
6T M
7 VDDD Digital supply voltage
8 RESETN External reset input (active low)
9 XTI Oscillator input
10 XTO Oscillator output
11 SCL_CLK Clock signal for I
12 SDA_DATAIN Data line in I
13 SA_DATAOUT Slave address in I
14 CSN Chip select (1 = I
15 INTN
Testmode selection (scan test).
Normal mode must be connected to gnd.
2
C and SPI modes
2
C mode, data input in SPI mode
2
C mode, data output in SPI mode
2
C mode, 0=SPI mode)
Interrupt output (active low), prog. at buff.not empty, buff. full, block A,B,D
,TA, TA EON
16 MPX Multiplex input signal
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TDA7333 Electrical specifications
2 Electrical specifications
2.1 Quick reference
Table 3. Quick Reference
Symbol Parameter Min. Typ. Max. Unit
V
DDA/VDDD
T
S
V
(T
= 25 °C, VDDA/VDDD = 3.3 V, f
amb
Analog/digital power supply 3.0 3.3 3.6 V
amb
f
osc
I
dd
P
d
RDS
MPX
i Maximum speed in SPI mode 1 MHz
f
SP
f
i2c
Operating temperature -40 +85 °C
Quartz frequency
Total supply current 10 mA
Power dissipation 33 mW
RDS input sensitivity 1 mVrms
Input range of MPX signal 750 mVrms
Maximum speed in I2C mode 400 kHz
= 8.55 MHz)
osc
8.55 or
8.664
MHz
2.2 Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
V
peak
3.3 V power supply voltages -0.5 4 V
DD
Input voltage 5 V tolerant inputs -0.5 5.5 V
in
Output voltage 5 V tolerant output buffers in tri-state -0.5 5.5 V
out
Maximum peak voltage 6 V
2.3 General interface electrical characteristics
Table 5. General interface electrical characteristics
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Symbol Parameter Test conditions Min. Typ. Max. Unit
I
il
I
ih
I
oz
Low level input current Vi = 0 V 1 µA
High level input current Vi = V
V
= 0 V or V
Tri-state output leakage
o
= 5.5 V 1 3 µA
V
o
DD
DD
1µ A
1µ A
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Electrical specifications TDA7333
2.4 Electrical characteristics
Table 6. Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
Supply (pin 1,5,7)
V
DDD
V
DDA
I
DDD
I
DDA
P
d
Digital inputs (pin 6,8,11,12,13,14)
V
il
V
ih
V
ilhyst
V
ihhyst
V
hst
Digital outputs (pin 12,13,15) are open drains
T
= -40 to +85 °C, V
amb
V
and V
DDD
Digital supply voltage 3.0 3.3 3.6 V
Analog supply voltage 3.0 3.3 3.6 V
Digital supply current 2 mA
Analog supply current 8 mA
Total power dissipation 33 mW
Low level input voltage 0.8 V
High level input voltage 2.0 V
Low level threshold input
falling
High level threshold input
rising
Schmitt trigger hysteresis 0.4 0.7 V
must not differ more than 0.15 V
DDA
DDA/VDDD
= 3.0 to 3.6 V, f
= 8.55 MHz, unless otherwise specified
osc
1.0 1.15 V
1.5 1.7 V
V
V
Analog inputs (pin 16)
V
MPX
S
R
Crystal parameters
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f
g
C
xti,Cxto
t
High level output voltage
oh
Low level output voltage
ol
Input range of MPX signal 0.75 Vrms
RDS detection sensitivity 1 mVrms
RDS
Input Impedance of MPX pin 55k Ohm
MPX
Quartz frequency
osc
Start up time 10 ms
su
Transconductance 0.0006 A/V
m
Load capacitance 16 pF
Open drain, depends on external
circuitry
= 4 mA, takes into account
I
ol
200 mV drop in the supply voltage
8.55 or
8.664
V
DDD
0.4 V
V
MHz
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TDA7333 Electrical specifications
Table 6. Electrical characteristics (continued)
T
= -40 to +85 °C, V
amb
V
and V
DDD
Symbol Parameter Test conditions Min. Typ. Max. Unit
Sigma delta modulator
must not differ more than 0.15 V
DDA
DDA/VDDD
= 3.0 to 3.6 V, f
= 8.55 MHz, unless otherwise specified
osc
F
OVR Oversampling ratio f = 57 kHz 38
THD+N
Sinc4/16 decimation filter
A57 Attenuation at 57 kHz -2.6 dB
Bandpass filter
R
f
stop
R
M
2
I
C
f
SPI
Sample rate f
s
Relative total harmonic dist.
plus noise
f
Decimated sample rate f
s
Attenuation difference BW = 54.5 to 59.5 kHz 0.4 dB
f
Sample rate f
s
f
Pass-band frequencies 55.6 58.4 kHz
p
Pass-band ripple -0.5 +0.5 dB
p
Stop-band corner frequencies 53.0 61 kHz
Stop-band attenuation -43 dB
s
Interpolation factor 32
i
Clock frequency in I2C mode 400 kHz
I2C
= 8.55 MHz 4.275 MHz
osc
BW = 54.5 to 59.5 kHz,
unweigted, V
= 8.55 MHz 267.2 kHz
osc
= 8.55 MHz 267.2 kHz
osc
= 3 mVrms
rds
27 dB
f
SPI
t
t
t
t
odv
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t
t
Clock frequency in SPI mode 1 MHz
Clock high time 450 ns
ch
Clock low time 450 ns
t
cl
Chip select setup time 500 ns
csu
Chip select hold 500 ns
csh
Output data valid 250 ns
Output hold 0 ns
oh
Deselect time 1000 ns
t
d
Data setup time 200 ns
su
t
Data hold time 200 ns
h
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