STMicroelectronics DALC208SC6 Schematic [ru]

®

DALC208SC6

Application Specific Discretes

A.S.D.

MAIN APPLICATIONS

Where ESD and/or over and undershoot
protection for datalines is required :

Sensitive logic input protection

■

Microprocessor based equipment

■

Audio / Video inputs

■

Portable electronics

■

Networks

■

ISDN equipment

■

USB interface

■

DESCRIPTION

The DALC208SC6 diode array is designed to
protect components which are connected to data
and transmission lines from overvoltages caused
by electrostatic discharge (ESD) or other
transients. It is a rail-to-rail protection device also
suited for overshoot and undershoot suppression
on sensitive logic inputs.

The low capacitance of the DALC208SC6
prevents from significant signal distortion.

TM

LOW CAPACITANCE

DIODE ARRAY

1

SOT23-6L (SC74)

FUNCTIONAL DIAGRAM

FEATURES

■

PROTECTION OF 4 LINES

■

PEAK REVERSE VOLTAGE:

= 9 V per diode

V

RRM

■

VERY LOW CAPACITANCE PER DIODE:
C< 5pF

■

VERY LOW LEAKAGE CURRENT: IR<1µA

BENEFITS

■

Cost-effectiveness compared to discrete solution

■

High efficiency in ESD suppression

■

No significant signal distortion thanks to very low
capacitance

■

High reliability offered by monolithic integration

■

Lower PCB area consumption versus discrete
solution

February 2002 - Ed: 5C

I/O 1

I/O 4

REF 2 REF 1

I/O 2 I/O 3

COMPLIESWITHTHEFOLLOWINGSTANDARDS:

IEC61000-4-2 level4
MIL STD 883C - Method 3015-6

(human body test) class 3

1/10

DALC208SC6

ABSOLUTE MAXIMUM RATINGS (T

amb

= 25°C).

Symbol Parameter Value Unit

V

PP

V

RRM

∆V

REF

max.

V

In

min.

V

In

I

F

I

FRM

I

FSM

IEC61000-4-2, air discharge
IEC61000-4-2, contact discharge

Peak reverse voltage per diode
Reference voltage gap between V

REF2

and V

REF1

Maximum operating signal input voltage
Minimum operating signal input voltage
Continuous forward current (single diode loaded)
Repetitive peak forward current (tp=5µs,F=50kHz)
Surge non repetitive forward current -

15

8
9V
9V

V

REF2

V

REF1

200 mA
700 mA

rectangular waveform (see curve on figure 1)

= 2.5 µs

t

p

=1ms

t

p

= 100 ms

t

p

T

stg

T

j

Storage temperature range
Maximum junction temperature

6
2
1

-55 to + 150
150

THERMAL RESISTANCE

Symbol Parameter Value Unit

R

th(j-a)

Note 1: device mounted on FR4 PCB with recommended footprint dimensions.

Junction to ambient (note 1)

500 °C/W

kV

V
V

A

°C
°C

ELECTRICAL CHARACTERISTICS (T

amb

= 25°C).

Symbol Parameter Conditions Typ. Max. Unit

V

F

I

R

C

Note 2: The dynamical behavior is described in the Technical Information section, on page 4.

Forward voltage

Reverse leakage current per diode

Input capacitance between Line and GND

=50mA 1.2 V

I

F

=5V 1 µA

V

R

see note 3 7 10 pF

Note 3: Input capacitance measurement

REF2

REF1 connected to GND

I/O

+V

CC

REF2 connected to +Vcc
Input applied :

R

V

G

Vcc = 5V, Vsign = 30 mV, F = 1 MHz

REF1

2/10

DALC208SC6

Fig. 1: Maximumnon-repetitive peak forward current

versus rectangular pulse duration (Tj initial = 25°C).

IFSM(A)

8
7

I/O vs

REF1 or

REF2

6
5
4
3
2
1
0

0.001 0.01 0.1 1 10 100 1000

tp(ms)

Fig. 3: Variation of leakage current versus junction

temperature (typical values).

IR(µA)

100

Fig. 2: Reverse clamping voltage versus peak
pulse current (Tj initial = 25°C), typical values.
Rectangular waveform tp = 2.5 µs.

Ipp(A)

2.0

tp=2.5µs

1.0

I/O vs REF1

or REF2

0.1
5 1015202530

Vcl(V)

Fig. 4: Input capacitance versus reverse applied

voltage (typical values).

C(pF)

8.0

10

1

0.1

0.01
25 50 75 100 125 150

Tj(°C)

Fig. 5: Peak forward voltage drop versus peak for-

ward current (typical values).
Rectangular waveform tp = 2.5 µs.

IFM(A)

10.0

Tj=25°C

Tj=150°C

1.0

7.5

7.0

6.5

6.0

5.5

5.0
012345

F=1MHz

Vsign=30mV

Vref1/ref2=5V

VR(V)

I/O vs REF 1

or REF2

0.1
0 2 4 6 8 10 12 14 16 18 20

VFM(V)

3/10

DALC208SC6

TECHNICAL INFORMATION
SURGE PROTECTION

The DALC208SC6 is particularly optimized to
perform surge protection based on the rail to rail
topology.

The clamping voltage V
follow :

+=V

V

CL

V

CL

with : V
(V

F=Vt

forward drop voltage) / (Vtforward drop

F

-=V

+ rd.Ip

REF2+VF
REF1 -VF

threshold voltage)

can be calculated as

CL

for positive surges
for negative surges

APPLICATION EXAMPLE

If we consider that the connections from the pin
REF

to VCCand from REF1to GND are done by

2

two tracks of 10mm long and 0.5mm large; we
assume that the parasitic inductances of these
tracks are about 6nH.

So when an IEC61000-4-2 surge occurs, due to
the rise time of this spike (tr=1ns), the voltage V

CL

has an extra value equal to Lw.dI/dt.
The dI/dt is calculated as:

di/dt = Ip/tr ′ 24 A/ns

The overvoltage due to the parasitic inductances
is: Lw.di/dt=6x24′144V

According to the curve Fig.5 on page 3, we
assumethatthevalueof the dynamic resistance of
the clamping diode is typically rd = 0.7Ω and V

t

1.2V.
For an IEC61000-4-2 surge Level 4 (Contact

Discharge: Vg=8kV, Rg=330Ω), V
V

= 0V, and if in first approximation, we

REF1

REF2

= +5V,

assume that : Ip=Vg/Rg ′ 24A.
So, we find:

+ ′ +23V

V

CL

V

- ′ -18V

CL

Note: the calculations do not take into account

By taking into account the effect of these parasitic
inductancesdueto unsuitable layout, the clamping

=

voltage will be :

+ = +23 + 144 ′ 167V

V

CL

V

- = -18 - 144 ′ -162V

CL

We can reduce as much as possible these
phenomena with simple layout optimization.

It’s the reason why some recommendations have
to be followed (

good ESD protection”

phenomena due to parasitic inductances

Fig. A1: ESD behavior; parasitic phenomena due to unsuitable layout.

Vf

Vcl+ =

Vcl- =

Lw

di

Lw

dt

Vcc+Vf+

-Vf-

Lw

Lw

dt

di

dt

REF2=+Vcc

di

surge >0

surge <0

ESD

SURGE

VI/O

Lw

I/O

di

dt

see paragraph “How to ensure a

).

4/10

167V

di

Lw

dt

Vcc+Vf

Vcl+

tr=1ns

POSITIVE

SURGE

REF1=GND

tr=1ns

-Vf

NEGATIVE

di

-Lw
dt

t

-162V

SURGE

Vcl-

t