STMicroelectronics AVAS User Manual

UM2719

User manual

AVAS architecture based on AutoDevKit

Introduction

The AutoDevKit Acoustic Vehicle Alerting System (AVAS) consists of an AEK-MCU-C1MLIT1 Discovery board, an AEK-AUD- D903V1 evaluation board, and appropriate speakers. The AEK-MCU-C1MLIT1 board MCU monitors and controls the FDA903D power amplifier on the AEK-AUD-D903V1 board via I²C and I²S serial interfaces and GPIOs.

The MCU board and the audio board can be wired together directly or via a connector board designed to simplify the process.

The AEK-MCU-C1MLIT1 board is supplied 5 V through its mini-USB connector, while the AEK-AUD-D903V1 can either be supplied low voltage (from 3.3 V to 18 V) or standard voltage (from 5 V to 18 V).

Figure 1. AVAS system AutoDevKit control board and audio board

The hardware is fully supported by a software ecosystem, which includes SPC5-STUDIO development environment, SPC5- UDESTK-SW software for debugging and STSW-AUTODEVKIT Eclipse plugin containing AEK-AUD-D903V1 driver and sample application codes.

UM2719 - Rev 3 - April 2021	www.st.com
For further information contact your local STMicroelectronics sales office.

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AVAS system hardware

1AVAS system hardware

Figure 2. AVAS demo hardware and connections

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AEK-MCU-C1MLIT1 Discovery board audio support

2AEK-MCU-C1MLIT1 Discovery board audio support

The AEK-MCU-C1MLIT1 Discovery evaluation board features the SPC582B60E1 automotive microcontroller with high performance e200z2 single core 32-bit CPU with 80MHz clock, 1088 KB Flash and 96 KB SRAM in an eTQFP64 package. The I²S (simulated by an SPI port), I²C port and GPIOs provide the necessary signal and communication lines to control a class D power amplifier.

The board also integrates a programmer/debugger interface based on the UDE PLS software, allowing the user to program the microcontroller and debug software applications. The integrated debugger software is available through ST's free integrated development environment, SPC5-STUDIO. To download the debugger software and to activate the license, refer to the PLS website.

Note:

Arduino connectors are not mounted on this board and are not required for the audio application.

Figure 3. AEK-MCU-C1MLIT1 Discovery board components

1.PLS programmer/debugger

2.USB power connector to supply 5V and load firmware

3.User interface with three LEDs and two buttons

4.32-bit SPC582B60E1 MCU

5.CN10 19x2 connector for access to I²C and I²S ports and GPIOs

6.CN7 11x2 connector for access to I²S ports and GPIOs

7.CN6 connector allows supplying the board with different external voltage (3.3 V, 5 V or 12 V)

The SPC582B60E1 microcontroller includes the following additional features:

•1088 KB (1024 KB code flash + 64 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation

•Comprehensive new generation ASIL-B safety concept:

–ASIL-B of ISO 26262 – FCCU for collection and reaction to failure notifications

–Memory Error Management Unit (MEMU) for collection and reporting of error events in memories.

•1 enhanced 12-bit SAR analog-to-digital converter:

–Up to 27 channels (two channels are used in the AVAS application for sound volume and acceleration)

–enhanced diagnostic feature.

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I²S bus interface on the SPC582B60E1 microcontroller

•I²C interface

•4 serial peripheral interface (DSPI) modules (a DSPI is used in the AVAS Demo to simulate the I²S bus interface).

2.1I²S bus interface on the SPC582B60E1 microcontroller

The FDA903D audio amp receives the audio signal from the flash blocks of the SPC582B60E1 via the I²S bus. This interface can transmit two different audio channels on the same data line. As SPC5 microcontrollers do not have a native I²S interface, an emulation through the DSPI protocol is implemented.

2.1.1I²S protocol details

The I²S bus consists of the following lines:

I2S SCL	The clock signal frequency is the product of the sampling frequency and the number of bits
	transmitted.
I2S DATA	The transmitted data are coded in two's complement, and the MSB (Most Significant Bit) is
	therefore in the first position of each word. The data word is composed of 32 bits.
Note:	The device only processes the first 24 most significant bits and disregards the least significant 8 bits.
I2S WS	The Word Select signal is synchronized with the sampling frequency. Its digital value identifies
	the transmission channel (0 = right channel, 1 = left channel).

2.1.2I²S emulation on DSPI for SPC5 MCU control of FDA903D amplifier

The FDA903D power amplifier allows audio playback at the following sampling frequencies:

•44.1 kHz

•48 kHz

•96 kHz

•192 kHz

The maximum DSPI clock limit can only support the lowest frequency (fs = 44.1 kHz).

DSPI is a synchronous serial communication interface primarily used for short-distance communication in embedded systems. This interface is based on four signals:

SCLK:		the serial clock signal from the master (the microcontroller in our application)
MOSI:		the serial data from the master to the slave (the FDA903D in our case)
MISO:		the serial data from the slave to the master
CS:		selects which slave chip receives the message from the master
DSPI emulation of the I²S interface is therefore obtained through the following associations and parameter values:
•	I2S DATA → DSPI MOSI
	–	32-bit data word
•	I2S WS → DSPI CS
	–	varies the channel (right or left) according to the fs (sampling frequency).
•	I2S SCLK → DPSI SCLK
	–	Frequency = numberofc annels × numberofbitsinaword × samplingfrequency = 2x32x44.1kHz
		TEST → DSPI MISO
•	I2S	= 2.822 MHz .
	–	This additional signal allows the FDA903D to send real-time current sensing information to the
		microcontroller and to a DSP for sound processing.

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		UM2719
	I²S bus interface on the SPC582B60E1 microcontroller
	Figure 4. Standard I²S data format
	1 / fs
TSCK	1 / (64 x fs)
		I2Sclk
1 / (2 x fs)	1 / (2 x fs)	I2Sws
Left channel	Right channel	I2Sdata

•MCU DSPI0 port access via four CN10 connector pins

•MCU has four DSPI ports

Figure 5. Connector CN10 pins for DSPI0

I2S SCL

I2S CR

I2S SDA

I2S WS

RELATED LINKS

Refer to TN1296: "I²S emulation on DSPI" for more information about emulating the I²S protocol

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I²C bus interface on the SPC582B60E1 microcontroller

2.2I²C bus interface on the SPC582B60E1 microcontroller

The I²C interface is used to control, program and request information from the audio amp. Data transmission from SPC582B60E1 to the FDA903D and vice versa takes place through the two-wire I²C bus interface for the SDA and SCL lines.

Note:

According to the I²C protocol, it is mandatory to insert pull-up resistors to positive supply voltage on the SDA and

SCL lines.

Figure 6. I²C typical data format

[S] Start bit

Chip address byte

Sub-address byte

[data] n-byte + Acknowledge bit

[P] Stop bit

S

Address

A

Subaddress

A

Data

P

=

Address

ADDR

ADDR

ADDR

ADDR

ADDR

ADDR

ADDR

ADDR

Subaddrs

Data

=

=

SUB A	SUB A	SUB A	SUB A	SUB A	SUB A	SUB A	SUB A
DATA	DATA	DATA	DATA	DATA	DATA	DATA	DATA

The AEK-MCU-C1MLIT1 provides I²C port access through two pins on the CN10 connector shown in the figure below.

The discovery board has a single dedicated I²C port. Additional ports can be added by emulating the I²C protocol via software to configure a GPIO pin for I²C SCL and another pin for I²C SDA.

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I²C bus interface on the SPC582B60E1 microcontroller

Figure 7. Connector CN10 pins dedicated to I²C

I2C SCL

I2C SDA

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AEK-AUD-D903V1 evaluation board for automotive power amplifier

3AEK-AUD-D903V1 evaluation board for automotive power amplifier

The AEK-AUD-D903V1 is designed to allow evaluation and application development based on the embedded FDA903D automotive digital class D power amplifier in a PowerSSO-36 slug-down package.

Figure 8. AEK-AUD-D903V1 main components and interfaces

1. Output channel; 2. FDA903D power amplifier; 3. Power supply connector

4.Enable and HW mute pins: [EN1 to EN4]: 4 pins can be configured to switch on the amplifier and assign it on of 7 possible an

I²C addresses, [MUTE]: allows MUTE setting control of the power amplifier through a GPIO

5.I²C interface: [I2C SCL]: I2C clock line, [I2C SDA]: I2C data line

6.I²S interface: [I2S SCL]: I2S clock line, [I2S WS]: I2S Word select line, [I2S SDA]: digital input, [I2S CR]: I2S Output test current, [GND]

2

1

3

4

5

6

The FDA903D power amplifier can be configured through its I²C bus interface and the device includes the following diagnostics suite designed for automotive applications:

•open load in play detection

•DC diagnostic in MUTE to monitor the load status

•short to VCC / GND diagnostic

•digital Input Offset detection

•output Voltage Offset detection

•output Current Offset detection

•thermal protection

The FDA903D features a configurable power limiting function and can be optionally operated in legacy mode without I²C communication.

3.1FDA903D finite state machine

The FDA903D finite state machine (FSM) describes how the device reacts to system and user inputs.

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FDA903D finite state machine

Figure 9. FDA903D state machine

90ms Short to Vcc/Gnd check

Enables set AND

Stand By I2C programmed for the first time

Diag Vcc/Gnd

Enables = "0000"

OR

Vcc for system reset

OR

I2S missed or not correct

		Overcurrent protection
		OR
	Vcc under	UVLO present
		OR
	Overvoltage
		Thermal shutdown
	shutdown limit

Dump

I2C cmd: "MUTE"

OR

Automatic mute Vcc over Overvoltage condition present

shutdown limit

I2C cmd: “PLAY”

Play

No short to Vcc/Gnd condition STABLE for at least 90ms

Short to Vcc/Gnd present	ECO-mode
(even for one instant)

I2C cmd: “PWM OFF”

I2C cmd: “PWM ON”

Mute	I2C cmd:
	“Diag DC start”
	Diagnostic DC end	Diag DC

The initial standby state of the device cannot be exited until the I²C interface has been correctly enabled by providing the correct supply voltage, the I²S clock, the I²S data and a valid combination of enable pins in order to determine the I²C device address.

Table 1. I²C device address combinations

Configuration				Pin
		Enable 1	Enable 2		Enable 3	Enable 4
Standby		0	0		0	0
Amplifier ON address 1 = ‘1110000’		0	1		0	0
Amplifier ON address 2 = ‘1110001’		1	1		0	0
Amplifier ON address 3 = ‘1110010’		0	0		1	0
Amplifier ON address 4 = ‘1110011’		0	1		1	0
Amplifier ON address 5 = ‘1110100’		0	1		0	1
Amplifier ON address 6	= ‘1110101’	1	1		0	1
Amplifier ON address 7	= ‘1110110’	0	0		1	1
Amplifier ON address 8	= ‘1110111’	0	1		1	1

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FDA903D I²S protocol

When a valid combination of Enable 1/2/3/4 is recognized, the device turns on all the internal supply voltages and outputs are biased to VCC / 2. The internal I²C registers are preset in the default condition until the I²C next instruction. A return to the Standby condition (all the enable pins set to 0) resets of the amplifier. The finite state machine shows that a reset is also triggered if PLL is not locked, I²S is missing or not correct, or VCC is removed.

There are also four possible legacy mode combinations for device operation without using the I²C interface.

Table 2. Legacy mode Enable configurations

	Configuration			Pins
		Enable 1	Enable 2		Enable 3	Enable 4
	Legacy mode: low voltage mode; in-phase	1	1		1	0
	Legacy mode: low voltage mode; out-phase	1	1		1	1
	Legacy mode: standard voltage mode; in-phase	1	0		0	0
	Legacy mode: standard voltage mode; out-phase	1	0		0	1
Note:	FDA903D can only work in I²C slave mode; any combination other than those indicated are invalid.

3.1.1FDA903D FSM state descriptions

Standby	The ENABLEx pins set the I²C addresses and start up the system; if ENABLE1/2/3/4 are all
	low ("0000"), then the FDA903D is off, the outputs remain biased to ground and the current
	consumption is limited.
Diagnostic Vcc-Gnd	This state checks the device is in a safe operating condition, with no short to ground (Gnd),
	short to VCC, overcurrent, undervoltage (UVLOVcc), or thermal shutdown. The FDA903D moves
	to the next Eco-mode if none of these faults occur for at least 90 ms. A stable fault is
	communicated to the user via I²C messages after 90 ms. While in Diagnostic Vcc-Gnd state,
	FDA903D can receive all the I²C commands but will not turn the PWM on.
ECO-mode	The amplifier is fully operational and can receive and execute any valid command. Output
	switching is disabled for low power consumption. The device can move from ECO-mode to
	the MUTE state in order to activate switching within about 1 ms and without experiencing
	POP-noise. This facilitates fast transition from ECO-mode to PLAY.
MUTE	The FSM transitions from ECO-mode to the MUTE state through the I²C command to turn on
	PWM. The MUTE state allows quick transition to PLAY and diagnostic states.
PLAY	The FSM transitions to this state from MUTE via the I²C “PLAY” command, and the same status
	register bit governs the return from PLAY back to MUTE. Certain external conditions such as
	low battery mute, high battery mute, hardware mute pin and thermal mute automatically return
	the amplifier to the MUTE state.
Diag DC	This state starts the DC diagnostic routine to detect the load connection status and returns to
	the MUTE state when the routine has finished.

Note: I²C commands performed by the user are executed via the I²C protocol by modifying the device register settings.

RELATED LINKS

Refer to the FAD903 datasheet for more information regarding its state machine

3.2FDA903D I²S protocol

Audio data is transmitted to the power amplifier via the I²S protocol. The 32-bit data word is in two's complement representation starting from the MSB. The device only processes the first 24 most significant bits and disregards the 8 least significant bits.

Note:	Besides the standard I²S used in our demo, the FDA903D device also supports Time Division Multiplexing mode
	(TDM).

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FDA903D I²C protocol

The FDA903D internal PLL locks on the I²S clock line signal frequency, which is why it is important to configure the I²S bus appropriately. When the I²S clock is missing or corrupted, the PLL unlocks and the device is forced into a standby state.

Figure 10. I²S (DSPI) connection in AEK-AUD-D903V1

I2S CLOCK LINE

I2S WS LINE

I2S DATA LINE

I2S CURRENT TEST

3.3FDA903D I²C protocol

The DATA and SCLK wires for the I²C protocol are used to communicate, control and manage the FDA903D. Connection between the I²C microcontroller port and I²C power amplifier pins on the AEK-AUD-D903V1 is provided by the pins on the connector shown below.

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FDA903D I²C protocol

Figure 11. I²C connection in AEK-AUD-D903V1

I2C CLOCK LINE

I2C DATA LINE

The power amplifier FDA903D is controlled with appropriate read and write operations on Instruction Bytes registers (from IB0 to IB14) performed with the I2C protocol. Additional Data Bytes registers (from DB0 to DB6) in the device record the state of the amplifier.

Writing to the instruction registers and reading from the device status registers are the fundamental elements of device management.

3.3.1I²C protocol writing procedure

Communication through the I²C protocol takes place via a well-defined sequence of bit packages: start bit → recipient address → acknowledge bit → sub-address → acknowledge bit → actual data → stop bit.

The amplifier address is chosen from eight possible enable pins combinations that represent eight corresponding addresses. For example, to assign I²C address1 = “1110000” to the device, enable pin 2 is set high (Enable 2 = “1”) and enable pins 1,3 and 4 are set low (Enable1 = “0”, Enable3 = “0”, Enable4 = “0”).

Table 3. I²C address 1 selection

Configuration				Pin
		Enable 1	Enable 2		Enable 3	Enable 4
Standby		0	0		0	0
Amplifier ON address 1 = ‘1110000’		0	1		0	0
Amplifier ON address 2	= ‘1110001’	1	1		0	0
Amplifier ON address 3	= ‘1110010’	0	0		1	0
Amplifier ON address 4	= ‘1110011’	0	1		1	0

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FDA903D I²C protocol

Configuration				Pin
		Enable 1	Enable 2		Enable 3	Enable 4
Amplifier ON address 5	= ‘1110100’	0	1		0	1
Amplifier ON address 6	= ‘1110101’	1	1		0	1
Amplifier ON address 7	= ‘1110110’	0	0		1	1
Amplifier ON address 8	= ‘1110111’	0	1		1	1

The connector on the AEK-AUD-D903V1 provide access to the four enable pins by four corresponding GPIO pins on the microcontroller.

Important: Close J2 connector pins with jumpers.

Figure 12. ENABLE pin locations on the connector

ENABLE 1

ENABLE 2

ENABLE 3

ENABLE 4

The subaddress is assigned according to the IB register to be written, as shown in the following table.

	Table 4. Subaddress association
Register name		Corresponding Subaddress
IB0		I0000001
IB1		I0000010

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FDA903D I²C protocol

Register name	Corresponding Subaddress
IB2	I0000011
IB3	I0000100
IB4	I0000101
IB5	I0000110
IB6	I0000111
IB7	I0001000
IB8	I0001001
IB9	I0001010
IB10	I0001011
IB11	I0001100
IB12	I0001101
IB13	I0001110
IB14	I0001111

In the above table, bit 7 of the subaddress is the letter “I” to represent the possibility of having an incremental writing procedure. If the “I” bit is set to 1, the write operation is performed from the corresponding register and all consecutive ones with a unique flow of data from I²C. The process can involve all registers or can be interrupted by a stop bit received from I²C.

The data bits carry the actual information required to control the power amplifier.

3.3.2I²C protocol: reading procedure

The reading procedure consists of the device address (sent by master) and the data (sent by slave).

Figure 13. Read operation packet

When a reading procedure is performed, the first register read is the last addressed in a previous access to I²C peripheral. Hence, the reading of a register is enabled by a write action (a write interrupted after the sub-address is sent) to specify which register must be read. The following figure shows the complete procedure to read a specific register where:

1.The master performs a write action by sending only the device address and the subaddress; the transmission must be interrupted with the stop condition after the subaddress.

2.The master starts a new communication by sending the device address and the FDA903D slave responds by sending the data bits.

3.The read communication is ended by the master which sends a stop condition preceded by a notacknowledge.

Figure 14. Read operation required data

Alternatively, performing a start immediately after the stop condition can be used to generate the repeated start condition (Sr), which also keeps busy the I²C bus until the stop is reached.

Figure 15. Read operation with repeated start condition

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FDA903D I²C protocol

3.3.3IB registers in I²C

The microcontroller accesses all amplifier functionality through the IB registers.

				Table 5. IB register map
				IB register map
	D7	D6	D5	D4		D3		D2		D1	D0
IB0		D7: enable/disable writing on IB registers
		D6-D5: enable/disable the I²S standard protocol for transmitting the digital input
		D4-D1: choose between right or left channel
		DO: select between low voltage and standard voltage modes
IB1		D7-D6: select the I²S WS
		D4-D3: select the PWM switching frequency based on the I²S WS value
		D2: select between PWM amplifier dithered or not dithered
		DO: select between PWM in phase or out of phase
IB2		D7-D6: establish the short to supply diagnostic timing
		D4: activate/deactivate the low radiation function
		D3-D0: enable and configure the amplifier power limiter
IB3		D5: enable/disable output voltage offset detector
		D4: enable/disable input offset detector
		D3: enable/disable output current offset detector
		D2: enable/disable high pass filter in DAC amplifier DAC
		D1: enable/disable noise gating
		D0: enable/disable open load in play detection
IB4		D7: enable CDDIAG to report presence of output voltage offset
		D6-D4: enable CDDIAG to report temperature warnings
		D3: enable CDDIAG to report overcurrent faults
		D2: enable CDDIAG to report input offset
		D1: enable CDDIAG to report short to VCC or to Gnd fault
		D0: enable CDDIAG to report high voltage Mute fault
IB5		D7: enable CDDIAG to report undervoltage fault
		D6: enable CDDIAG to report thermal shutdown fault
		D5-4: enable CDDIAG to report PWM pulse skipping
IB6		D7-D6: establish MUTE timing setup
		D5: select audio signal gain control
		D4: choose between standard gain or low gain
IB7		D7-D6: select the diagnostic ramp time
		D5-D4: select the diagnostic hold time
		D1: choose between data generated on I²S clock falling edge or rising edge
		D0: select the current sensing protocol configuration

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FDA903D I²C protocol

IB8	D7-D6: set the full current sensing scale
	D5: turn on/off the PWM
	D4: enable the DC Diagnostic
	D3-D1: configure the I²S CR pin
	D0: put the amplifier in MUTE/PLAY
IB9	D4: enable/disable the watchdog for word select management
IB10	D7: set short load impedance threshold for DC diagnostic
	D6: set open load impedance threshold for DC diagnostic and open load in play
	D4-D3: configure the output current offset detector threshold
IB11	D5-D4: select the overcurrent protection level
	D3: select between default PWM or PWM Slow slope
IB12	D7: select between standard thermal warning or thermal warning shift - 15 °C
IB13	D6: select whether digital mute is enabled or disabled in PLAY when Start Analog Mute without
	thermal warnings occurs
IB14:	D4: set feedback on LC filter/Out
	D3-D1: configure the LC filter setup
	D0: select whether or not setup is programmed via 1²C

3.3.4DB registers in I²C

DB registers allow the microcontroller to monitor the status and operation of the power amplifier.

				Table 6. DB register map
				DB register map
	D7	D6	D5	D4	D3		D2		D1	D0
DB0		D7: indicates whether an offset at input is present
		D6: indicates whether the current offset test has ended and if it is valid
		D5: indicates whether an offset at current offset is present
		D3: indicates whether an offset at voltage offset is present
		D2: indicates whether the open load in play test has ended
		D1: indicates whether the open load in play test is valid
		Do: indicates whether an open load is present or not
DB1		D7-D4: indicates whether the thermal warning is active
		D3: indicates whether the PLL is locked

D2: indicates whether an undervoltage UVLOALL has been detected

D1: indicates whether an overvoltage shutdown has been detected

D0: indicates whether PWM pulse skipping has been detected

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Potentiometers

DB2	D7: indicates whether the DC diagnostic pulse has ended
	D6: indicates whether the DC diagnostic is valid
	D5: indicates whether the overcurrent protection has been activated
	D4: indicates when a short load on channel occurs
	D3: indicates when a short to VCC on channel occurs
	D2: indicates when a short to Gnd on channel occurs
	D1: indicates when an open load on channel occurs
	D0: indicates whether the channel is in MUTE or in PLAY
DB3	Reserved for DC Diagnostic Error codes
DB4	Register is reserved for Channel Current Sensing (1O - 8)
DB5	Register is reserved for Channel Current Sensing (7 - 0)
DB6	D7: indicates whether the high voltage mute has started
	D6: indicates whether an undervoltage UVLOVCC has been detected
	D5: indicates whether a thermal shutdown has been detected
	D4: indicates whether the analog mute is started
	D2: indicates whether the watchdog for word select occurs
	D1: indicates whether an error frame occurs

3.3.5Driver

A driver has been developed to allow the user to monitor and control the amplifier without engaging in tedious IB and DB register read and write operations associated with a task.

3.4Potentiometers

The AVAS system includes two potentiometers to help simulate the sound of a car engine: one to simulate the accelerator pedal and another to adjust the sound volume. The potentiometers are powered through two supply voltages (5V and 3.3V) from the AEK-MCU-C1MLIT1 control board via female connector CN6 or male connector CN7.

Our system uses the potentiometer as a voltage divider to obtain a manually adjustable output voltage from a fixed input voltage applied across the two ends of the potentiometer. It is formed by an insulating cylinder on which a metal wire is wound, and the two ends are connected to two terminals. One of these terminals is

connected to a sliding contact that runs the length of the cylinder. The operation is equivalent to a pair of resistors in series whose total value is constant, but individually variable according to the position of the sliding contact.

Figure 16. Linear potentiometer circuit

Considering RL an open, we have the voltage on RT2 equal to the power supply voltage of the potentiometer
multiplied by	2, and since this ratio is equal to that of LT2 (RT2 resistor length) on LT (total resistor length), we

see that the output voltage of the potentiometer is a function of the cursor position.

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Successive approximation analog-to-digital converter (SARADC)

V*L

T2

(1)

V2 = LT

It is possible to implement speed and volume control by directly relating these variables to the output voltage of a potentiometer. The analog output of the potentiometers are converted into discrete values by the SPC582B60E1 microcontroller ADCs.

3.5Successive approximation analog-to-digital converter (SARADC)

Two of the 27 SARADC channels on the AEK-MCU-C1MLIT1 control board microcontroller are used to convert the potentiometer speed and volume signals into digital quantities through the connector CN7.

Note:

These signals can also be routed through CN11.

Figure 17. Potentiometer connections

3.6Stereo mode

In order to produce stereo audio, the system requires a second AEK-AUD-D903V1 board to occupy both the left and right channels available on the I²S DATA line.

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