AN5326
Application note
AIS2DW12: ultra-low-power 3-axis accelerometer for automotive applications
This document is intended to provide usage information and application hints related to ST’s AIS2DW12 motion sensor.
The AIS2DW12 is an ultra-low-power three-axis linear accelerometer designed to address nonsafety automotive applications which leverages on the robust and mature manufacturing processes already used for the production of micromachined accelerometers.
The device has four different ultra-low-power modes, two user-selectable full scales (±2g/±4g) and is capable of measuring accelerations with output data rates from 1.6 Hz to 100 Hz.
The AIS2DW12 has an integrated 32-level first-in, first-out (FIFO) buffer allowing the user to store data in order to limit intervention by the host processor. The device includes a dedicated internal engine to process motion and acceleration detection including free-fall, motion and no-motion, wakeup, activity/inactivity and 6D/4D orientation.
The embedded self-test capability allows the user to check the functioning of the sensor in the final application.
The AIS2DW12 is available in a small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C.
AN5326 - Rev 3 - January 2021 |
www.st.com |
For further information contact your local STMicroelectronics sales office. |
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AN5326
1Pin description
Figure 1. Pin connections
Z
1
X Y
(TOPVIEW)
DIRECTION OF THE DETECTABLE
ACCELERATIONS
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<![if ! IE]> <![endif]>INT2 |
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<![if ! IE]> <![endif]>INT1 |
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1 |
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VDDIO |
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10 |
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11 |
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12 |
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SCL/SPC |
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CS |
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VDD |
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9 |
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2 |
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GND |
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8 |
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3 |
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SDO/SA0 |
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RES |
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7 |
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6 |
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5 |
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4 |
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SDA/SDI/SDO |
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<![if ! IE]> <![endif]>GND |
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<![if ! IE]> <![endif]>NC |
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(BOTTOM VIEW)
Table 1. Pin description
Pin# |
Name |
Function |
Pin status |
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1 |
SCL |
I²C serial clock (SCL) |
Default: input without internal pull-up |
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SPC |
SPI serial port clock (SPC) |
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SPI enable |
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2 |
CS |
I²C/SPI mode selection |
Default: input with internal pull-up(1) |
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(1: SPI idle mode / I²C communication enabled; |
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0: SPI communication mode / I²C disabled) |
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3 |
SDO |
SPI serial data output (SDO) |
Default: input with internal pull-up(2) |
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SA0 |
I²C less significant bit of the device address (SA0) |
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SDA |
I²C serial data (SDA) |
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4 |
SDI |
SPI serial data input (SDI) |
Default: (SDA) input without internal pull-up |
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SDO |
3-wire interface serial data output (SDO) |
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5 |
NC |
Internally not connected. Can be tied to VDD, VDDIO, or GND. |
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6 |
GND |
0 V supply |
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7 |
RES |
Connect to GND |
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8 |
GND |
0 V supply |
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9 |
VDD |
Power supply |
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10 |
VDD_IO |
Power supply for I/O pins |
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11 |
INT2 |
Interrupt pin 2. Clock input when selected in single data conversion on demand. |
Default: push-pull output forced to ground |
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12 |
INT1 |
Interrupt pin 1 |
Default: push-pull output forced to ground |
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1.In order to disable the internal pull-up on the CS pin, write '1' to the CS_PU_DISC bit in CTRL2 (21h).
2.Internal pull-up on SDO/SA0 pin cannot be disabled. Do not connect this pin to GND in low-power applications.
AN5326 - Rev 3 |
page 2/42 |
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<![endif]>3 Rev - AN5326
<![if ! IE]><![endif]>3/42 page
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Table 2. Registers |
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Register name |
Address |
Bit7 |
Bit6 |
Bit5 |
Bit4 |
Bit3 |
Bit2 |
Bit1 |
Bit0 |
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OUT_T_L |
0Dh |
TEMP3 |
TEMP2 |
TEMP1 |
TEMP0 |
0 |
0 |
0 |
0 |
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OUT_T_H(1) |
0Eh |
TEMP11 |
TEMP10 |
TEMP9 |
TEMP8 |
TEMP7 |
TEMP6 |
TEMP5 |
TEMP4 |
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WHO_AM_I(1) |
0Fh |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
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CTRL1 |
20h |
ODR3 |
ODR2 |
ODR1 |
ODR0 |
OP_MODE1 |
OP_MODE0 |
PW_MODE1 |
PW_MODE0 |
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CTRL2 |
21h |
BOOT |
SOFT_RESET |
0 |
CS_PU_DISC |
BDU |
IF_ADD_INC |
I2C_DISABLE |
SIM |
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CTRL3 |
22h |
ST2 |
ST1 |
PP_OD |
LIR |
H_LACTIVE |
0 |
SLP_MODE |
SLP_MODE_1 |
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_SEL |
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CTRL4_INT1 |
23h |
INT1_6D |
0 |
INT1_WU |
INT1_FF |
0 |
INT1_DIFF5 |
INT1_FTH |
INT1_DRDY |
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INT2_ |
INT2_ |
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INT2_ |
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CTRL5_INT2 |
24h |
SLEEP_ |
INT2_BOOT |
INT2_OVR |
INT2_DIFF5 |
INT2_FTH |
INT2_DRDY |
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SLEEP_CHG |
DRDY_T |
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STATE |
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CTRL6 |
25h |
BW_FILT1 |
BW_FILT0 |
FS1 |
FS0 |
FDS |
0 |
0 |
0 |
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OUT_T(1) |
26h |
TEMP7 |
TEMP6 |
TEMP5 |
TEMP4 |
TEMP3 |
TEMP2 |
TEMP1 |
TEMP0 |
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STATUS(1) |
27h |
FIFO_THS |
WU_IA |
SLEEP_STATE |
0 |
0 |
6D_IA |
FF_IA |
DRDY |
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OUT_X_L(1) |
28h |
X_L7 |
X_L6 |
X_L5 |
X_L4 |
X_L3(2) |
X_L2(2) |
0 |
0 |
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OUT_X_H(1) |
29h |
X_H7 |
X_H6 |
X_H5 |
X_H4 |
X_H3 |
X_H2 |
X_H1 |
X_H0 |
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OUT_Y_L(1) |
2Ah |
Y_L7 |
Y_L6 |
Y_L5 |
Y_L4 |
Y_L3(2) |
Y_L2(2) |
0 |
0 |
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OUT_Y_H(1) |
2Bh |
Y_H7 |
Y_H6 |
Y_H5 |
Y_H4 |
Y_H3 |
Y_H2 |
Y_H1 |
Y_H0 |
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OUT_Z_L(1) |
2Ch |
Z_L7 |
Z_L6 |
Z_L5 |
Z_L4 |
Z_L3(2) |
Z_L2(2) |
0 |
0 |
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OUT_Z_H(1) |
2Dh |
Z_H7 |
Z_H6 |
Z_H5 |
Z_H4 |
Z_H3 |
Z_H2 |
Z_H1 |
Z_H0 |
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FIFO_CTRL |
2Eh |
FMode2 |
FMode1 |
FMode0 |
FTH4 |
FTH3 |
FTH2 |
FTH1 |
FTH0 |
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FIFO_SAMPLES(1) |
2Fh |
FIFO_FTH |
FIFO_OVR |
Diff5 |
Diff4 |
Diff3 |
Diff2 |
Diff1 |
Diff0 |
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SIXD_THS |
30h |
4D_EN |
6D_THS1 |
6D_THS0 |
0 |
0 |
0 |
0 |
0 |
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WAKE_UP_THS |
34h |
0 |
SLEEP_ON |
WK_THS5 |
WK_THS4 |
WK_THS3 |
WK_THS 2 |
WK_THS 1 |
WK_THS 0 |
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WAKE_UP_DUR |
35h |
FF_DUR5 |
WAKE_DUR1 |
WAKE_DUR0 |
STATIONARY |
SLEEP_DUR3 |
SLEEP_DUR2 |
SLEEP_DUR1 |
SLEEP_DUR0 |
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FREE_FALL |
36h |
FF_DUR4 |
FF_DUR3 |
FF_DUR2 |
FF_DUR1 |
FF_DUR0 |
FF_THS2 |
FF_THS1 |
FF_THS0 |
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<![if ! IE]> <![endif]>AN5326 |
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<![if ! IE]> <![endif]>Registers |
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STATUS_DUP(1) |
37h |
OVR |
DRDY_T |
SLEEP_STATE_IA |
0 |
0 |
6D_IA |
FF_IA |
DRDY |
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WAKE_UP_SRC(1) |
38h |
0 |
0 |
FF_IA |
SLEEP_STATE IA |
WU_IA |
X_WU |
Y_WU |
Z_WU |
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<![if ! IE]> <![endif]>AN5326 |
SIXD_SRC(1) |
3Ah |
0 |
6D_IA |
ZH |
ZL |
YH |
YL |
XH |
XL |
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Register name |
Address |
Bit7 |
Bit6 |
Bit5 |
Bit4 |
Bit3 |
Bit2 |
Bit1 |
Bit0 |
<![if ! IE]> <![endif]>- |
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<![if ! IE]> <![endif]>3Rev |
ALL_INT_SRC(1) |
3Bh |
0 |
0 |
SLEEP_ |
6D_IA |
0 |
0 |
WU_IA |
FF_IA |
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CHANGE_IA |
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X_OFS_USR |
3Ch |
X_OFS_USR_7 |
X_OFS_USR_6 |
X_OFS_USR_5 |
X_OFS_USR_4 |
X_OFS_USR_3 |
X_OFS_USR_2 |
X_OFS_USR_1 |
X_OFS_USR_0 |
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Y_OFS_USR |
3Dh |
Y_OFS_USR_7 |
Y_OFS_USR_6 |
Y_OFS_USR_5 |
Y_OFS_USR_4 |
Y_OFS_USR_3 |
Y_OFS_USR_2 |
Y_OFS_USR_1 |
Y_OFS_USR_0 |
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Z_OFS_USR |
3Eh |
Z_OFS_USR_7 |
Z_OFS_USR_6 |
Z_OFS_USR_5 |
Z_OFS_USR_4 |
Z_OFS_USR_3 |
Z_OFS_USR_2 |
Z_OFS_USR_1 |
Z_OFS_USR_0 |
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CTRL7 |
3Fh |
DRDY_ |
INT2_ON_INT1 |
INTERRUPTS |
USR_OFF_ON |
USR_OFF_ON |
USR_OFF_W |
HP_REF_ |
LPASS_ON6D |
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PULSED |
_ENABLE |
_OUT |
_WU |
MODE |
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1.Read-only register
2.If Low-Power Mode 1 is enabled, this bit is set to 0.
<![if ! IE]> <![endif]>4/42 page |
<![if ! IE]> <![endif]>AN5326 Registers |
AN5326
3Operating modes
Four sets of operating modes have been designed to offer the customer a broad choice of noise/powerconsumption combinations.
Table 3. Accelerometer resolution
Power Mode 4 |
Power Mode 3 |
Power Mode 2 |
Power Mode 1 |
14-bit |
14-bit |
14-bit |
12-bit |
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These operating modes are selected by writing the OP_ MODE[1:0] and PW_MODE[1:0] bits in CTRL1 (20h) given in the tables below. Additional details concerning power consumption and noise in different operating modes are available in the device datasheet.
Table 4. CTRL1 register
b7 |
b6 |
b5 |
b4 |
b3 |
b2 |
b1 |
b0 |
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ODR3 |
ODR2 |
ODR1 |
ODR0 |
OP_MODE1 |
OP_MODE0 |
PW_MODE1 |
PW_MODE0 |
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Table 5. Operating mode selection |
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OP_MODE[1:0] |
Operating mode and resolution |
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00 |
Continuous mode (12/14-bit resolution) |
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01 |
Not allowed |
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10 |
Single data conversion on-demand mode (12/14-bit resolution) |
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11 |
Not allowed |
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Table 6. Power mode selection |
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PW_MODE[1:0] |
Power mode and resolution |
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00 |
Power Mode 1 (12-bit resolution) |
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01 |
Power Mode 2 (14-bit resolution) |
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10 |
Power Mode 3 (14-bit resolution) |
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11 |
Power Mode 4 (14-bit resolution) |
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AN5326 - Rev 3 |
page 5/42 |
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AN5326
3.2Continuous conversion
When bits OP_MODE[1:0] in CTRL1 (20h) are set to Continuous Mode (00b), the device is in continuous conversion and the output data rate can be selected through the ODR[3:0] bits in CTRL1 (20h).
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Table 7. Output data rate selection |
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ODR[3:0] |
Output data rate |
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0000 |
Power-down |
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0001 |
1.6 Hz (independent of power mode) |
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0010 |
12.5 Hz (independent of power mode) |
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0011 |
25 Hz (independent of power mode) |
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0100 |
50 Hz (independent of power mode) |
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0101 |
100 Hz (independent of power mode) |
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AN5326 - Rev 3 |
page 6/42 |
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AN5326
3.3Single data conversion (on-demand mode)
This mode is enabled by writing the OP_MODE[1:0] bits to ‘10' in CTRL1 (20h).
In this configuration the device waits for a trigger signal in order to generate new data according to the selected power mode PW_MODE[1:0] bits in CTRL1 (20h), after that the device immediately enters power-down.
The trigger can be:
•A rising edge on the INT2 pin (if SLP_MODE_SEL = ‘0' in register CTRL3 (22h)). In this case the user can detect the end of the conversion using the DRDY bit of the STATUS register (27h) that can also be routed to the INT1 pin by setting the INT1_DRDY bit to 1 in register CTRL4_INT1 (23h). Minimum duration of trigger signal high level is 20 ns.
•A write of SLP_MODE_1 to ‘1' in register CTRL3 (22h) (if SLP_MODE_SEL ='1' in register CTRL3 (22h)). In this case, the user can detect the end of the conversion using the DRDY bit/signal as in the previous case, or by checking when the SLP_MODE_1 bit in register CTRL3 (22h) is automatically cleared.
Figure 2. Single data conversion using INT2 as external trigger (SLP_MODE_SEL = 0)
The maximum data rate using single data conversion mode is 100 Hz and the time of conversion depends on the low-power mode selected (refer to the following table).
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Table 8. Single data conversion: typical time of conversion |
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Power mode |
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Typical time of conversion |
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(T_on) |
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Mode 1 |
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1.20 ms |
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Mode 2 |
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1.70 ms |
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Mode 3 |
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2.30 ms |
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Mode 4 |
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3.55 ms |
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Note: If the ODR[3:0] bits of the CTRL1 register are set to 0000b, the accelerometer is permanently configured in Power-down mode and no conversion can be triggered. When the single data conversion mode has to be used, the ODR[3:0] bits of the CTRL1 register must be different than 0000b.
Interrupts, embedded features and FIFO are still supported when using single data conversion mode. Also the embedded filters LPF1, LPF2 and HP are available in single data conversion (on-demand mode) with the same bandwidth and settling time of the selected low-power mode (see Section 3.4 Accelerometer bandwidth for details).
AN5326 - Rev 3 |
page 7/42 |
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AN5326
3.4Accelerometer bandwidth
The accelerometer sampling chain (Figure 3. Accelerometer filtering chain diagram) is represented by a cascade of a few blocks:
•ADC: Analog-to-digital converter
•LPF1(2): low-pass filter 1(2)
•HP: high-pass filter
•User offset: configurable values that are subtracted from the sampled data (one for each axis)
Figure 3. Accelerometer filtering chain diagram
As shown in the figure above, data can be generated using three different filter paths:
•only LPF1 (green path) : in order to select this path set BW_FILT[1:0] = 00 and FDS = 0. Additional details in Table 9. Low-pass filter 1 bandwidth.
•LPF1 + LPF2 (purple path) : in order to select this path set BW_FILT[1:0] to a value different from 00 and FDS = 0. Additional details in Table 10. Bandwidth: low-pass path.
•LPF1 + HP (blue path): these outputs are available by setting FDS = 1. Additional details in Table 11. Bandwidth: high-pass path.
Table 9. Low-pass filter 1 bandwidth
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BW_FILT[1:0] = 00 |
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Mode |
ODR selection |
Samples to discard(1) |
Cutoff [Hz] |
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Settling @95% |
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Power Mode 4 |
@ each ODR |
0 |
180 |
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Power Mode 3 |
@ each ODR |
0 |
360 |
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Power Mode 2 |
@ each ODR |
0 |
720 |
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Power Mode 1 |
@ each ODR |
0 |
3200 |
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1.The starting condition of ODR[3:0],OP_ MODE[1:0], PW_MODE[1:0] and BW_FILT[1:0] do not impact these values. The turn-on time (first sample available starting from power-down condition) is 1 / ODR.
AN5326 - Rev 3 |
page 8/42 |
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AN5326
Accelerometer bandwidth
Table 10. Bandwidth: low-pass path
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BW_FILT[1:0] = 01 |
BW_FILT[1:0] = 10 |
BW_FILT[1:0] = 11 |
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Mode |
ODR selection |
Samples to |
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Samples to discard(1) |
Cutoff |
Samples to discard(1) |
Cutoff |
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discard(1) |
Cutoff [Hz] |
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Settling @95% |
[Hz] |
Settling @95% |
[Hz] |
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Settling @95% |
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PW Mode 4 |
@ each ODR |
1 |
ODR/4 |
5 |
ODR/10 |
11 |
ODR/20 |
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PW Mode 3 |
@ each ODR |
1 |
ODR/4 |
5 |
ODR/10 |
11 |
ODR/20 |
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PW Mode 2 |
@ each ODR |
1 |
ODR/4 |
5 |
ODR/10 |
11 |
ODR/20 |
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PW Mode 1 |
@ each ODR |
1 |
ODR/4 |
5 |
ODR/10 |
11 |
ODR/20 |
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1.The starting condition of ODR[3:0], OP_MODE[1:0], PW_MODE[1:0] and BW_FILT[1:0] do not impact these values.
Table 11. Bandwidth: high-pass path
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BW_FILT[1:0] = 01 / 00 |
BW_FILT[1:0] = 10 |
BW_FILT[1:0] = 11 |
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Mode |
ODR selection |
Samples to |
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Samples to discard(1) |
Cutoff |
Samples to discard(1) |
Cutoff |
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discard(1) |
Cutoff [Hz] |
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Settling @95% |
[Hz] |
Settling @95% |
[Hz] |
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Settling @95% |
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PW Mode 4 |
@ each ODR |
1 |
ODR/4 |
5 |
ODR/10 |
11 |
ODR/20 |
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PW Mode 3 |
@ each ODR |
1 |
ODR/4 |
5 |
ODR/10 |
11 |
ODR/20 |
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PW Mode 2 |
@ each ODR |
1 |
ODR/4 |
5 |
ODR/10 |
11 |
ODR/20 |
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PW Mode 1 |
@ each ODR |
1 |
ODR/4 |
5 |
ODR/10 |
11 |
ODR/20 |
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1.The starting condition of ODR[3:0], OP_MODE[1:0], PW_MODE[1:0] and BW_FILT[1:0] do not impact these values.
Setting USR_OFF_ON_OUT = 1 in CTRL7 does not change the bandwidth of the system. In this configuration, the values written in registers X_OFS_USR, Y_OFS_USR, Z_OFS_USR are subtracted from the respective axis. The offset values are signed values (two's complement).
The weight of the bits in registers X_OFS_USR, Y_OFS_USR, Z_OFS_USR is defined through the USR_OFF_W bit in CTRL7.
AN5326 - Rev 3 |
page 9/42 |
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AN5326
3.5High-pass filter configuration
The AIS2DW12 provides an embedded high-pass filtering capability to easily delete the DC component of the measured acceleration. As shown in Figure 3. Accelerometer filtering chain diagram, through the FDS bit in register CTRL6 the user can route the filter outputs to the output registers.
It is also possible to independently apply the filter to the embedded function data (Figure 6. Embedded functions in Section 5 Interrupt generation and embedded functions). This means that it is possible to get filtered data while the interrupt generation works on unfiltered data.
The high-pass filter can be configured in reference mode by setting the HP_REF_MODE bit in the CTRL7 register to 1. In this configuration the output data is calculated as the difference between the measured acceleration and the output values captured when reference mode was enabled. In this way only the difference is applied without any filtering.
As an example, this feature can be combined with the wake-up functionality described in Section 5.4 in order to detect when the device is displaced with respect to a specific orientation, i.e. the orientation of the device when the HP_REF_MODE bit was set to 1. When the output acceleration exceeds the wake-up threshold defined by the WK_THS[5:0] bits in the WAKE_UP_THS register for a duration longer than the one defined by the
WAKE_DUR[1:0] bits in the WAKE_UP_DUR register, an interrupt is generated. If the device is moved back to the original reference orientation, the interrupt is deactivated.
Figure 4. High-pass filter in normal and reference mode
AN5326 - Rev 3 |
page 10/42 |
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AN5326
4Reading output data
Once the device is powered up, it automatically downloads the calibration coefficients from the embedded non-volatile memory to the internal registers. When the boot procedure is completed, i.e. after approximately
20 milliseconds, the accelerometer automatically enters power-down. The default status of the pins with both VDD and VDDIO "on" is indicated in Table 1. Pin description.
Note: VDD cannot be lower than VDDIO. VDD = 0 V and VDDIO "on" is allowed: when this power supply configuration is applied, an internal pull-up is applied also to the SDA and SCL pins (the other pins maintain the default status indicated in Table 1).
To turn on the accelerometer and gather acceleration data, it is necessary to select one of the operating modes through the CTRL1 register.
Refer to Section 3 Operating modes for a detailed description of data generation.
The device is provided with a STATUS register which can be polled to check when a new set of data is available. The DRDY bit is set to 1 when a new set of data is available from the accelerometer output.
The read operations should be performed as follows:
1.Read STATUS
2.If DRDY = 0, then go to 1
3.Read OUT_X_L
4.Read OUT_X_H
5.Read OUT_Y_L
6.Read OUT_Y_H
7.Read OUT_Z_L
8.Read OUT_Z_H
9.Data processing
10.Go to 1
4.3Using the data-ready signal
The device can be configured to have one hardware signal to determine when a new set of measurement data is available to be read.
The data-ready signal is derived from the DRDY bit of the STATUS register. The signal can be driven to the INT1 pin by setting the INT1_DRDY bit of the CTRL4_INT1 register to 1 and to the INT2 pin by setting the INT2_DRDY bit of the CTRL5_INT2 register to 1.
The data-ready signal rises to 1 when a new set of data has been measured and is available to be read. In DRDY latched mode (DRDY_PULSED bit = 0 in CTRL7 register), which is the default condition, the signal gets reset when the higher part of one of the channels has been read (29h, 2Bh, 2Dh). In DRDY pulsed mode (DRDY_PULSED = 1) the pulse duration can vary between 105 μs and 175 μs. Pulsed mode is not applied to the DRDY bit which is always latched.
AN5326 - Rev 3 |
page 11/42 |
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AN5326
Figure 5. Data-ready signal
4.4Using the block data update (BDU) feature
If reading the accelerometer data is particularly slow and cannot be synchronized (or it is not required) with either the DRDY event bit in the STATUS register or with the DRDY signal driven to the INT1/INT2 pins, it is strongly recommended to set the BDU (block data update) bit to 1 in the CTRL2 (21h) register.
This feature avoids reading values (most significant and least significant parts of output data) related to different samples. In particular, when the BDU is activated, the data registers related to each channel always contain the most recent output data produced by the device, but, in case the read of a given pair (i.e. OUT_X_H and OUT_X_L, OUT_Y_H and OUT_Y_L, OUT_Z_H and OUT_Z_L) is initiated, the refresh for that pair is blocked until both MSB and LSB parts of the data are read.
Note: BDU only guarantees that the LSB part and MSB part of one data channel have been sampled at the same moment. For example, if the reading speed is too slow, X and Y can be read at T1 and Z sampled at T2.
The measured acceleration data are sent to the OUT_X_H, OUT_X_L, OUT_Y_H, OUT_Y_L, OUT_Z_H, and OUT_Z_L registers. These registers contain, respectively, the most significant part and the least significant part of the acceleration signals acting on the X, Y, and Z axes.
The complete output data for the X, Y, Z channels is given by the concatenation OUT_X_H & OUT_X_L, OUT_Y_H & OUT_Y_L , OUT_Z_H & OUT_Z_L.
Acceleration data is represented as 16-bit numbers, left-aligned and encoded in two’s complement. These values (LSB) have different resolution according to the selected operating mode.
After calculating the LSB, it must be multiplied by the proper sensitivity parameter to obtain the corresponding value in mg.
Table 12. Sensitivity
Full Scale |
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Sensitivity [mg/LSB] |
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12-bit format |
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14-bit format |
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±2 g |
0.976 |
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0.244 |
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±4 g |
1.952 |
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0.488 |
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AN5326 - Rev 3 |
page 12/42 |
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AN5326
Understanding output data
Below is a simple example of how to use the LSB data and transform it into mg.
The values are given under the hypothesis of ideal device calibration (i.e., no offset, no gain error, etc.). Get raw data from the sensor in 14-bit power mode at ±2 g:
OUT_X_L: 60h
OUT_X_H: FDh
OUT_Y_L: 78h
OUT_Y_H: 00h
OUT_Z_L: FCh
OUT_Z_H: 42h
Do register concatenation:
OUT_X_H & OUT_X_L: FD60h
OUT_Y_H & OUT_Y_L: 0078h
OUT_Z_H & OUT_Z_L: 42FCh
Apply sensitivity (e.g., 14-bit resolution, 0.244 at full scale ±2 g):
X:-672 / 4 * 0.244 = -41 mg
Y:+120 / 4 * 0.244 = +7 mg
Z:+17148 / 4 * 0.244 = +1046 mg
AN5326 - Rev 3 |
page 13/42 |
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