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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT670
4 x 4 register file; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
FEATURES
• Simultaneous and independent read and write
operations
• Expandable to almost any word size and bit length
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT670 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT670 are 16-bit 3-state register files
organized as 4 words of 4 bits each. Separated read and
write address inputs (R
, RBand WA,WB) and enable
A
inputs (RE andWE) are available, permitting simultaneous
writing into one word location and reading from another
location. The 4-bit word to be stored is presented to four
data inputs (D0 to D3). The WA and WB inputs determine
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
the location of the stored word. When the WE input is
LOW, the data is entered into the addressed location. The
addressed location remains transparent to the data while
the WE input is LOW. Data supplied at the inputs will be
read out in true (non-inverting) form from the 3-state
outputs (Q0 to Q3). Dnand Wninputs are inhibited when
WE is HIGH.
Direct acquisition of data stored in any of the four registers
is made possible by individual read address inputs
(RAand RB). The addressed word appears at the four
outputs when the RE is LOW. Data outputs are in the high
impedance OFF-state when RE is HIGH. This permits
outputs to be tied together to increase the word capacity to
very large numbers.
Design of the read enable signals for the stacked devices
must ensure that there is no overlap in the LOW levels
which would cause more than one output to be active at
the same time. Parallel expansion to generate n-bit words
is accomplished by driving the enable and address inputs
of each device in parallel.
SYMBOL PARAMETER CONDITIONS
t
PHL
C
C
/ t
I
PD
propagation delay Dn to Q
PLH
n
CL= 15 pF; VCC= 5 V 23 23 ns
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 122 124 pF
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to VCC;
for HCT the condition is VI= GND to VCC−1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
TYPICAL
UNIT
HC HCT
December 1990 2
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Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
5, 4 R
8 GND ground (0 V)
10, 9, 7, 6 Q
11
12
14, 13 W
15, 1, 2, 3 D
16 V
, R
A
to Q
0
B
3
read address inputs
data outputs
RE 3-state output read enable input (active LOW)
WE write enable input (active LOW)
, W
A
to D
0
CC
B
3
write address inputs
data inputs
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol. Fig.3 IEC logic symbol. Fig.4 Functional diagram.
WRITE MODE SELECT TABLE
OPERATING
MODE
write data
INPUTS
WE D
LLL
HLH
INTERNAL
LATCHES
n
data latched H X no change
Note
1. The write address (WA and WB) to the
“internal latches” must be stable while WE is
LOW for conventional operation.
(1)
READ MODE SELECT TABLE
OPERATING
MODE
read
disabled H X Z
Notes
1. The selection of the “internal latches” by read address
(RA and RB) are not constrained by WE or RE operation.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
December 1990 3
INPUTS OUTPUT
RE INTERNAL LATCHES
L
L
L
H
(1)
Q
n
L
H
Page 4
Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
Fig.5 Logic diagram.
December 1990 4
Page 5
Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=tf= 6 ns; CL=50pF
SYMBOL PARAMETER
t
PHL
t
PHL
t
PHL
t
PZH
t
PHZ
t
THL
t
W
/ t
/ t
/ t
/ t
/ t
/ t
propagation delay
PLH
RA, RB to Q
propagation delay
PLH
WE to Q
propagation delay
PLH
Dn to Q
3-state output enable time
PZL
RE to Q
3-state output disable time
PLZ
RE to Q
output transition time 14
TLH
n
n
n
n
n
write enable pulse width
LOW
t
su
set-up time
Dn to WE
t
su
set-up time
WA, WB to WE
t
h
hold time
Dn to WE
t
h
hold time
WA, WB to WE
t
latch
latch time
WE to RA, R
B
(°C)
T
amb
74HC
min. typ. max. min. max. min. max.
58
80
16
14
60
12
10
60
12
10
5
5
5
5
5
5
100
20
17
21
17
77
28
22
74
27
22
39
14
11
47
17
14
5
4
14
5
4
3
1
1
6
2
2
0
0
0
0
0
0
28
10
8
195
39
33
250
50
43
250
50
43
150
30
26
150
30
26
60
12
10
100
20
17
75
15
13
75
15
13
5
5
5
5
5
5
125
25
21
245
49
42
315
63
54
315
63
54
190
38
33
190
38
33
75
15
13
295
59
50
375
75
64
375
75
64
225
45
38
225
45
38
90
18
15
120
24
20
90
18
15
90
18
15
5
5
5
5
5
5
150
30
26
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to +85 −40 to+125
(V)
Fig.6
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.9
4.5
6.0
Fig.9
4.5
6.0
Fig.6
4.5
6.0
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.8
4.5
6.0
December 1990 5
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Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
D
n
WE, W
W
B
R
A
R
B
RE
A
0.25
0.40
0.60
0.70
1.10
1.35
December 1990 6
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Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
PHL
t
PZH
t
PHZ
t
THL
t
W
/ t
/ t
/ t
/ t
/ t
/ t
propagation delay
PLH
RA, RB to Q
propagation delay
PLH
WE to Q
propagation delay
PLH
Dn to Q
3-state output enable time
PZL
RE to Q
3-state output disable time
PLZ
RE to Q
output transition time 5 12 15 18 ns 4.5 Fig.6
TLH
n
n
n
n
n
write enable pulse width
LOW
t
su
set-up time
Dn to WE
t
su
set-up time
WA, WB to WE
t
h
hold time
Dn to WE
t
h
hold time
WA, WB to WE
t
latch
latch time
WE to RA, R
B
T
amb
(°C)
TEST CONDITIONS
74HCT
UNIT
V
(V)
CC
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
21 40 50 60 ns 4.5 Fig.6
28 50 63 75 ns 4.5 Fig.7
27 50 63 75 ns 4.5 Fig.7
18 35 44 53 ns 4.5 Fig.9
19 35 44 53 ns 4.5 Fig.9
18 9 23 27 ns 4.5 Fig.8
12 4 15 18 ns 4.5 Fig.8
12 −2 15 18 ns 4.5 Fig.8
5 −1 5 5 ns 4.5 Fig.8
5 0 5 5 ns 4.5 Fig.8
25 11 31 38 ns 4.5 Fig.8
December 1990 7
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Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.6 Waveforms showing the read address input
(RA, RB) to output (Qn) propagation delays
and output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
The shaded areas indicate when the input is permitted
to change for predictable output performance.
The time allowed for the internal output of the latch to
assume the state of the new data (t
only when attempting to read from a location
immediately after that location has received new data.
This parameter is measured from the falling edge of
WE to the rising edge of RA or RB, RE must be LOW.
= 1.3 V; VI= GND to 3 V.
M
) is important
latch
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.7 Waveforms showing the write enable input
(WE) and data input (Dn) to output (Qn)
propagation delays, and the write enable
pulse width.
Fig.8 Waveforms showing the write address input (WA, WB) and data input (Dn) to write enable (WE) set-up,
hold and latch times.
December 1990 8
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Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.9 Waveforms showing the read enable (RE) to output (Qn) enable and disable times, and the read enable
pulse width.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 9
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