The M27C256B is a 256 Kbit EPROM offered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited for microprocessor systems and is
organized as 32,768 by 8 bits.
The FDIP28W (window ceramic frit-seal package) has a transparent lid which allows the
user to expose the chip to ultra viol et light to er ase the bit pattern. A ne w pattern can then be
written to the device by following the programming procedure.
For applications where the content is programmed only one time and erasure is not
required, the M27C256B is offered in PDIP28 and PLCC32 packages.
In order to meet environmental requirements, ST offers the M27C256B in ECOPACK®
packages.
ECOPACK packages are Lead-free. The category of second Level Interconnect is marked
on the package and on the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1.Logic diagram
V
15
A0-A14Q0-Q7
E
G
V
CC
M27C256B
V
PP
SS
8
AI00755B
5/24
Page 6
Summary descriptionM27C256B
Table 1.Signal names
A0-A14Address Inputs
Q0-Q7Data Outputs
E
Chip Enable
G
V
PP
V
CC
V
SS
Output Enable
Program Supply
Supply Voltage
Ground
NCNot Connected Internally
DUDon’t Use
Figure 2.DIP connections
1
V
PP
A12
Q0
Q2
SS
A7
A6
A5
A4
A3
A2
A1
A0
2
3
4
5
6
7
M27C256B
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI00756
V
CC
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V
6/24
Page 7
M27C256BSummary description
Figure 3.LCC connections
PP
CC
A13
DU
32
A14
V
A8
A9
A11
NC
G
25
A10
E
Q7
Q6
A6
A5
A4
A3
A2
A1
A0
NC
Q0
9
A7
A12
M27C256B
V
1
17
Q1
Q2
V
SS
DU
Q3
Q4
Q5
AI00757
7/24
Page 8
Device operationM27C256B
2 Device operation
The operating modes of the M27C256B are listed in the Operating Modes. A single power
supply is required in the read mode. All inputs are TTL lev els except for V
for Electronic Signature.
2.1 Read mode
The M27C256B has two control functions, both of which must be logically active in order to
obtain data at the outputs. Chip Enable (E
device selection. Out put Enable (G
the output pins, independent of device selection. Assuming that the addresses are stable,
the address access time (t
available at the output after delay of t
been low and the addresses have been stable for at least t
2.2 Standby mode
The M27C256B has a standby mode which reduces the supply current from 30mA to
100µA. The M27C256B is placed in the standb y mode by applying a CMOS high signal to
the E
input. When in the standby mode, t he outputs are in a high impedance state,
independent of the G
input.
) is the power control and should be u sed for
) is the output control and should be used to gate data to
) is equal to the delay from E to output (t
AVQV
from the falling edge of G, assuming that E has
GLQV
AVQV-tGLQV
and 12V on A9
PP
). Data is
ELQV
.
2.3 Two-line output control
Because EPROMs are usually used in larger memory arrays, this product features a 2 line
control function which accommodates the use of multiple memory connection. The two line
control function allows:
●the lowest possible memory power dissipation,
●complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E
primary device selecting function, while G
devices in the array and connected to the READ
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is desired from a particular memory device.
should be decoded and used as the
should be made a common connection to all
line from the system control bus. This
8/24
Page 9
M27C256BDevice operation
2.4 System considerations
The power switch ing characteristics of Adv ance CMOS EPROMs r equire careful decoupling
of the devices. The supply cu rrent, I
, has three segments that are of interest to the system
CC
designer: the standby current level, the active current level, and transient current peaks th at
are produced by the falling and rising edges of E
. The magnitude of this transient current
peaks is dependent on the capacitive and inductive loading of the device at the output. The
associated transient voltage p eaks can be suppressed b y complying with the two line outp ut
control and by properly selected decoupling capacitors. It is recommended that a 0.1µF
ceramic capacitor be used on every device between V
and VSS. This should be a high
CC
frequency capacitor of low inherent indu cta nce and sho uld b e placed a s clo se to the d evice
as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between V
V
for e very eight devices. The bulk capacitor should be located near the power supply
SS
CC
and
connection point. The purpose of the bulk capacitor is t o o vercome the voltage drop caused
by the inductive effects of PCB traces.
2.5 Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27C256B are in the
"1" state. Data is introduced by selectively programming "0"s into the desired bit locations.
Although only "0"s will be programmed, both "1"s and "0"s can be present in the data word.
The only way to change a ' 0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The
M27C256B is in the programming mode when V
pulsed to V
. The data to be programmed is applied to 8 bits in parallel to the data output
IL
pins. The levels required for the address and data inputs are TTL. V
6.25V ± 0.25 V.
input is at 12.75V, G is at VIH and E is
PP
is specified to be
CC
2.6 PRESTO II programming algorithm
PRESTO II Programming Algorithm allows to program the whole array with a guaranteed
margin, in a typical time of 3.5 seconds. Programming with PRESTO II involves the
application of a sequence of 100µs program pulses to each b yte un til a correct verify occurs
(see Figure 4.). During programming and verify operation, a MARGIN MODE circuit is
automatically activated in order to guarantee that each cell is programmed with enough
margin. No overprogram pulse is applied since the verify in MARGIN MODE provides
necessary margin to each programmed cell.
9/24
Page 10
Device operationM27C256B
Figure 4.Programming flowchart
VCC = 6.25V, VPP = 12.75V
n = 0
E = 100µs Pulse
NO
NO
VERIFY
YES
Last
NO
Addr
YES
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
++ Addr
AI00760B
YES
++n
= 25
FAIL
2.7 Program inhibit
Programming of multiple M27C256Bs in parallel with different data is also easily
accomplished. Except for E
, all like inputs including G of the parallel M27C256B may be
common. A TTL low level pulse applied to a M27C256B's E
program that M27C256B. A high level E
programmed.
2.8 Program Verify
A verify (read) should be performed on the programmed bits to determine that they were
correctly programmed. The v erify is accomplished with G
V
at 6.25V.
CC
2.9 Electronic signature
The Electronic Signature (ES) mode allows the reading out of a binary code from an
EPROM that will identify its manufacturer and type. This mode is intended for use by
programming equipment to automatically match the device to be programmed with its
corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C
ambient temperature range t hat is required when programming the M27C256B. To activate
the ES mode, the progr amm ing e qui pme nt must force 11.5V to 12.5V on address line A9 of
the M27C256B, with V
device outputs by toggling address line A0 from V
held at V
during Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer
IL
code and byte 1 (A0 = V
M27C256B, these two ident ifier bytes are given in Table 3 and can be read-out on outputs
Q7 to Q0.
= VPP = 5V. Two identifier bytes may then be sequenced from the
CC
) the device identifier code. For the STMicroelectronics
IH
input, with VPP at 12.75V, will
input inhibits the other M27C256Bs from being
at VIL, E at VIH, VPP at 12.75V and
to VIH. All other address lines must be
IL
10/24
Page 11
M27C256BDevice operation
2.10 Erasure operation (applies for UV EPROM)
The erasure characteristics of the M27C256B is such that erasu re begins when the cells are
exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted
that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å
range. Research shows that constant exposure to room level fluorescent lighting could
erase a typical M27C256B in about 3 years, while it would take approximately 1 week to
cause erasure when exposed to direct sunlight. If the M27C256B is to be exposed to these
types of lighting conditions for extended periods of time, it is suggeste d that opaque labels
be put over the M27C256B window to prevent unintentional erasure. The recommended
erasure procedure for the M27C256B is exposure to short wave ultraviolet light which has
wavelength 2537Å. The integrated dose (i.e. UV intensity x exposure time) for erasure
should be a minimum of 15 W-sec/cm
15 to 20 minutes using an ultr a violet lamp with 12 000 µW/cm
should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps
have a filter on their tubes which should be removed before erasure.
Table 2.Operating modes
(1)
2
. The erasure time with this dosage is approximately
2
power rating. The M27C25 6B
ModeEGA9V
ReadV
Output DisableV
ProgramV
VerifyV
Program InhibitV
StandbyV
Electronic SignatureV
1. X = V
Table 3.Electronic signature
or VIL, VID = 12V ± 0.5V.
IH
IL
IL
PulseV
IL
IH
IH
IH
IL
V
IL
V
IH
IH
V
IL
V
IH
XVCCData Out
XVCCHi-Z
XVPPData In
XVPPData Out
XVPPHi-Z
XXVCCHi-Z
V
IL
V
ID
PP
V
CC
IdentifierA0Q7Q6Q5Q4Q3Q2Q1Q0Hex Data
Manufacturer’s
Code
Device CodeV
V
00100000 20h
IL
100011018Dh
IH
Q7-Q0
Codes
11/24
Page 12
Maximum ratingM27C256B
3 Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any ot her conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may aff ect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.Absolute maximum ratings
SymbolParameterValueUnit
T
A
T
BIAS
T
STG
V
IO
V
CC
V
A9
V
PP
1. Depends on range.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than
20ns. Maximum DC voltage on Output is V
than 20ns.
Ambient Operating Temperature
Temperature Under Bias–50 to 125°C
Storage Temperature–65 to 150°C
(2)
Input or Output Voltage (except A9)–2 to 7V
Supply Voltage–2 to 7V
(2)
A9 Voltage–2 to 13.5V
Program Supply Voltage–2 to 14V
(1)
+0.5V with possible overshoot to VCC +2V for a period less
CC
–40 to 125°C
12/24
Page 13
M27C256BDC and AC parameters
4 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 5.AC measurement conditions
High SpeedStandard
Input Rise and Fall Times≤ 10ns≤ 20ns
Input Pulse Voltages0 to 3V0.4V to 2.4V
Input and Output Timing Ref.
Voltages
1.5V0.8V and 2V
Figure 5.AC testing input output waveform
High Speed
3V
0V
Standard
2.4V
0.4V
1.5V
2.0V
0.8V
AI01822
13/24
Page 14
DC and AC parametersM27C256B
Figure 6.AC testing load circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
CL
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
OUT
AI01823B
Table 6.Capacitance
(1) (2)
SymbolParameterTest ConditionMinMaxUnit
C
C
OUT
1. Sampled only, not 100% tested.
2. (T
Table 7.Read mode DC characteristics
Input Capacitance VIN = 0V6pF
IN
Output CapacitanceV
= 25 °C, f = 1 MHz)
A
(1) (2)
= 0V12pF
OUT
SymbolParameterTest ConditionMinMaxUnit
I
V
I
LO
I
CC
I
CC1
I
CC2
I
PP
V
IH
V
Input Leakage Current0V ≤ VIN ≤ V
LI
Output Leakage Current0V ≤ V
= VIL, G = VIL,
Supply Current
E
= 0mA, f = 5MHz
I
OUT
Supply Current (Standby) TTLE = V
Supply Current (Standby)
CMOS
> VCC – 0.2V100µA
E
Program CurrentVPP = V
Input Low Voltage–0.30.8V
IL
(3)
Input High Voltage2VCC + 1V
Output Low VoltageIOL = 2.1mA0.4V
OL
OUT
≤ V
IH
CC
CC
CC
±10µA
±10µA
30mA
1mA
100µA
Output High Voltage TTLIOH = –1mA3.6V
V
OH
Output High Voltage CMOSI
1. T
= 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC.
A
must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. V
CC
3. Maximum DC voltage on Output is VCC +0.5V.
= –100µAVCC – 0.7VV
OH
14/24
Page 15
M27C256BDC and AC parameters
Table 8.Programming mode DC characteristics
(1) (2)
SymbolParameterTest ConditionMinMaxUnit
1. T
2. V
I
I
CC
I
PP
V
V
V
OL
V
OH
V
A
CC
Input Leakage CurrentVIL ≤ VIN ≤ V
LI
IH
±10µA
Supply Current50mA
Program CurrentE = V
Input Low Voltage–0.30.8V
IL
Input High Voltage2VCC + 0.5V
IH
IL
50mA
Output Low VoltageIOL = 2.1mA0.4V
Output High Voltage TTLIOH = –1mA3.6V
A9 Voltage11.512.5V
1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc) or for further information on any aspect
of this device, please contact the STMicroelectronics Sales Office nearest to you.
Package mechanical data clarified for PDIP28 (Table 13.),
PLCC32 (Table 14., Figure 11.) and TSOP28 (Table 15., Figure 13.)
Document converted to new template (sections added, information
moved).
TSOP28 package removed. Packages are ECOPACK® compliant. X
option removed from Table 15: Ordering information scheme.
23/24
Page 24
M27C256B
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