The M27C256B is a 256 Kbit EPROM offered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited for microprocessor systems and is
organized as 32,768 by 8 bits.
The FDIP28W (window ceramic frit-seal package) has a transparent lid which allows the
user to expose the chip to ultra viol et light to er ase the bit pattern. A ne w pattern can then be
written to the device by following the programming procedure.
For applications where the content is programmed only one time and erasure is not
required, the M27C256B is offered in PDIP28 and PLCC32 packages.
In order to meet environmental requirements, ST offers the M27C256B in ECOPACK®
packages.
ECOPACK packages are Lead-free. The category of second Level Interconnect is marked
on the package and on the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1.Logic diagram
V
15
A0-A14Q0-Q7
E
G
V
CC
M27C256B
V
PP
SS
8
AI00755B
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Summary descriptionM27C256B
Table 1.Signal names
A0-A14Address Inputs
Q0-Q7Data Outputs
E
Chip Enable
G
V
PP
V
CC
V
SS
Output Enable
Program Supply
Supply Voltage
Ground
NCNot Connected Internally
DUDon’t Use
Figure 2.DIP connections
1
V
PP
A12
Q0
Q2
SS
A7
A6
A5
A4
A3
A2
A1
A0
2
3
4
5
6
7
M27C256B
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI00756
V
CC
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V
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M27C256BSummary description
Figure 3.LCC connections
PP
CC
A13
DU
32
A14
V
A8
A9
A11
NC
G
25
A10
E
Q7
Q6
A6
A5
A4
A3
A2
A1
A0
NC
Q0
9
A7
A12
M27C256B
V
1
17
Q1
Q2
V
SS
DU
Q3
Q4
Q5
AI00757
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Device operationM27C256B
2 Device operation
The operating modes of the M27C256B are listed in the Operating Modes. A single power
supply is required in the read mode. All inputs are TTL lev els except for V
for Electronic Signature.
2.1 Read mode
The M27C256B has two control functions, both of which must be logically active in order to
obtain data at the outputs. Chip Enable (E
device selection. Out put Enable (G
the output pins, independent of device selection. Assuming that the addresses are stable,
the address access time (t
available at the output after delay of t
been low and the addresses have been stable for at least t
2.2 Standby mode
The M27C256B has a standby mode which reduces the supply current from 30mA to
100µA. The M27C256B is placed in the standb y mode by applying a CMOS high signal to
the E
input. When in the standby mode, t he outputs are in a high impedance state,
independent of the G
input.
) is the power control and should be u sed for
) is the output control and should be used to gate data to
) is equal to the delay from E to output (t
AVQV
from the falling edge of G, assuming that E has
GLQV
AVQV-tGLQV
and 12V on A9
PP
). Data is
ELQV
.
2.3 Two-line output control
Because EPROMs are usually used in larger memory arrays, this product features a 2 line
control function which accommodates the use of multiple memory connection. The two line
control function allows:
●the lowest possible memory power dissipation,
●complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E
primary device selecting function, while G
devices in the array and connected to the READ
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is desired from a particular memory device.
should be decoded and used as the
should be made a common connection to all
line from the system control bus. This
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