ST MICROELECTRONICS 27C160-100 Datasheet

M27C160

16 Mbit (2Mb x 8 or 1Mb x 16) UV EPROM and OTP EPROM

■ 5V ± 10% SUPPLY VOLTAGE inREAD

OPERATION

■ ACCESS TIME: 70ns

■ BYTE-WIDE or WORD-WIDE

CONFIGURABLE

■ 16 Mbit MASK ROM REPLACEMENT

■ LOW POWER CONSUMPTION

– Active Current 70mA at 8MHz
– Standby Current 100µA

■ PROGRAMMING VOLTAGE: 12.5V ± 0.25V

■ PROGRAMMING TIME: 100µs/word

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Device Code: B1h

42

1

FDIP42W (F)

42

1

PDIP42 (B)

42

1

SDIP42 (S)

DESCRIPTION

The M27C160 is a 16 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro­processor systemsrequiring large data orprogram
storage and is organised as either 2 Mbitwords of
8 bit or 1 Mbitwords of 16 bit. Thepin-out is com­patible with a 16 Mbit Mask ROM.

The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex­pose thechip to ultravioletlight toerase the bit pat­tern. A new pattern can then be written rapidly to
the device by following the programming proce­dure.

For applications where the contentis programmed
only one time and erasure is not required, the
M27C160 is offered in PDIP42, SDIP42, PLCC44
and SO44 packages.

PLCC44 (K)

Figure 1. Logic Diagram

V

CC

20

A0-A19

BYTEV

E

G

PP

M27C160

V

SS

44

1

SO44 (M)

Q15A–1

15

Q0-Q14

AI00739B

1/18July 2001

M27C160

Figure 2A. DIP Connections

A18 A19

1
2

A7

3
4

A6

5

A5
A4

6

A3

7

A2

8

A1

9

A0

10

M27C160

11
12
13
14
15
16
17
18
19
20
21

V

SS

Q0
Q8
Q1
Q9

Q10

Q3

Q11

E

G

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

AI00740

A8A17
A9
A10
A11
A12
A13
A14
A15
A16
BYTEV
V

SS

Q15A-1
Q7
Q14
Q6
Q13
Q5Q2
Q12
Q4
V

CC

PP

Figure 2B. PLCC Connections

SS

A18

A17

A7

A5

A6

A4
A3
A2
A1 A15
A0

E

12

V

SS

Q0
Q8
Q1

Q9

Q2

Q10

Q3

M27C160

23

Q11

A8

A19

V

1

44

CC

NC

V

Q4

A9

Q12

A10

Q5

A11

34

Q13

A12
A13
A14

A16
BYTEV
V

SS

Q15A–1G
Q7
Q14
Q6

AI03012

PP

Figure 2C. SO Connections

NC NC

A17 A8

V

SS

Q0
Q8

Q9

Q10

Q3

Q11

A7
A6
A5
A4
A3
A2
A1
A0

1
2
3
4
5
6
7
8
9
10
11

E

M27C160

12
13

G

14
15
16
17Q1
18
19
20
21

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322

AI01264

A19A18

A9
A10
A11
A12
A13
A14
A15
A16
BYTEV
V

SS

Q15A-1
Q7
Q14
Q6
Q13
Q5Q2
Q12
Q4
V

CC

PP

Table 1. Signal Names

A0-A19 Address Inputs
Q0-Q7 Data Outputs
Q8-Q14 Data Outputs
Q15A–1 Data Output / Address Input
E Chip Enable
G
BYTEV

PP

V

CC

V

SS

NC Not Connected Internally

Output Enable
Byte Mode / Program Supply
Supply Voltage
Ground

2/18

M27C160

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A Ambient Operating Temperature

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi­tions for extended periods mayaffect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual­ity documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V

3. Depends on range.

Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC+2V for a period less than 20ns.

CC

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E G BYTEV

Read Word-wide
Read Byte-wide Upper
Read Byte-wide Lower
Output Disable
Program

V
Verify
Program Inhibit
Standby
Electronic Signature V

Note: X = VIHor VIL,VID= 12V ± 0.5V.

V

IL

V

IL

V

IL

V

IL

Pulse V

IL

V

IH

V

IH

V

IH

IL

PP

V

IL

V

IL

V

IL

V

IH

IH

V

IL

V

IH

V

IH

V

IL

V

IL

X X Hi-Z Hi-Z Hi-Z

V

PP

V

PP

V

PP

X X X Hi-Z Hi-Z Hi-Z

V

IL

V

IH

A9 Q15A–1 Q8-Q14 Q7-Q0

X Data Out Data Out Data Out
X
X

V

IH

V

IL

Hi-Z Data Out
Hi-Z Data Out

X Data In Data In Data In
X Data Out Data Out Data Out
X Hi-Z Hi-Z Hi-Z

V

ID

Code Codes Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code
Device Code

Note: Outputs Q15-Q8 areset to ’0’.

V

IL

V

IH

00100000 20h
10110001 B1h

3/18

M27C160

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only, not 100% tested.

(1)

(TA=25°C, f= 1 MHz)

Input Capacitance (except BYTEVPP)V
Input Capacitance (BYTEV
Output Capacitance V

2.0V

0.8V

AI01822

)V

PP

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE

UNDER

TEST

C

L

CL= 30pF forHigh Speed
CL= 100pF for Standard
CLincludes JIG capacitance

=0V

IN

=0V

IN

=0V 12 pF

OUT

10 pF

120 pF

OUT

AI01823B

DEVICE OPERATION

The operating modes of the M27C160are listed in
the OperatingModes Table. Asingle powersupply
is required in the read mode. All inputs are TTL
compatible except for VPPand 12V on A9 for the
Electronic Signature.

Read Mode

The M27C160 has two organisations, Word-wide
and Byte-wide.The organisationis selected by the
signal level on the BYTEVPPpin. When BYTEV

PP

is at VIHthe Word-wide organisation is selected
and the Q15A–1 pinis used for Q15 Data Output.
When the BYTEVPPpin is at VILthe Byte-wide or­ganisation is selected and the Q15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at VILthe

4/18

lower 8bits of the 16 bit data are selected and with
A–1 at VIHthe upper 8 bits of the 16 bit data are
selected.

The M27C160 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte- wide organisation must be selected.

Chip Enable(E) is the power control and should be
used for deviceselection. Output Enable (G)is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad­dress access time (t
from E to output (t

ELQV

output after a delay of t

) is equal to the delay

AVQV

). Data is available at the

from the falling edge

GLQV

of G, assuming that E has been low and the ad­dresses have been stableforat leastt

AVQV-tGLQV

.

M27C160

Table 7. Read Mode DC Characteristics

(1)

(TA= 0 to 70 °C or –40 to 85 °C; VCC=5V±5% or 5V ± 10%; VPP=VCC)

Symbol Parameter Test Condition Min Max Unit

I

I

LO

I

CC

I

CC1

I

CC2

I

PP

V

V

IH

V

V

Note: 1. VCCmust be applied simultaneously withor before VPPand removed simultaneously or after VPP.

Input Leakage Current 0V ≤ VIN≤ V

LI

Output Leakage Current

Supply Current

Supply Current (Standby)TTL E = V
Supply Current (Standby)CMOS
Program Current
Input Low Voltage –0.3 0.8 V

IL

(2)

Input High Voltage 2
Output Low Voltage

OL

Output High Voltage TTL

OH

2. Maximum DC voltage on Output is V

CC

+0.5V.

0V ≤ V

E=V

= 0mA, f = 8MHz

I

OUT

E=V

= 0mA, f = 5MHz

I

OUT

E>V

V

PP=VCC

I

OL

I

= –400µA

OH

≤ V

OUT

,G=VIL,

IL

,G=VIL,

IL

IH

– 0.2V

CC

= 2.1mA

CC

CC

2.4 V

±1 µA

±10 µA

70 mA

50 mA

1mA

100 µA

10 µA

V

+1

CC

0.4 V

V

Standby Mode

The M27C160 has a standby mode which reduces
the active current from 50mA to 100µA. The
M27C160 is placed in the standby mode by apply­ing aCMOS highsignal to the Einput. When inthe
standby mode, the outputs are in a high imped­ance state, independent of the G input.

Two Line Output Control

Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con­trol function which accommodates the use of mul­tiple memory connection. The two line control
function allows:

a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control
lines, E should bedecoded and usedas theprima­ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect­ed memory devices are intheir low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.

System Considerations

The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current I

CC

has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges ofE.

The magnitude of the transient current peaks is
dependent on the capacitive and inductive loading
of the device outputs. The associated transient
voltage peaks can be suppressed by complying
with the two line output control andby properly se­lected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor is used on every
device between VCCand VSS. This should be a
high frequency type of low inherent inductance
and should be placed as close as possible to the
device. In addition, a 4.7µF electrolytic capacitor
should be used between VCCand VSSfor every
eight devices.

This capacitor should be mountednear the power
supply connection point. The purpose of this ca­pacitor is to overcome the voltage drop caused by
the inductive effects of PCB traces.

5/18

M27C160

Table 8. Read Mode AC Characteristics

(1)

(TA= 0 to 70 °C or –40 to 85 °C; VCC=5V±5% or 5V ± 10%; VPP=VCC)

M27C160

Symbol Alt Parameter TestCondition

t

AVQVtACC

t

BHQV

t

ELQV

t

GLQV

(2)

t

BLQZ

(2)

t

EHQZ

(2)

t

GHQZ

t

AXQX

t

BLQX

Note: 1. VCCmust be applied simultaneously withor before VPPand removed simultaneously or after V

2. Sampled only, not 100% tested.

3. Speed obtained with High Speed AC measurement conditions.

Address Validto
Output Valid

BYTE High to

t

ST

Output Valid
Chip Enable Low to

t

CE

Output Valid
Output Enable Low

t

OE

to Output Valid
BYTE Low to Output

t

STD

Hi-Z
Chip Enable High to

t

DF

Output Hi-Z
Output Enable High

t

DF

to OutputHi-Z
Address Transition

t

OH

to Output Transition
BYTE Low to

t

OH

Output Transition

E=V

,G=V

E=V

G=V

E=V

E=V

G=V

E=V

E=V

E=V

IL

IL

IL

IL

IL

IL

,G=V

IL

IL

IL

,G=V

IL

IL

IL

,G=VIL5555ns

,G=V

IL

-70

(3)

-90 -100 -120/-150

Min Max Min Max Min Max Min Max

70 90 100 120 ns

70 90 100 120 ns

70 90 100 120 ns

35 45 50 60 ns

30 30 40 50 ns

025030040050ns

025030040050ns

5555ns

Unit

PP.

Figure 5. Word-Wide Read Mode AC Waveforms

A0-A19

E

G

Q0-Q15

Note: BYTEVPP=VIH.

6/18

VALID

tAVQV

tGLQV

tELQV

VALID

tAXQX

tEHQZ

tGHQZ

Hi-Z

AI00741B