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ISM330DHCX
Application note
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STM ISM330DHCX Application note

AN5398
Application note
ISM330DHCX: always-on 3D accelerometer and 3D gyroscope with digital output
for industrial applications

Introduction

This document is intended to provide usage information and application hints related to ST’s ISM330DHCX iNEMO inertial module.
The ISM330DHCX is a system-in-package featuring a high-accuracy and high-performance 3D digital accelerometer and 3D digital gyroscope tailored for Industry 4.0 applications.
All the design aspects and the testing and calibration of the ISM330DHCX have been optimized to reach superior accuracy, stability, and extremely low noise.
The ISM330DHCX has a 3D accelerometer capable of wide bandwidth, ultra-low noise and a selectable full-scale range of ±2/±4/±8/±16 g. The 3D gyroscope has an angular rate range of ±125/±250/±500/±1000/±2000/±4000 dps and offers superior stability over temperature and time along with ultra-low noise.
The unique set of embedded features facilitates the implementation of smart and complex sensor nodes which deliver high performance at very low power:
• its capability to support up to 16 embedded finite state machines that can be programmed and run independently to detect and classify complex motion sequences.
• the embedded Machine Learning Core logic allows identifying if a data pattern matches a user-defined set of classes. A typical example of an application is the identification and detection of multiple complex motion patterns.
• the integrated smart first-in first-out (FIFO) buffer of up to 9 kbyte size allows dynamic batching of significant data (i.e. internal and external sensors, timestamp and temperature).
The ISM330DHCX is available in a small plastic land grid array (LGA) package of 2.5 x 3.0 x 0.83 mm.
AN5398 - Rev 3 - January 2021 For further information contact your local STMicroelectronics sales office.
www.st.com

1 Pin description

AN5398
Pin description
Figure 1. Pin connections
AN5398 - Rev 3
page 2/132
AN5398
- Rev 3
page 3/132
Table 1. Pin status
Pin # Name
SDO
1
SA0
2 SDx Connect to VDDIO or GND
3 SCx Connect to VDDIO or GND
INT1
INT2
(2)
(3)
4
5 Vdd_IO Power supply for I/O pins Power supply for I/O pins Power supply for I/O pins
6 GND 0 V supply 0 V supply 0 V supply
7 GND 0 V supply 0 V supply 0 V supply
8 Vdd Power supply Power supply Power supply
9
10 OCS_Aux
11 SDO_Aux
12 CS
13 SCL
14 SDA
Mode 1 function
SPI 4-wire interface serial data
output (SDO)
I²C least significant bit of the device
address (SA0)
Programmable interrupt 1 Programmable interrupt 1 Programmable interrupt 1 Default: input with pull-down. Default: input with pull-down. Default: input with pull-down.
Programmable interrupt 2 (INT2) /
Data enabled (DEN)
Connect to VDDIO or leave
unconnected
Connect to VDDIO or leave
unconnected
I²C/SPI mode selection (1:SPI idle
mode / I²C communication enabled;
0: SPI communication mode / I²C
disabled)
I²C serial clock (SCL) / SPI serial port
I²C serial data (SDA) / SPI serial data
clock (SPC)
input (SDI) / 3-wire interface serial
data output (SDO)
(1)
Mode 2 function
SPI 4-wire interface serial data
output (SDO)
I²C least significant bit of the device
address (SA0)
I²C serial data master
I²C serial clock master
Programmable interrupt 2 (INT2) /
Data enabled (DEN) / I²C master
external synchronization signal
(MDRDY)
Connect to VDDIO or leave
unconnected
Connect to VDDIO or leave
unconnected
I²C/SPI mode selection (1:SPI idle
mode / I²C communication enabled;
0: SPI communication mode / I²C
disabled)
I²C serial clock (SCL) / SPI serial port
I²C serial data (SDA) / SPI serial data
clock (SPC)
input (SDI) / 3-wire interface serial
data output (SDO)
1. Refer to description in Section 3.6 Connection modes.
2. INT1 must be set to '0' or left unconnected during power-on. If no interrupt signal is needed on INT1, this pin can be left unconnected.
3. If no interrupt signal is needed on INT2, this pin can be left unconnected.
(MSDA)
(MSCL)
(1)
Mode 3/4 function
SPI 4-wire interface serial data
output (SDO)
I²C least significant bit of the device
address (SA0)
Auxiliary SPI 3/4-wire interface serial data input (SDI) and SPI 3-wire serial
data output (SDO)
Auxiliary SPI 3/4-wire interface serial
port clock (SPC_Aux)
Programmable interrupt 2 (INT2) /
Data enabled (DEN)
Auxiliary SPI 3/4-wire interface
Auxiliary SPI 3-wire interface: leave
unconnected
Auxiliary SPI 4-wire interface: serial
data output (SDO_Aux)
I²C/SPI mode selection (1:SPI idle
mode / I²C communication enabled;
0: SPI communication mode / I²C
disabled)
I²C serial clock (SCL) / SPI serial port
I²C serial data (SDA) / SPI serial data
clock (SPC)
input (SDI) / 3-wire interface serial
data output (SDO)
enable
(1)
Pin status Mode 1 Pin status Mode 2 Pin status Mode 3/4
Default: input without pull-up.
Pull-up is enabled if bit SDO_PU_EN = 1
in PIN_CTRL register.
Default: input without pull-up.
Pull-up is enabled if bit SHUB_UP_EN =
1 in MASTER_CONFIG register.
Default: input without pull-up.
Pull-up is enabled if bit SHUB_UP_EN =
1 in MASTER_CONFIG register.
Default: output forced to ground. Default: output forced to ground. Default: output forced to ground.
Default: input with pull-up.
Pull-up is disabled if bit OIS_PU_DIS = 1
in PIN_CTRL register.
Default: input with pull-up.
Pull-up is disabled if bit OIS_PU_DIS = 1
in PIN_CTRL register.
Default: input with pull-up.
Pull-up is disabled if bit
I2C_disable = 1 in CTRL4_C register
and bit DEVICE_CONF = 1 in
CTRL9_XL register.
Default: input without pull-up. Default: input without pull-up. Default: input without pull-up.
Default: input without pull-up. Default: input without pull-up. Default: input without pull-up.
Pull-up is enabled if bit SDO_PU_EN = 1
Pull-up is enabled if bit SHUB_UP_EN =
Pull-up is enabled if bit SHUB_UP_EN =
Pull-up is disabled if bit OIS_PU_DIS = 1
Pull-up is disabled if bit OIS_PU_DIS = 1
Internal pull-up value is from 30 kΩ to 50 kΩ, depending on VDDIO.
Default: input without pull-up.
in PIN_CTRL register.
Default: input without pull-up.
1 in MASTER_CONFIG register.
Default: input without pull-up.
1 in MASTER_CONFIG register.
Default: input with pull-up.
in PIN_CTRL register.
Default: input with pull-up.
in PIN_CTRL register.
Default: input with pull-up.
Pull-up is disabled if bit
I2C_disable = 1 in CTRL4_C register
and bit DEVICE_CONF = 1 in
CTRL9_XL register.
Default: input without pull-up.
Pull-up is enabled if bit SDO_PU_EN = 1
in PIN_CTRL register.
Default: input without pull-up.
Pull-up is enabled if bit SHUB_UP_EN =
1 in MASTER_CONFIG register.
Default: input without pull-up.
Pull-up is enabled if bit SHUB_UP_EN =
1 in MASTER_CONFIG register.
Input without pull-up.
(regardless of the value of bit
OIS_PU_DIS in PIN_CTRL register)
Default: input without pull-up.
Pull-up is enabled if bit SIM_OIS = 1
(Aux_SPI 3-wire) in CTRL1_OIS
register and bit OIS_PU_DIS = 0 in
PIN_CTRL register.
Default: input with pull-up.
Pull-up is disabled if bit
I2C_disable = 1 in CTRL4_C register
and bit DEVICE_CONF = 1 in
CTRL9_XL register.
AN5398
AN5398 - Rev 3
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2 Registers

Table 2. Registers
Register name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
FUNC_CFG_ACCESS 01h
PIN_CTRL 02h OIS_PU_DIS SDO_PU_EN 1 1 1 1 1 1
FIFO_CTRL1 07h WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0
FIFO_CTRL2 08h STOP_ON_WTM
FIFO_CTRL3 09h BDR_GY_3 BDR_GY_2 BDR_GY_1 BDR_GY_0 BDR_XL_3 BDR_XL_2 BDR_XL_1 BDR_XL_0
FIFO_CTRL4 0Ah DEC_TS_BATCH_1 DEC_TS_BATCH_0 ODR_T_BATCH_1 ODR_T_BATCH_0 0 FIFO_MODE2 FIFO_MODE1 FIFO_MODE0
COUNTER_BDR_REG1 0Bh
COUNTER_BDR_REG2 0Ch CNT_BDR_TH_7 CNT_BDR_TH_6 CNT_BDR_TH_5 CNT_BDR_TH_4 CNT_BDR_TH_3 CNT_BDR_TH_2 CNT_BDR_TH_1 CNT_BDR_TH_0
INT1_CTRL 0Dh DEN_DRDY_flag INT1_CNT_BDR INT1_FIFO_FULL INT1_FIFO_OVR INT1_FIFO_TH INT1_BOOT INT1_DRDY _G INT1_DRDY _XL
INT2_CTRL 0Eh 0 INT2_CNT_BDR INT2_FIFO_FULL INT2_FIFO_OVR INT2_FIFO_TH INT2_DRDY _TEMP INT2_DRDY _G INT2_DRDY _XL
WHO_AM_I 0Fh 0 1 1 0 1 0 1 1
CTRL1_XL 10h ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0 FS1_XL FS0_XL LPF2_XL_EN 0
CTRL2_G 11h ODR_G3 ODR_G2 ODR_G1 ODR_G0 FS1_G FS0_G FS_125 FS_4000
CTRL3_C 12h BOOT BDU H_LACTIVE PP_OD SIM IF_INC 0 SW_RESET
CTRL4_C 13h 0 SLEEP_G INT2_on_INT1 0 DRDY _MASK I2C_disable LPF1_SEL _G 0
CTRL5_C 14h 0 ROUNDING1 ROUNDING0 0 ST1_G ST0_G ST1_XL ST0_XL
CTRL6_C 15h TRIG_EN LVL1_EN LVL2_EN XL_HM_MODE USR_OFF_W FTYPE_2 FTYPE_1 FTYPE_0
CTRL7_G 16h G_HM_MODE HP_G_EN HPM1_G HPM0_G 0 OIS_ON_EN
CTRL8_XL 17h HPCF_XL2 HPCF_XL1 HPCF_XL0
CTRL9_XL 18h DEN_X DEN_Y DEN_Z DEN_XL_G DEN_XL_EN DEN_LH DEVICE_CONF 0
CTRL10_C 19h 0 0 TIMESTAMP_EN 0 0 0 0 0
ALL_INT_SRC 1Ah
WAKE_UP_SRC 1Bh 0
TAP_SRC 1Ch 0 TAP_IA SINGLE_TAP DOUBLE_TAP TAP_SIGN X_TAP Y_TAP Z_TAP
D6D_SRC 1Dh DEN_DRDY D6D_IA ZH ZL YH YL XH XL
STATUS_REG / STATUS_SPIAux
1Eh 0 0 0 0 0
FUNC_CFG
_ACCESS
dataready_
pulsed
TIMESTAMP
_ENDCOUNT
SHUB_REG
_ACCESS
FIFO_COMPR_
RT_RN
RST_COUNTER
_BDR
0
SLEEP_
CHANGE_IA
0 0 0 0 0 0
0 ODRCHG_EN 0 UNCOPTR_RATE_1 UNCOPTR_RATE_0 WTM8
TRIG_COUNTER
_BDR
SLEEP_
CHANGE_IA
FF_IA SLEEP_STATE WU_IA X_WU Y_WU Z_WU
0 0 CNT_BDR_TH_10 CNT_BDR_TH_9 CNT_BDR_TH_8
USR_OFF_
ON_OUT
HP_REF
_MODE_XL
D6D_IA DOUBLE_TAP SINGLE_TAP WU_IA FF_IA
FASTSETTL
_MODE_XL
HP_SLOPE_XL_EN 0
TDA
/ GYRO_SETTLING
GDA
/ GDA
OIS_ON
LOW_PASS
_ON_6D
XLDA
/ XLDA
AN5398
Registers
AN5398 - Rev 3
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Register name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
OUT_TEMP_L 20h Temp7 Temp6 Temp5 Temp4 Temp3 Temp2 Temp1 Temp0
OUT_TEMP_H 21h Temp15 Temp14 Temp13 Temp12 Temp11 Temp10 Temp9 Temp8
OUTX_L_G 22h D7 D6 D5 D4 D3 D2 D1 D0
OUTX_H_G 23h D15 D14 D13 D12 D11 D10 D9 D8
OUTY_L_G 24h D7 D6 D5 D4 D3 D2 D1 D0
OUTY_H_G 25h D15 D14 D13 D12 D11 D10 D9 D8
OUTZ_L_G 26h D7 D6 D5 D4 D3 D2 D1 D0
OUTZ_H_G 27h D15 D14 D13 D12 D11 D10 D9 D8
OUTX_L_A 28h D7 D6 D5 D4 D3 D2 D1 D0
OUTX_H_A 29h D15 D14 D13 D12 D11 D10 D9 D8
OUTY_L_A 2Ah D7 D6 D5 D4 D3 D2 D1 D0
OUTY_H_A 2Bh D15 D14 D13 D12 D11 D10 D9 D8
OUTZ_L_A 2Ch D7 D6 D5 D4 D3 D2 D1 D0
OUTZ_H_A 2Dh D15 D14 D13 D12 D11 D10 D9 D8
EMB_FUNC_ STATUS_MAINPAGE
FSM_STATUS_A _MAINPAGE
FSM_STATUS_B _MAINPAGE
MLC_STATUS _MAINPAGE
STATUS_MASTER _MAINPAGE
FIFO_STATUS1 3Ah DIFF_FIFO_7 DIFF_FIFO_6 DIFF_FIFO_5 DIFF_FIFO_4 DIFF_FIFO_3 DIFF_FIFO_2 DIFF_FIFO_1 DIFF_FIFO_0
FIFO_STATUS2 3Bh FIFO_WTM_IA FIFO_OVR_IA FIFO_FULL_IA
TIMESTAMP0 40h T7 T6 T5 T4 T3 T2 T1 T0
TIMESTAMP1 41h T15 T14 T13 T12 T11 T10 T9 T8
TIMESTAMP2 42h T23 T22 T21 T20 T19 T18 T17 T16
TIMESTAMP3 43h T31 T30 T29 T28 T27 T26 T25 T24
TAP_CFG0 56h 0
TAP_CFG1 57h TAP_PRIORITY_2 TAP_PRIORITY_1 TAP_PRIORITY_0 TAP_THS_X_4 TAP_THS_X_3 TAP_THS_X_2 TAP_THS_X_1 TAP_THS_X_0
TAP_CFG2 58h
TAP_THS_6D 59h D4D_EN SIXD_THS1 SIXD_THS0 TAP_THS_Z_4 TAP_THS_Z_3 TAP_THS_Z_2 TAP_THS_Z_1 TAP_THS_Z_0
INT_DUR2 5Ah DUR3 DUR2 DUR1 DUR0 QUIET1 QUIET0 SHOCK1 SHOCK0
WAKE_UP_THS 5Bh SINGLE_ USR_OFF_ON_WU WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0
35h IS_FSM_LC 0 IS_SIGMOT IS_TILT IS_STEP_DET 0 0 0
36h IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1
37h IS_FSM16 IS_FSM15 IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9
38h IS_MLC8 IS_MLC7 IS_MLC6 IS_MLC5 IS_MLC4 IS_MLC3 IS_MLC2 IS_MLC1
39h WR_ONCE_DONE SLAVE3_NACK SLAVE2_NACK SLAVE1_NACK SLAVE0_NACK 0 0
INTERRUPTS
_ENABLE
COUNTER
_BDR_IA
INT_CLR_ ON_READ
INACT_EN1 INACT_EN0 TAP_THS_Y_4 TAP_THS_Y_3 TAP_THS_Y_2 TAP_THS_Y_1 TAP_THS_Y_0
SLEEP_STATUS
_ON_INT
SLOPE_FDS TAP_X_EN TAP_Y_EN TAP_Z_EN LIR
FIFO_OVR
_LATCHED
0 DIFF_FIFO_9 DIFF_FIFO_8
SENS_HUB
_ENDOP
AN5398
Registers
AN5398 - Rev 3
Register name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DOUBLE_TAP
WAKE_UP_DUR 5Ch FF_DUR5 WAKE_DUR1 WAKE_DUR0 WAKE_THS_W SLEEP_DUR3 SLEEP_DUR2 SLEEP_DUR1 SLEEP_DUR0
FREE_FALL 5Dh FF_DUR4 FF_DUR3 FF_DUR2 FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0
MD1_CFG 5Eh
MD2_CFG 5Fh
INTERNAL_FREQ_FINE 63h FREQ_FINE7 FREQ_FINE6 FREQ_FINE5 FREQ_FINE4 FREQ_FINE3 FREQ_FINE2 FREQ_FINE1 FREQ_FINE0
INT_OIS 6Fh INT2_DRDY_OIS LVL2_OIS DEN_LH_OIS - - 0 ST1_XL_OIS ST0_XL_OIS
CTRL1_OIS 70h 0 LVL1_OIS SIM_OIS Mode4_EN FS1_G_OIS FS0_G_OIS FS_125_OIS OIS_EN_SPI2
CTRL2_OIS 71h - - HPM1_OIS HPM0_OIS 0 FTYPE_1_OIS FTYPE_0_OIS HP_EN_OIS
CTRL3_OIS 72h FS1_XL_OIS FS0_XL_OIS
X_OFS_USR 73h X_OFS_USR_7 X_OFS_USR_6 X_OFS_USR_5 X_OFS_USR_4 X_OFS_USR_3 X_OFS_USR_2 X_OFS_USR_1 X_OFS_USR_0
Y_OFS_USR 74h Y_OFS_USR_7 Y_OFS_USR_6 Y_OFS_USR_5 Y_OFS_USR_4 Y_OFS_USR_3 Y_OFS_USR_2 Y_OFS_USR_1 Y_OFS_USR_0
Z_OFS_USR 75h Z_OFS_USR_7 Z_OFS_USR_6 Z_OFS_USR_5 Z_OFS_USR_4 Z_OFS_USR_3 Z_OFS_USR_2 Z_OFS_USR_1 Z_OFS_USR_0
FIFO_DATA_OUT_TAG 78h TAG_SENSOR_4 TAG_SENSOR_3 TAG_SENSOR_2 TAG_SENSOR_1 TAG_SENSOR_0 TAG_CNT_1 TAG_CNT_0 TAG_PARITY
FIFO_DATA_OUT_X_L 79h D7 D6 D5 D4 D3 D2 D1 D0
FIFO_DATA_OUT_X_H 7Ah D15 D14 D13 D12 D11 D10 D9 D8
FIFO_DATA_OUT_Y_L 7Bh D7 D6 D5 D4 D3 D2 D1 D0
FIFO_DATA_OUT_Y_H 7Ch D15 D14 D13 D12 D11 D10 D9 D8
FIFO_DATA_OUT_Z_L 7Dh D7 D6 D5 D4 D3 D2 D1 D0
FIFO_DATA_OUT_Z_H 7Eh D15 D14 D13 D12 D11 D10 D9 D8
INT1_SLEEP
_CHANGE
INT2_SLEEP
_CHANGE
INT1_
SINGLE_TAP
INT2_
SINGLE_TAP
INT1_WU INT1_FF
INT2_WU INT2_FF
FILTER_XL_
CONF_OIS_2
FILTER_XL_
CONF_OIS_1
INT1_
DOUBLE_TAP
INT2_
DOUBLE_TAP
FILTER_XL_
CONF_OIS_0
INT1_6D INT1_EMB_FUNC INT1_SHUB
INT2_6D INT2_EMB_FUNC INT2_TIMESTAMP
ST1_OIS ST0_OIS
ST_OIS
_CLAMPDIS
page 6/132
AN5398
Registers
AN5398 - Rev 3
page 7/132

2.1 Embedded functions registers

The table given below provides a list of the registers for the embedded functions available in the device and the corresponding addresses. Embedded functions registers are accessible when FUNC_CFG_ACCESS is set to 1 in FUNC_CFG_ACCESS register.
Table 3. Embedded functions registers
Register name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PAGE_SEL 02h PAGE_SEL3 PAGE_SEL2 PAGE_SEL1 PAGE_SEL0 0 0 0 1
EMB_FUNC_EN_A 04h 0 0 SIGN_MOTION_EN TILT_EN PEDO_EN 0 0 0
EMB_FUNC_EN_B 05h 0 0 0 MLC_EN FIFO_COMPR_EN 0 0 FSM_EN
PAGE_ADDRESS 08h PAGE_ADDR7 PAGE_ADDR6 PAGE_ADDR5 PAGE_ADDR4 PAGE_ADDR3 PAGE_ADDR2 PAGE_ADDR1 PAGE_ADDR0
PAGE_VALUE 09h PAGE_VALUE7 PAGE_VALUE6 PAGE_VALUE5 PAGE_VALUE4 PAGE_VALUE3 PAGE_VALUE2 PAGE_VALUE1 PAGE_VALUE0
EMB_FUNC_INT1 0Ah INT1_FSM_LC 0 INT1_SIG_MOT INT1_TILT
FSM_INT1_A 0Bh INT1_FSM8 INT1_FSM7 INT1_FSM6 INT1_FSM5 INT1_FSM4 INT1_FSM3 INT1_FSM2 INT1_FSM1
FSM_INT1_B 0Ch INT1_FSM16 INT1_FSM15 INT1_FSM14 INT1_FSM13 INT1_FSM12 INT1_FSM11 INT1_FSM10 INT1_FSM9
MLC_INT1 0Dh INT1_MLC8 INT1_MLC7 INT1_MLC6 INT1_MLC5 INT1_MLC4 INT1_MLC3 INT1_MLC2 INT1_MLC1
EMB_FUNC_INT2 0Eh INT2_FSM_LC 0 INT2_SIG_MOT INT2_TILT
FSM_INT2_A 0Fh INT2_FSM8 INT2_FSM7 INT2_FSM6 INT2_FSM5 INT2_FSM4 INT2_FSM3 INT2_FSM2 INT2_FSM1
FSM_INT2_B 10h INT2_FSM16 INT2_FSM15 INT2_FSM14 INT2_FSM13 INT2_FSM12 INT2_FSM11 INT2_FSM10 INT2_FSM9
MLC_INT2 11h INT2_MLC8 INT2_MLC7 INT2_MLC6 INT2_MLC6 INT2_MLC4 INT2_MLC3 INT2_MLC2 INT2_MLC1
EMB_FUNC_STATUS 12h IS_FSM_LC 0 IS_SIGMOT IS_TILT IS_STEP_DET 0 0 0
FSM_STATUS_A 13h IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1
FSM_STATUS_B 14h IS_FSM16 IS_FSM15 IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9
MLC_STATUS 15h IS_MLC8 IS_MLC7 IS_MLC6 IS_MLC5 IS_MLC4 IS_MLC3 IS_MLC2 IS_MLC1
PAGE_RW 17h EMB_FUNC_LIR PAGE_WRITE PAGE_READ 0 0 0 0 0
EMB_FUNC_FIFO_CFG 44h 0 PEDO_FIFO_EN 0 0 0 0 0 0
FSM_ENABLE_A 46h FSM8_EN FSM7_EN FSM6_EN FSM5_EN FSM4_EN FSM3_EN FSM2_EN FSM1_EN
FSM_ENABLE_B 47h FSM16_EN FSM15_EN FSM14_EN FSM13_EN FSM12_EN FSM11_EN FSM10_EN FSM9_EN
FSM_LONG_COUNTER_L 48h FSM_LC_7 FSM_LC_6 FSM_LC_5 FSM_LC_4 FSM_LC_3 FSM_LC_2 FSM_LC_1 FSM_LC_0
FSM_LONG_COUNTER_H 49h FSM_LC_15 FSM_LC_14 FSM_LC_13 FSM_LC_12 FSM_LC_11 FSM_LC_10 FSM_LC_9 FSM_LC_8
FSM_LONG_ COUNTER_CLEAR
FSM_OUTS1 4Ch P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS2 4Dh P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS3 4Eh P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS4 4Fh P_X N_X P_Y N_Y P_Z N_Z P_V N_V
4Ah 0 0 0 0 0 0
INT1_STEP_
DETECTOR
INT2_STEP_
DETECTOR
0 0 0
0 0 0
FSM_LC_
CLEARED
FSM_LC_
CLEAR
Embedded functions registers
AN5398
AN5398 - Rev 3
Register name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
FSM_OUTS5 50h P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS6 51h P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS7 52h P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS8 53h P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS9 54h P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS10 55h P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS11 56h P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS12 57h P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS13 58h P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS14 59h P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS15 5Ah P_X N_X P_Y N_Y P_Z N_Z P_V N_V
FSM_OUTS16 5Bh P_X N_X P_Y N_Y P_Z N_Z P_V N_V
EMB_FUNC_ODR_CFG_B 5Fh 0 1 0 FSM_ODR1 FSM_ODR0 0 1 1
EMB_FUNC_ODR_CFG_C 60h 0 0 MLC_ODR1 MLC_ODR0 0 1 0 1
STEP_COUNTER_L 62h STEP_7 STEP_6 STEP_5 STEP_4 STEP_3 STEP_2 STEP_1 STEP_0
STEP_COUNTER_H 63h STEP_15 STEP_14 STEP_13 STEP_12 STEP_11 STEP_10 STEP_9 STEP_8
EMB_FUNC_SRC 64h PEDO_RST_STEP 0 STEP_DETECTED
EMB_FUNC_INIT_A 66h 0 0 SIG_MOT_INIT TILT_INIT STEP_DET_INIT 0 0 0
EMB_FUNC_INIT_B 67h 0 0 0 MLC_INIT
MLC0_SRC 70h MLC0_SRC_7 MLC0_SRC_6 MLC0_SRC_5 MLC0_SRC_4 MLC0_SRC_3 MLC0_SRC_2 MLC0_SRC_1 MLC0_SRC_70
MLC1_SRC 71h MLC1_SRC_7 MLC1_SRC_6 MLC1_SRC_5 MLC1_SRC_4 MLC1_SRC_3 MLC1_SRC_2 MLC1_SRC_1 MLC1_SRC_0
MLC2_SRC 72h MLC2_SRC_7 MLC2_SRC_6 MLC2_SRC_5 MLC2_SRC_4 MLC2_SRC_3 MLC2_SRC_2 MLC2_SRC_1 MLC2_SRC_0
MLC3_SRC 73h MLC3_SRC_7 MLC3_SRC_6 MLC3_SRC_5 MLC3_SRC_4 MLC3_SRC_3 MLC3_SRC_2 MLC3_SRC_1 MLC3_SRC_0
MLC4_SRC 74h MLC4_SRC_7 MLC4_SRC_6 MLC4_SRC_5 MLC4_SRC_4 MLC4_SRC_3 MLC4_SRC_2 MLC4_SRC_1 MLC4_SRC_0
MLC5_SRC 75h MLC5_SRC_7 MLC5_SRC_6 MLC5_SRC_5 MLC5_SRC_4 MLC5_SRC_3 MLC5_SRC_2 MLC5_SRC_1 MLC5_SRC_0
MLC6_SRC 76h MLC6_SRC_7 MLC6_SRC_6 MLC6_SRC_5 MLC6_SRC_4 MLC6_SRC_3 MLC6_SRC_2 MLC6_SRC_1 MLC6_SRC_0
MLC7_SRC 77h MLC7_SRC_7 MLC7_SRC_6 MLC7_SRC_5 MLC7_SRC_4 MLC7_SRC_3 MLC7_SRC_2 MLC7_SRC_1 MLC7_SRC_0
STEP_COUNT_
DELTA_IA
STEP_OVERFLOW
FIFO_COMPR
_INIT
STEPCOUNTER
_BIT_SET
0 0 FSM_INIT
0 0
Embedded functions registers
page 8/132
AN5398
AN5398 - Rev 3

2.2 Embedded advanced features pages

The table given below provides a list of the registers for the embedded advanced features page 0. These registers are accessible when PAGE_SEL[3:0] are set to 0000b in the PAGE_SEL register.
Table 4. Embedded advanced features registers - page 0
Register name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MAG_SENSITIVITY_L BAh MAG_SENS7 MAG_SENS6 MAG_SENS5 MAG_SENS4 MAG_SENS3 MAG_SENS2 MAG_SENS1 MAG_SENS0
MAG_SENSITIVITY_H BBh MAG_SENS15 MAG_SENS14 MAG_SENS13 MAG_SENS12 MAG_SENS11 MAG_SENS10 MAG_SENS9 MAG_SENS8
MAG_OFFX_L C0h MAG_OFFX_7 MAG_OFFX_6 MAG_OFFX_5 MAG_OFFX_4 MAG_OFFX_3 MAG_OFFX_2 MAG_OFFX_1 MAG_OFFX_0
MAG_OFFX_H C1h MAG_OFFX_15 MAG_OFFX_14 MAG_OFFX_13 MAG_OFFX_12 MAG_OFFX_11 MAG_OFFX_10 MAG_OFFX_9 MAG_OFFX_8
MAG_OFFY_L C2h MAG_OFFY_7 MAG_OFFY_6 MAG_OFFY_5 MAG_OFFY_4 MAG_OFFY_3 MAG_OFFY_2 MAG_OFFY_1 MAG_OFFY_0
MAG_OFFY_H C3h MAG_OFFY_15 MAG_OFFY_14 MAG_OFFY_13 MAG_OFFY_12 MAG_OFFY_11 MAG_OFFY_10 MAG_OFFY_9 MAG_OFFY_8
MAG_OFFZ_L C4h MAG_OFFZ_7 MAG_OFFZ_6 MAG_OFFZ_5 MAG_OFFZ_4 MAG_OFFZ_3 MAG_OFFZ_2 MAG_OFFZ_1 MAG_OFFZ_0
MAG_OFFZ_H C5h MAG_OFFZ_15 MAG_OFFZ_14 MAG_OFFZ_13 MAG_OFFZ_12 MAG_OFFZ_11 MAG_OFFZ_10 MAG_OFFZ_9 MAG_OFFZ_8
MAG_SI_XX_L C6h MAG_SI_XX_7 MAG_SI_XX_6 MAG_SI_XX_5 MAG_SI_XX_4 MAG_SI_XX_3 MAG_SI_XX_2 MAG_SI_XX_1 MAG_SI_XX_0
MAG_SI_XX_H C7h MAG_SI_XX_15 MAG_SI_XX_14 MAG_SI_XX_13 MAG_SI_XX_12 MAG_SI_XX_11 MAG_SI_XX_10 MAG_SI_XX_9 MAG_SI_XX_8
MAG_SI_XY_L C8h MAG_SI_XY_7 MAG_SI_XY_6 MAG_SI_XY_5 MAG_SI_XY_4 MAG_SI_XY_3 MAG_SI_XY_2 MAG_SI_XY_1 MAG_SI_XY_0
MAG_SI_XY_H C9h MAG_SI_XY_15 MAG_SI_XY_14 MAG_SI_XY_13 MAG_SI_XY_12 MAG_SI_XY_11 MAG_SI_XY_10 MAG_SI_XY_9 MAG_SI_XY_8
MAG_SI_XZ_L CAh MAG_SI_XZ_7 MAG_SI_XZ_6 MAG_SI_XZ_5 MAG_SI_XZ_4 MAG_SI_XZ_3 MAG_SI_XZ_2 MAG_SI_XZ_1 MAG_SI_XZ_0
MAG_SI_XZ_H CBh MAG_SI_XZ_15 MAG_SI_XZ_14 MAG_SI_XZ_13 MAG_SI_XZ_12 MAG_SI_XZ_11 MAG_SI_XZ_10 MAG_SI_XZ_9 MAG_SI_XZ_8
MAG_SI_YY_L CCh MAG_SI_YY_7 MAG_SI_YY_6 MAG_SI_YY_5 MAG_SI_YY_4 MAG_SI_YY_3 MAG_SI_YY_2 MAG_SI_YY_1 MAG_SI_YY_0
MAG_SI_YY_H CDh MAG_SI_YY_15 MAG_SI_YY_14 MAG_SI_YY_13 MAG_SI_YY_12 MAG_SI_YY_11 MAG_SI_YY_10 MAG_SI_YY_9 MAG_SI_YY_8
MAG_SI_YZ_L CEh MAG_SI_YZ_7 MAG_SI_YZ_6 MAG_SI_YZ_5 MAG_SI_YZ_4 MAG_SI_YZ_3 MAG_SI_YZ_2 MAG_SI_YZ_1 MAG_SI_YZ_0
MAG_SI_YZ_H CFh MAG_SI_YZ_15 MAG_SI_YZ_14 MAG_SI_YZ_13 MAG_SI_YZ_12 MAG_SI_YZ_11 MAG_SI_YZ_10 MAG_SI_YZ_9 MAG_SI_YZ_8
MAG_SI_ZZ_L D0h MAG_SI_ZZ_7 MAG_SI_ZZ_6 MAG_SI_ZZ_5 MAG_SI_ZZ_4 MAG_SI_ZZ_3 MAG_SI_ZZ_2 MAG_SI_ZZ_1 MAG_SI_ZZ_0
MAG_SI_ZZ_H D1h MAG_SI_ZZ_15 MAG_SI_ZZ_14 MAG_SI_ZZ_13 MAG_SI_ZZ_12 MAG_SI_ZZ_11 MAG_SI_ZZ_10 MAG_SI_ZZ_9 MAG_SI_ZZ_8
MAG_CFG_A D4h 0 MAG_Y_AXIS2 MAG_Y_AXIS1 MAG_Y_AXIS0 0 MAG_Z_AXIS2 MAG_Z_AXIS1 MAG_Z_AXIS0
MAG_CFG_B D5h 0 0 0 0 0 MAG_X_AXIS2 MAG_X_AXIS1 MAG_X_AXIS0
Embedded advanced features pages
page 9/132
AN5398
AN5398 - Rev 3
The following table provides a list of the registers for the embedded advanced features page 1. These registers are accessible when PAGE_SEL[3:0] are set to 0001b in the PAGE_SEL register.
Table 5. Embedded advanced features registers - page 1
Register name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
FSM_LC_TIMEOUT_L 7Ah
FSM_LC_TIMEOUT_H 7Bh
FSM_PROGRAMS 7Ch FSM_N_PROG7 FSM_N_PROG6 FSM_N_PROG5 FSM_N_PROG4 FSM_N_PROG3 FSM_N_PROG2 FSM_N_PROG1 FSM_N_PROG0
FSM_START_ADD_L 7Eh FSM_START7 FSM_START6 FSM_START5 FSM_START4 FSM_START3 FSM_START2 FSM_START1 FSM_START0
FSM_START_ADD_H 7Fh FSM_START15 FSM_START714 FSM_START13 FSM_START12 FSM_START11 FSM_START10 FSM_START9 FSM_START8
PEDO_CMD_REG 83h 0 0 0 0
PEDO_DEB_ STEPS_CONF
PEDO_SC_DELTAT_L D0h PD_SC_7 PD_SC_6 PD_SC_5 PD_SC_4 PD_SC_3 PD_SC_2 PD_SC_1 PD_SC_0
PEDO_SC_DELTAT_H D1h PD_SC_15 PD_SC_14 PD_SC_13 PD_SC_12 PD_SC_11 PD_SC_10 PD_SC_9 PD_SC_8
MLC_MAG_ SENSITIVITY_L
MLC_MAG_ SENSITIVITY_H
84h DEB_STEP7 DEB_STEP6 DEB_STEP5 DEB_STEP4 DEB_STEP3 DEB_STEP2 DEB_STEP1 DEB_STEP0
E8h MLC_ MAG_S_7 MLC_ MAG_S_6 MLC_ MAG_S_5 MLC_ MAG_S_4 MLC_ MAG_S_3 MLC_ MAG_S_2 MLC_ MAG_S_1 MLC_ MAG_S_0
E9h MLC_ MAG_S_15 MLC_ MAG_S_14 MLC_ MAG_S_13 MLC_ MAG_S_12 MLC_ MAG_S_11 MLC_ MAG_S_10 MLC_ MAG_S_9 MLC_ MAG_S_8
FSM_LC_
TIMEOUT7
FSM_LC_
TIMEOUT15
FSM_LC_
TIMEOUT6
FSM_LC_
TIMEOUT14
FSM_LC_
TIMEOUT5
FSM_LC_
TIMEOUT13
FSM_LC_
TIMEOUT4
FSM_LC_
TIMEOUT12
FSM_LC_
TIMEOUT3
FSM_LC_
TIMEOUT11
CARRY_
COUNT_EN
FSM_LC_
TIMEOUT2
FSM_LC_
TIMEOUT10
0 0 0
FSM_LC_
TIMEOUT1
FSM_LC_
TIMEOUT9
FSM_LC_
TIMEOUT0
FSM_LC_
TIMEOUT8
page 10/132
Embedded advanced features pages
AN5398
AN5398 - Rev 3
page 11/132

2.3 Sensor hub registers

The table given below provides a list of the registers for the sensor hub functions available in the device and the corresponding addresses. The sensor hub registers are accessible when bit SHUB_REG_ACCESS is set to 1 in the FUNC_CFG_ACCESS register.
Table 6. Sensor hub registers
Register name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SENSOR_HUB_1 02h SensorHub1_7 SensorHub1_6 SensorHub1_5 SensorHub1_4 SensorHub1_3 SensorHub1_2 SensorHub1_1 SensorHub1_0
SENSOR_HUB_2 03h SensorHub2_7 SensorHub2_6 SensorHub2_5 SensorHub2_4 SensorHub2_3 SensorHub2_2 SensorHub2_1 SensorHub2_0
SENSOR_HUB_3 04h SensorHub3_7 SensorHub3_6 SensorHub3_5 SensorHub3_4 SensorHub3_3 SensorHub3_2 SensorHub3_1 SensorHub3_0
SENSOR_HUB_4 05h SensorHub4_7 SensorHub4_6 SensorHub4_5 SensorHub4_4 SensorHub4_3 SensorHub4_2 SensorHub4_1 SensorHub4_0
SENSOR_HUB_5 06h SensorHub5_7 SensorHub5_6 SensorHub5_5 SensorHub5_4 SensorHub5_3 SensorHub5_2 SensorHub5_1 SensorHub5_0
SENSOR_HUB_6 07h SensorHub6_7 SensorHub6_6 SensorHub6_5 SensorHub6_4 SensorHub6_3 SensorHub6_2 SensorHub6_1 SensorHub6_0
SENSOR_HUB_7 08h SensorHub7_7 SensorHub7_6 SensorHub7_5 SensorHub7_4 SensorHub7_3 SensorHub7_2 SensorHub7_1 SensorHub7_0
SENSOR_HUB_8 09h SensorHub8_7 SensorHub8_6 SensorHub8_5 SensorHub8_4 SensorHub8_3 SensorHub8_2 SensorHub8_1 SensorHub8_0
SENSOR_HUB_9 0Ah SensorHub9_7 SensorHub9_6 SensorHub9_5 SensorHub9_4 SensorHub9_3 SensorHub9_2 SensorHub9_1 SensorHub9_0
SENSOR_HUB_10 0Bh SensorHub10_7 SensorHub10_6 SensorHub10_5 SensorHub10_4 SensorHub10_3 SensorHub10_2 SensorHub10_1 SensorHub10_0
SENSOR_HUB_11 0Ch SensorHub11_7 SensorHub11_6 SensorHub11_5 SensorHub11_4 SensorHub11_3 SensorHub11_2 SensorHub11_1 SensorHub11_0
SENSOR_HUB_12 0Dh SensorHub12_7 SensorHub12_6 SensorHub12_5 SensorHub12_4 SensorHub12_3 SensorHub12_2 SensorHub12_1 SensorHub12_0
SENSOR_HUB_13 0Eh SensorHub13_7 SensorHub13_6 SensorHub13_5 SensorHub13_4 SensorHub13_3 SensorHub13_2 SensorHub13_1 SensorHub13_0
SENSOR_HUB_14 0Fh SensorHub14_7 SensorHub14_6 SensorHub14_5 SensorHub14_4 SensorHub14_3 SensorHub14_2 SensorHub14_1 SensorHub14_0
SENSOR_HUB_15 10h SensorHub15_7 SensorHub15_6 SensorHub15_5 SensorHub15_4 SensorHub15_3 SensorHub15_2 SensorHub15_1 SensorHub15_0
SENSOR_HUB_16 11h SensorHub16_7 SensorHub16_6 SensorHub16_5 SensorHub16_4 SensorHub16_3 SensorHub16_2 SensorHub16_1 SensorHub16_0
SENSOR_HUB_17 12h SensorHub17_7 SensorHub17_6 SensorHub17_5 SensorHub17_4 SensorHub17_3 SensorHub17_2 SensorHub17_1 SensorHub17_0
SENSOR_HUB_18 13h SensorHub18_7 SensorHub18_6 SensorHub18_5 SensorHub18_4 SensorHub18_3 SensorHub18_2 SensorHub18_1 SensorHub18_0
MASTER_CONFIG 14h
SLV0_ADD 15h slave0_add6 slave0_add5 slave0_add4 slave0_add3 slave0_add2 slave0_add1 slave0_add0 rw_0
SLV0_SUBADD 16h slave0_reg7 slave0_reg6 slave0_reg5 slave0_reg4 slave0_reg3 slave0_reg2 slave0_reg1 slave0_reg0
SLAVE0_CONFIG 17h SHUB_ODR1 SHUB_ODR0 0 0
SLV1_ADD 18h slave1_add6 slave1_add5 slave1_add4 slave1_add3 slave1_add2 slave1_add1 slave1_add0 r_1
SLV1_SUBADD 19h slave1_reg7 slave1_reg6 slave1_reg5 slave1_reg4 slave1_reg3 slave1_reg2 slave1_reg1 slave1_reg0
SLAVE1_CONFIG 1Ah 0 0 0 0
SLV2_ADD 1Bh slave2_add6 slave1_add5 slave1_add4 slave1_add3 slave1_add2 slave1_add1 slave1_add0 r_2
SLV2_SUBADD 1Ch slave2_reg7 slave2_reg6 slave2_reg5 slave2_reg4 slave2_reg3 slave2_reg2 slave2_reg1 slave2_reg0
SLAVE2_CONFIG 1Dh 0 0 0 0 BATCH_EXT Slave2_numop2 Slave2_numop1 Slave2_numop0
RST_MASTER
_REGS
WRITE_ONCE START_CONFIG
PASS_
THROUGH_MODE
SHUB_PU_EN MASTER_ON AUX_SENS_ON1 AUX_SENS_ON0
BATCH_EXT
_SENS_0_EN
BATCH_EXT
_SENS_1_EN
Slave0_numop2 Slave0_numop1 Slave0_numop0
Slave1_numop2 Slave1_numop1 Slave1_numop0
Sensor hub registers
AN5398
AN5398 - Rev 3
Register name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
_SENS_2_EN
SLV3_ADD 1Eh slave3_add6 slave3_add5 slave3_add4 slave3_add3 slave3_add2 slave3_add1 slave3_add0 r_3
SLV3_SUBADD 1Fh slave3_reg7 slave3_reg6 slave3_reg5 slave3_reg4 slave3_reg3 slave3_reg2 slave3_reg1 slave3_reg0
SLAVE3_CONFIG 20h 0 0 0 0
DATAWRITE_SLV0 21h Slave0_dataw7 Slave0_dataw6 Slave0_dataw5 Slave0_dataw4 Slave0_dataw3 Slave0_dataw2 Slave0_dataw1 Slave0_dataw0
STATUS_MASTER 22h WR_ONCE_DONE SLAVE3_NACK SLAVE2_NACK SLAVE1_NACK SLAVE0_NACK 0 0
BATCH_EXT
_SENS_3_EN
Slave3_numop2 Slave3_numop1 Slave3_numop0
SENS_HUB
_ENDOP
page 12/132
Sensor hub registers
AN5398

3 Operating modes

The ISM330DHCX provides three possible operating configurations:
• only accelerometer active and gyroscope in Power-Down or Sleep mode;
• only gyroscope active and accelerometer in Power-Down;
• both accelerometer and gyroscope active with independent ODR.
The device offers a wide VDD voltage range from 1.71 V to 3.6 V and a VDDIO range from 1.62 V to 3.6 V. The power-on sequence is not restricted: VDD/VDDIO pins can be either set to power supply level or to ground level (they must not be left floating) and no specific sequence is required for powering them on.
In order to avoid potential conflicts, during the power-on sequence it is recommended to set the lines (on the host side) connected to the device IO pins floating or connected to ground, until VDDIO is set. After VDDIO is set, the lines connected to the IO pins have to be configured according to their default status described in
Table 1. Pin status. In order to avoid an unexpected increase in current consumption, the input pins which are not
pulled-up/pulled-down must the polarized by the host.
When the VDD power supply is applied, the device performs a 10 ms (maximum) boot procedure to load the trimming parameters. After the boot is completed, both the accelerometer and the gyroscope are automatically configured in Power-Down mode. To guarantee proper power-off of the device it is recommended to maintain the duration of the VDD line to GND for at least 100 μs.
The accelerometer and the gyroscope can be configured independently. The accelerometer can be configured in four different power modes: Power-Down, Low-Power, Normal and High-Performance mode. The gyroscope can be configured in four different power modes: Power-Down, Low-Power, Normal and High-Performance mode. They are allowed to have different data rates without any limit. The gyroscope sensor can also be set to Sleep mode to reduce its power consumption.
When both the accelerometer and gyroscope are on, the accelerometer is synchronized with the gyroscope, and the data rates of the two sensors are integer multiples of each other.
Referring to the datasheet, the output data rate (ODR_XL) bits of CTRL1_XL register and the High-Performance disable (XL_HM_MODE) bit of CTRL6_C register are used to select the power mode and the output data rate of the accelerometer (Table 7. Accelerometer ODR and power mode selection).
AN5398
Operating modes
Table 7. Accelerometer ODR and power mode selection
ODR_XL [3:0]
0000 Power-Down Power-Down
1011 1.6 Hz (Low-Power) N.A.
0001 12.5 Hz (Low-Power) 12.5 Hz (High-Performance)
0010 26 Hz (Low-Power) 26 Hz (High-Performance)
0011 52 Hz (Low-Power) 52 Hz (High Performance)
0100 104 Hz (Normal mode) 104 Hz (High-Performance)
0101 208 Hz (Normal mode) 208 Hz (High-Performance)
0110 417 Hz (High-Performance) 417 Hz (High-Performance)
0111 833 Hz (High-Performance) 833 Hz (High-Performance)
1000 1.66 kHz (High-Performance) 1.66 kHz (High-Performance)
1001 3.33 kHz (High-Performance) 3.33 kHz (High-Performance)
1010 6.66 kHz (High-Performance) 6.66 kHz (High-Performance)
ODR [Hz] when
XL_HM_MODE = 1
ODR [Hz] when
XL_HM_MODE = 0
The output data rate (ODR_G) bits of the CTRL2_G register and the High-Performance disable (G_HM_MODE) bit of the CTRL7_G register are used to select the power mode and output data rate of the gyroscope sensor (Table 8. Gyroscope ODR and power mode selection).
AN5398 - Rev 3
page 13/132
Table 8. Gyroscope ODR and power mode selection
AN5398
Operating modes
ODR_G [3:0]
ODR [Hz] when
G_HM_MODE = 1
ODR [Hz] when
G_HM_MODE = 0
0000 Power-Down Power-Down
0001 12.5 Hz (Low-Power) 12.5 Hz (High-Performance)
0010 26 Hz (Low-Power) 26 Hz (High-Performance)
0011 52 Hz (Low-Power) 52 Hz (High-Performance)
0100 104 Hz (Normal mode) 104 Hz (High-Performance)
0101 208 Hz (Normal mode) 208 Hz (High-Performance)
0110 417 Hz (High-Performance) 417 Hz (High-Performance)
0111 833 Hz (High-Performance) 833 Hz (High-Performance)
1000 1.66 kHz (High-Performance) 1.66 kHz (High-Performance)
1001 3.33 kHz (High-Performance) 3.33 kHz (High-Performance)
1010 6.66 kHz (High-Performance) 6.66 kHz (High-Performance)
The following table shows the typical values of power consumption for the different operating modes.
Table 9. Power consumption
ODR [Hz]
Power-Down - - 3 μA
Sleep - 420 µA -
1.6 Hz (Low Power) 5.5 μA - -
12.5 Hz (Low Power) 11 μA 440 μA 0.47 mA
26 Hz (Low Power) 17 μA 455 μA 0.49 mA
52 Hz (Low Power) 32 μA 490 μA 0.52 mA
104 Hz (Low Power) 56 μA 550 μA 0.6 mA
208 Hz (Low Power) 105 μA 670 μA 0.7 mA
12.5 Hz (High Perf.) 360 μA 960 μA 1.2 mA
26 Hz (High Perf.) 360 μA 960 μA 1.2 mA
52 Hz (High Perf.) 360 μA 960 μA 1.2 mA
104 Hz (High Perf.) 360 μA 960 μA 1.2 mA
208 Hz (High Perf.) 360 μA 960 µA 1.2 mA
417 Hz (High Perf.) 360 μA 960 μA 1.2 mA
833 Hz (High Perf.) 360 μA 960 μA 1.2 mA
1.66 kHz (High Perf.) 360 μA 960 μA 1.2 mA
3.33 kHz (High Perf.) 360 μA 960 μA 1.2 mA
6.66 kHz (High Perf.) 360 μA 960 μA 1.2 mA
Accelerometer only
(at Vdd = 1.8 V)
Gyroscope only
(at Vdd = 1.8 V)
Combo [Acc + Gyro]
(at Vdd = 1.8 V)
AN5398 - Rev 3
page 14/132

3.1 Power-Down mode

When the accelerometer/gyroscope is in Power-Down mode, almost all internal blocks of the device are switched off to minimize power consumption. Digital interfaces (I²C and SPI) are still active to allow communication with the device. The content of the configuration registers is preserved and the output data registers are not updated, keeping the last data sampled in memory before going into Power-Down mode.

3.2 High-Performance mode

In High-Performance mode, all accelerometer/gyroscope circuitry is always on and data are generated at the data rate selected through the ODR_XL/ODR_G bits.
Data interrupt generation is active.

3.3 Normal mode

While High-Performance mode guarantees the best performance in terms of noise, Normal mode further reduces the current consumption. The accelerometer/gyroscope data reading chain is automatically turned on and off to save power. In the gyroscope device, only the driving circuitry is always on.
Data interrupt generation is active.
AN5398
Power-Down mode

3.4 Low-Power mode

Low-Power mode differs from Normal mode in the available output data rates. In Low-Power mode low-speed ODRs are enabled. Four low-speed ODRs can be chosen for the accelerometer through the ODR_XL bits: 1.6 Hz, 12.5 Hz, 26 Hz and 52 Hz. Three low-speed ODRs can be chosen for the gyroscope thorough the ODR_G bits: 12.5 Hz, 26 Hz and 52 Hz.
Data interrupt generation is active.

3.5 Gyroscope Sleep mode

While the gyroscope is in Sleep mode the circuitry that drives the oscillation of the gyroscope mass is kept active. Compared to gyroscope Power-Down, turn-on time from Sleep mode to Low-Power/Normal/High-Performance mode is drastically reduced.
If the gyroscope is not configured in Power-Down mode, it enters in Sleep mode when the Sleep mode enable (SLEEP_G) bit of CTRL4_C register is set to 1, regardless of the selected gyroscope ODR.

3.6 Connection modes

The device offers four different connection modes, described in detail in this document:
• Mode 1: it is the connection mode enabled by default; I²C slave interface or SPI (3- / 4-wire) serial interface is available.
• Mode 2: it is the sensor hub mode; I²C slave interface or SPI (3- / 4-wire) serial interface and I²C interface master for external sensor connections are available. This connection mode is described in Section 7 Mode
2 - Sensor hub mode.
• Mode 3: in addition to the primary I²C slave interface or SPI (3- / 4-wire) serial interface, an auxiliary SPI (3- / 4-wire) serial interface for external device connections (i.e. camera module) is available for the gyroscope only. This connection mode is described in Section 8 Mode 3 and Mode 4 - Auxiliary SPI modes.
• Mode 4: in addition to the primary I²C slave interface or SPI (3- / 4-wire) serial interface, an auxiliary SPI (3- / 4-wire) serial interface for external device connections is available for both gyroscope and accelerometer. This connection mode is described in Section 8 Mode 3 and Mode 4 - Auxiliary SPI modes.
AN5398 - Rev 3
page 15/132

3.7 Accelerometer bandwidth

SLOPE
FILTER
HPCF_XL[2:0]
000
001 010 … 111
SPI I2C
1
0
HP_SLOPE_XL_EN
LPF2_XL_EN
0
1
Digital HP Filter
HPCF_XL[2:0]
Digital LP Filter
LPF2
HPCF_XL[2:0]
S/D Tap
6D / 4D
0
1
LOW_PASS_ON_6D
1
0
SLOPE_FDS
Wake-up
Activity / Inactivity
Free-fall
Advanced functions
FIFO
ADC
Digital LP Filter
ODR_XL[3:0]
LPF1
ODR/2
(1)
(1)
The cut-off value of this LPF1 output is:
• ODR/2 in High -Performance mode
• 780 Hz in Low-Power / Normal mode
USER
OFFSET
0
1
USR_OFF_ON_OUT
USR_OFF_W OFS_USR[7:0]
1
0
USR_OFF_ON_WU
The accelerometer sampling chain is represented by a cascade of three main blocks: an ADC converter, a digital low-pass filter (LPF1) and the composite group of digital filters.
Figure 2. Accelerometer filtering chain (UI path) shows the accelerometer sampling chain on the UI path;
the accelerometer sampling chain active on the OIS path (when using Mode 4 configuration) is described in
Section 8 Mode 3 and Mode 4 - Auxiliary SPI modes.
The analog signal coming from the mechanical parts is converted by the ADC; then, the digital LPF1 filter provides different cutoff values based on the accelerometer mode selected:
• ODR / 2 when the accelerometer is configured in High-Performance mode;
• 780 Hz when the accelerometer is configured in Low-Power/Normal mode;
Figure 2. Accelerometer filtering chain (UI path)
AN5398
Accelerometer bandwidth
AN5398 - Rev 3
The “Advanced functions” block in the figure above refers to Pedometer, Step Detector and Step Counter, Significant Motion and Tilt functions, described in Section 6 Embedded functions, and also includes the Finite State Machine and the Machine Learning Core.
Finally, the composite group of filters composed of a low-pass digital filter (LPF2), a high-pass digital filter and a slope filter processes the digital signal.
The LPF2_XL_EN bit of CTRL1_XL register and the CTRL8_XL register can be used to configure the composite filter group and the overall bandwidth of the accelerometer filtering chain, as shown in Table 10. Accelerometer
bandwidth selection in Mode 1/2/3. Referring to this table, on the low-pass path side, the Bandwidth columns
refer to the LPF1 bandwidth if LPF2_XL_EN = 0; they refer to the LPF2 bandwidth if LPF2_XL_EN = 1. On the high-pass path side, the Bandwidth columns refer to the Slope filter bandwidth if HPCF_XL[2:0] = 000b; they refer to the HP filter bandwidth for all the other configurations.
Table 10. Accelerometer bandwidth selection in Mode 1/2/3 also provides the maximum (worst case) settling time
in terms of samples to be discarded for the various configurations of the accelerometer filtering chain.
page 16/132
Table 10. Accelerometer bandwidth selection in Mode 1/2/3
AN5398
Accelerometer bandwidth
HP_SLOPE_XL_EN LPF2_XL_EN HPCF_XL[2:0]
0 - ODR / 2 780 Hz See Table 12
000 ODR / 4 See Table 12
001 ODR / 10 10
0
(Low-pass path)
1
(High-pass path)
1. Settling time @ 99% of the final value, taking into account all output data rates and all operating mode switches
1
-
010 ODR / 20 19
011 ODR / 45 38
100 ODR / 100 75
101 ODR / 200 150
110 ODR / 400 296
111 ODR / 800 595
000 ODR / 4 (slope filter) See Table 12
001 ODR / 10 14
010 ODR / 20 19
011 ODR / 45 38
100 ODR / 100 75
101 ODR / 200 150
110 ODR / 400 296
111 ODR / 800 595
BandwidthHPBandwidth
LP
Max overall settling time (samples to be discarded)
(1)
Setting the HP_SLOPE_XL_EN bit to 0, the low-pass path of the composite filter block is selected. If the LPF2_XL_EN bit is set to 0, no additional filter is applied; if the LPF2_XL_EN bit is set to 1, the LPF2 filter is applied in addition to LPF1 and the overall bandwidth of the accelerometer chain can be set by configuring the HPCF_XL[2:0] field of the CTRL8_XL register.
The LPF2 low-pass filter can also be used in the 6D/4D functionality by setting the LOW_PASS_ON_6D bit of the CTRL8_XL register to 1.
Setting the HP_SLOPE_XL_EN bit to 1, the high-pass path of the composite filter block is selected: the HPCF_XL[2:0] field is used in order to enable, in addition to the LPF1 filter, either the Slope filter usage (when HPCF_XL[2:0] = 000b) or the digital High-Pass filter (other HPCF_XL[2:0] configurations). The HPCF_XL[2:0] field is also used to select the cutoff frequencies of the HP filter.
The high-pass filter reference mode feature is available for the accelerometer sensor: when this feature is enabled, the current X, Y, Z accelerometer sample is internally stored and subtracted from all subsequent output values. In order to enable the reference mode, both the HP_REF_MODE_XL bit and the HP_SLOPE_XL_EN bit of the CTRL8_XL register have to be set to 1, and the value of the HPCF_XL[2:0] field must be equal to 111b. When the reference mode feature is enabled, both the LPF2 filter and the HP filter are not available. The first accelerometer output data after enabling the reference mode has to be discarded.
The FASTSETTL_MODE_XL bit of CTRL8_XL register enables the accelerometer LPF2 or HPF fast-settling mode: the selected filter sets the second sample after writing this bit. This feature applies only upon device exit from Power-Down mode.
AN5398 - Rev 3
page 17/132

3.7.1 Accelerometer slope filter

ACCE
LERATION
SLOPE
Slope(tn) = [ acc(tn) - acc(t
n-1
) ] / 2
acc(tn)
acc(t
n-1
)
As shown in Figure 3. Accelerometer slope filter, the device embeds a digital slope filter, which can also be used for some embedded features such as single/double-tap recognition, wake-up detection and activity/inactivity.
The slope filter output data is computed using the following formula:
AN5398
Accelerometer turn-on/off time
slope(tn) = [ acc(tn) - acc(t
n-1
An example of a slope data signal is illustrated in the following figure.
Figure 3. Accelerometer slope filter
) ] / 2

3.8 Accelerometer turn-on/off time

The accelerometer reading chain contains low-pass filtering to improve signal-to-noise performance and to reduce aliasing effects. For this reason, it is necessary to take into account the settling time of the filters when the accelerometer power mode is switched or when the accelerometer ODR is changed.
Accelerometer chain settling time is dependent on the power mode and output data rate selected for the following configurations:
• LPF2 and HP filters disabled;
• LPF2 or HP filter enabled with ODR/4 bandwidth selection.
For these two possible configurations, the maximum overall turn-on/off in order to switch accelerometer power modes or accelerometer ODR is the one shown below in Table 11. Accelerometer turn-on/off time (LPF2 and HP
disabled) and Table 12. Accelerometer samples to be discarded
Note: accelerometer ODR timing is not impacted by power mode changes (the new configuration is effective after the completion of the current period).
AN5398 - Rev 3
page 18/132
Table 11. Accelerometer turn-on/off time (LPF2 and HP disabled)
Starting mode Target mode
Power-Down Low-Power / Normal See Table 12
Power-Down High-Performance See Table 12
Low-Power / Normal High-Performance See Table 12 + discard 1 additional sample
Low-Power / Normal Low-Power / Normal (ODR Change) See Table 12
High-Performance Low-Power / Normal See Table 12 + discard 1 additional sample
High-Performance
High-Performance
High-Performance
@ ODR < 6.66 kHz
High-Performance
@ ODR = 6.66 kHz
Low-Power / Normal / High-Performance Power-Down 1 µs
1. Settling time @ 99% of the final value
Max turn-on/off time
Discard 3 samples
Discard 3 samples
Table 12. Accelerometer samples to be discarded
AN5398
Accelerometer turn-on/off time
(1)
Target mode
Accelerometer ODR [Hz]
1.6 (Low-Power) 1 2
12.5 (Low-Power) 1 2
26 (Low-Power) 1 2
52 (Low-Power) 1 2
104 (Normal) 1 2
208 (Normal) 1 2
12.5 (High-Performance) 2 3
26 (High-Performance) 2 3
52 (High-Performance) 2 3
104 (High-Performance) 2 3
208 (High-Performance) 2 3
417 (High-Performance) 2 3
833 (High-Performance) 2 3
1667 (High-Performance) 3 3
3333 (High-Performance) 5 5
6667 (High-Performance) 11 11
Number of samples to be discarded
(LPF2 and HP filters disabled)
Number of samples to be discarded
(LPF2 or HP filter enabled @ODR/4 bandwidth)
Overall settling time if LPF2 or HP digital filters are enabled with bandwidth different from ODR/4 has been already indicated in Table 10. Accelerometer bandwidth selection in Mode 1/2/3.
When the device is configured in Mode 4, the accelerometer UI path filtering chain is not impacted by the enable/ disable of the accelerometer/gyroscope OIS path filtering chain.
AN5398 - Rev 3
page 19/132

3.9 Gyroscope bandwidth

ADC
Digital HP Filter
HP_EN_G
0
1
LPF1_SEL_G
Digital LP Filter
FTYPE[2:0]
LPF1
0
1
SPI
I2C
FIFO
Digital LP Filter
ODR_G[3:0]
LPF2
HPM[1:0]_G
The gyroscope filtering chain depends on the connection mode in use.
When Mode 1 or Mode 2 is selected, the gyroscope filtering chain configuration is the one shown in
Figure 4. Gyroscope digital chain - Mode 1 and Mode 2. It is a cascade of three filters: a selectable digital
high-pass filter (HPF), a selectable digital low-pass filter (LPF1) and a digital low-pass filter (LPF2).
Figure 4. Gyroscope digital chain - Mode 1 and Mode 2
In High-Performance mode, the digital HP filter can be enabled by setting the bit HP_EN_G of CTRL7_G register to 1. The digital HP filter cutoff frequency can be selected through the field HPM_G[1:0] of CTRL7_G register, according to the following table.
AN5398
Gyroscope bandwidth
AN5398 - Rev 3
Table 13. Gyroscope digital HP filter cutoff selection
HPM_G[1:0]
00 0.016 45
01 0.065 11
10 0.260 3
1. Settling time @ 99% of the final value
11 1.040 0.7
High-pass filter cutoff frequency [Hz]
Overall maximum settling time [s]
The digital LPF1 filter can be enabled by setting the LPF1_SEL_G bit of CTRL4_C register to 1 and its bandwidth can be selected through the field FTYPE_[2:0] of CTRL6_C register.
The digital LPF2 filter cannot be configured by the user and its cutoff frequency depends on the selected gyroscope ODR. When the gyroscope ODR is equal to 6.66 kHz, the LPF2 filter is bypassed.
The overall gyroscope bandwidth for different gyroscope ODR values and for different configurations of the LPF1_SEL_G bit of CTRL4_C register and FTYPE_[2:0] of CTRL6_C register is summarized in the following table.
Table 14. Gyroscope overall bandwidth selection
LPF1_SEL_G FTYPE[2:0] Bandwidth [Hz] (phase delay @ 20 Hz)
0 - 4.3 (-35° @ 1.3 Hz)
1 0xx 4.3 (-35° @ 1.3 Hz)
1 100 4.3 (-35° @ 1.3 Hz)
1 101 4.3 (-35° @ 1.3 Hz)
1 110 4.3 (-35° @ 1.3 Hz)
1 111 4.3 (-35° @ 1.3 Hz)
0 - 8.3 (-35° @ 2.5 Hz)
1 0xx 8.3 (-35° @ 2.5 Hz)
1 100 8.3 (-35° @ 2.5 Hz)
page 20/132
Gyroscope ODR [Hz]
12.5
26
(1)
AN5398
Gyroscope bandwidth
Gyroscope ODR [Hz] LPF1_SEL_G FTYPE[2:0] Bandwidth [Hz] (phase delay @ 20 Hz)
1 101 8.3 (-35° @ 2.5 Hz)
26
52
104
208
417
833
1667
1 110 8.3 (-35° @ 2.5 Hz)
1 111 8.3 (-35° @ 2.5 Hz)
0 - 16.7 (-35° @ 5 Hz)
1 0xx 16.7 (-36° @ 5 Hz)
1 100 16.7 (-39° @ 5 Hz)
1 101 16.9 (-43° @ 5 Hz)
1 110 13.4 (-44° @ 5 Hz)
1 111 9.8 (-49° @ 5 Hz)
0 - 33 (-35° @ 10 Hz)
1 0xx 33 (-38° @ 10 Hz)
1 100 34 (-43° @ 10 Hz)
1 101 31 (-51° @ 10 Hz)
1 110 19 (-54° @ 10 Hz)
1 111 11.6 (-64° @ 10 Hz)
0 - 67 (-35°)
1 0xx 67 (-41°)
1 100 62 (-51°)
1 101 43 (-68°)
1 110 23 (-74°)
1 111 12.2 (-93°)
0 - 133 (-18°)
1 000 133 (-23°)
1 001 128 (-25°)
1 010 112 (-28°)
1 011 134 (-21°)
1 100 86 (-34°)
1 101 48 (-51°)
1 110 24.6 (-57°)
1 111 12.4 (-76°)
0 - 267 (-9°)
1 000 222 (-14°)
1 001 186 (-16°)
1 010 140 (-20°)
1 011 260 (-12°)
1 100 96 (-25°)
1 101 49 (-43°)
1 110 25 (-48°)
1 111 12.6 (-68°)
0 - 539 (-5°)
1 000 274 (-10°)
1 001 212 (-12°)
1 010 150 (-15°)
AN5398 - Rev 3
page 21/132
ADC
Digital HP Filter
HP_EN_G
0
1
HP_EN_OIS
Digital LP Filter
FTYPE[1:0]_OIS
LPF1
1
0
SPI
I2C
FIFO
Digital LP Filter
ODR_G[3:0]
LPF2
SPI_Aux
ODR Gyro @6.6 kHz
AN5398
Gyroscope bandwidth
Gyroscope ODR [Hz] LPF1_SEL_G FTYPE[2:0] Bandwidth [Hz] (phase delay @ 20 Hz)
1 011 390 (-8°)
1 100 99 (-21°)
1667
3333
6667
1 101 50 (-38°)
1 110 25 (-44°)
1 111 12.6 (-63°)
0 - 1137 (-3°)
1 000 292 (-8°)
1 001 220 (-10°)
1 010 153 (-13°)
1 011 451 (-6°)
1 1xx Not available
0 - > 3333 (-2°)
1 000 297 (-7°)
1 001 223 (-9°)
1 010 154 (-12°)
1 011 470 (-5°)
1 1xx Not available
If Mode 3 or Mode 4 is enabled, the gyroscope digital chain becomes the one shown in Figure 5. Gyroscope
digital chain - Mode 3 and Mode 4. In this configuration, two different data chains are available:
• The User Interface (UI) chain, where the gyroscope data are provided to the primary I²C / SPI with an ODR selectable from 12.5 Hz up to 6.66 kHz.
• The Optical Image Stabilization (OIS) chain, where the gyroscope data are provided to the auxiliary SPI with an ODR fixed at 6.66 kHz.
Figure 5. Gyroscope digital chain - Mode 3 and Mode 4
In Mode 3/4, the LPF1 filter is dedicated to the OIS chain only; on the UI side, if the gyroscope is configured in High-Performance mode, the total bandwidth depends on the gyroscope ODR value, as shown in Table 15. UI
chain - gyroscope overall bandwidth selection in Mode 3/4.
AN5398 - Rev 3
page 22/132
AN5398

Gyroscope turn-on/off time

Table 15. UI chain - gyroscope overall bandwidth selection in Mode 3/4
Gyroscope ODR [Hz] Bandwidth [Hz]
12.5 4.3
26 8.3
52 16.7
104 33
208 67
417 133
833 267
1667 539
3333 1137
6667 3333
The digital HP filter is shared between the UI and OIS chains, but it can be applied to only one chain at a time:
• if the HP_EN_G bit of CTRL7_G register is set to 1, the HP filter is applied to the UI chain only, regardless of the value of the HP_EN_OIS bit of CTRL2_OIS register;
• if the HP_EN_G bit is set to 0 and the HP_EN_OIS bit is set to 1, the HP filter is applied to the OIS chain.
Note: The digital LPF1 filter is not available on the gyroscope UI chain when Mode 3/4 is enabled. The recommendation is to avoid using the LPF1 filter when Mode 3/4 is intended to be used.
A detailed description of Mode 3/4 connection modes and the gyroscope OIS chain is provided in
Section 8 Mode 3 and Mode 4 - Auxiliary SPI modes.
3.10
Gyroscope turn-on/off time
Turn-on/off time has to be considered also for the gyroscope sensor when switching its modes or when the gyroscope ODR is changed.
When the device is configured in Mode 1/2, the maximum overall turn-on/off time (with HP filter disabled) in order to switch gyroscope power modes or gyroscope ODR is the one shown in Table 16. Gyroscope turn-on/off time in
Mode 1/2 (HP disabled).
Note: The gyroscope ODR timing is not impacted by power mode changes (the new configuration is effective after the completion of the current period).
Table 16. Gyroscope turn-on/off time in Mode 1/2 (HP disabled)
Starting mode Target mode
Power-Down Sleep 70 ms
Power-Down Low-Power / Normal 70 ms + discard 1 sample
Power-Down High-Performance 70 ms + see Table 17 or Table 18
Sleep Low-Power / Normal Discard 1 sample
Sleep High-Performance See Table 17 or Table 18
Low-Power / Normal High-Performance Discard 2 samples
Low-Power / Normal Low-Power / Normal (ODR change) Discard 1 sample
High-Performance Low-Power / Normal Discard 1 sample
High-Performance High-Performance (ODR change) Discard 2 samples
Low-Power / Normal / High-Performance Power-Down
1. Settling time @ 99% of the final value
Max turn-on/off time
1 µs if both XL and Gyro in PD
300 µs if XL not in PD
(1)
AN5398 - Rev 3
page 23/132
Table 17. Gyroscope samples to be discarded in Mode 1/2 (LPF1 disabled)
Gyroscope ODR [Hz]
12.5 Hz 2
26 Hz 3
52 Hz 3
104 Hz 3
208 Hz 3
417 Hz 3
833 Hz 3
1.66 kHz 4
3.33 kHz 5
1. Settling time @ 99% of the final value
6.66 kHz 6
Table 18. Gyroscope chain settling time in Mode 1/2 (LPF1 enabled)
FTYPE[2:0]
000 3.5
001 4.8
010 6.9
011 2.1
100 11
101 22
110 30
1. Settling time @ 99% of the final value
111 60
Number of samples to be discarded
Maximum settling time @ each ODR [ms]
AN5398
Gyroscope turn-on/off time
(1)
(1)
When there is a mode change to High-Performance mode and the HP filter is enabled, or the HP filter is turned on, the HP filter settling time must be added to Table 16. Gyroscope turn-on/off time in Mode 1/2 (HP disabled). The HP filter settling time is independent from the ODR and is shown in Table 13. Gyroscope digital HP filter
cutoff selection.
When the device is configured in Mode 3 or 4, the gyroscope UI path filtering chain is not impacted by the enable/disable of the gyroscope OIS path filtering chain.
AN5398 - Rev 3
page 24/132

4 Mode 1 - Reading output data

4.1 Startup sequence

Once the device is powered up, it automatically downloads the calibration coefficients from the embedded flash to the internal registers. When the boot procedure is completed, i.e. after approximately 10 milliseconds, the accelerometer and gyroscope automatically enter Power-Down mode.
To turn on the accelerometer and gather acceleration data through the primary I²C / SPI interface, it is necessary to select one of the operating modes through the CTRL1_XL register.
The following general-purpose sequence can be used to configure the accelerorometer:
1. Write INT1_CTRL = 01h // Acc data-ready interrupt on INT1
2. Write CTRL1_XL = 60h // Acc = 417 Hz (High-Performance mode)
To turn on the gyroscope and gather angular rate data through the primary I²C / SPI interface, it is necessary to select one of the operating modes through CTRL2_G.
The following general-purpose sequence can be used to configure the gyroscope:
AN5398
Mode 1 - Reading output data
1. Write INT1_CTRL = 02h // Gyro data-ready interrupt on INT1
2. Write CTRL2_G = 60h // Gyro = 417 Hz (High-Performance mode)

4.2 Using the status register

The device is provided with a STATUS_REG register which should be polled to check when a new set of data is available. The XLDA bit is set to 1 when a new set of data is available at the accelerometer output; the GDA bit is set to 1 when a new set of data is available at the gyroscope output.
For the accelerometer (the gyroscope is similar), the read of the output registers should be performed as follows:
1. Read STATUS_REG
2. If XLDA = 0, then go to 1
3. Read OUTX_L_A
4. Read OUTX_H_A
5. Read OUTY_L_A
6. Read OUTY_H_A
7. Read OUTZ_L_A
8. Read OUTZ_H_A
9. Data processing
10. Go to 1
AN5398 - Rev 3
page 25/132

4.3 Using the data-ready signal

DATA
DRDY
DATA READ
The device can be configured to have one hardware signal to determine when a new set of measurement data is available to be read.
For the accelerometer sensor, the data-ready signal is represented by the XLDA bit of the STATUS_REG register. The signal can be driven to the INT1 pin by setting the INT1_DRDY_XL bit of the INT1_CTRL register to 1 and to the INT2 pin by setting the INT2_DRDY_XL bit of the INT2_CTRL register to 1.
For the gyroscope sensor, the data-ready signal is represented by the GDA bit of the STATUS_REG register. The signal can be driven to the INT1 pin by setting the INT1_DRDY_G bit of the INT1_CTRL register to 1 and to the INT2 pin by setting the INT2_DRDY_G bit of the INT2_CTRL register to 1.
The data-ready signal rises to 1 when a new set of data has been generated and it is available to be read. The data-ready signal can be either latched or pulsed: if the dataready_pulsed bit of the COUNTER_BDR_REG1 register is set to 0 (default value), then the data-ready signal is latched and the interrupt is reset when the higher part of one of the enabled channels is read (29h, 2Bh, 2Dh for the accelerometer; 23h, 25h, 27h for the gyroscope). If the dataready_pulsed bit of the COUNTER_BDR_REG1 register is set to 1, then the data-ready is pulsed and the duration of the pulse observed on the interrupt pins is 75 μs. Pulsed mode is not applied to the XLDA and GDA bits which are always latched.
AN5398
Using the data-ready signal
Figure 6. Data-ready signal

4.3.1 DRDY mask functionality

Setting the DRDY_MASK bit of the CTRL4_C register to 1, the accelerometer and gyroscope data-ready signals are masked until the settling of the sensor filters is completed.
When FIFO is active and the DRDY_MASK bit is set to 1, accelerometer/gyroscope invalid samples stored in FIFO can be equal to 7FFFh, 7FFEh or 7FFDh. In this way, a tag is applied to the invalid samples stored in the FIFO buffer so that they can be easily identified and discarded during data post-processing.
Note: The DRDY_MASK bit acts only on the accelerometer LPF1 digital filter settling time for every accelerometer ODR and on the gyroscope LPF2 digital filter settling time for gyroscope ODR ≤ 833 Hz.

4.4 Using the block data update (BDU) feature

If reading the accelerometer/gyroscope data is particularly slow and cannot be synchronized (or it is not required) with either the XLDA/GDA bits in the STATUS_REG register or with the DRDY signal driven to the INT1/INT2 pins, it is strongly recommended to set the BDU (Block Data Update) bit to 1 in the CTRL3_C register.
This feature avoids reading values (most significant and least significant parts of output data) related to different samples. In particular, when the BDU is activated, the data registers related to each channel always contain the most recent output data produced by the device, but, in case the read of a given pair (i.e. OUTX_H_A(G) and OUTX_L_A(G), OUTY_H_A(G) and OUTY_L_A(G), OUTZ_H_A(G) and OUTZ_L_A(G)) is initiated, the refresh for that pair is blocked until both MSB and LSB parts of the data are read.
Note: BDU only guarantees that the LSB part and MSB part have been sampled at the same moment. For example, if the reading speed is too slow, X and Y can be read at T1 and Z sampled at T2.
The BDU feature also acts on the FIFO_STATUS1 and FIFO_STATUS2 registers. When the BDU bit is set to 1, it is mandatory to read FIFO_STATUS1 first and then FIFO_STATUS2.
AN5398 - Rev 3
page 26/132

4.5 Understanding output data

The measured acceleration data are sent to the OUTX_H_A, OUTX_L_A, OUTY_H_A, OUTY_L_A, OUTZ_H_A, and OUTZ_L_A registers. These registers contain, respectively, the most significant part and the least significant part of the acceleration signals acting on the X, Y, and Z axes.
The measured angular rate data are sent to the OUTX_H_G, OUTX_L_G, OUTY_H_G, OUTY_L_G, OUTZ_H_G, and OUTZ_L_G registers. These registers contain, respectively, the most significant part and the least significant part of the angular rate signals acting on the X, Y, and Z axes.
The complete output data for the X, Y, Z channels is given by the concatenation OUTX_H_A(G) & OUTX_L_A(G), OUTY_H_A(G) & OUTY_L_A(G) , OUTZ_H_A(G) & OUTZ_L_A(G) and it is expressed as a two’s complement number.
Both acceleration data and angular rate data are represented as 16-bit numbers.

4.5.1 Examples of output data

Table 19. Content of output data registers vs. acceleration (FS_XL = ±2 g) provides a few basic examples of the
accelerometer data that is read in the data registers when the device is subjected to a given acceleration.
Table 20. Content of output data registers vs. angular rate (FS_G = ±250 dps ) provides a few basic examples of
the gyroscope data that is read in the data registers when the device is subjected to a given angular rate.
The values listed in the following tables are given under the hypothesis of perfect device calibration (i.e. no offset, no gain error, …).
AN5398
Understanding output data
Table 19. Content of output data registers vs. acceleration (FS_XL = ±2 g)
Acceleration values
0 g
350 mg 16h 69h
1 g 40h 09h
-350 mg E9h 97h
-1 g BFh F7h
OUTX_H_A (29h) OUTX_L_A (28h)
00h 00h
Register address
Table 20. Content of output data registers vs. angular rate (FS_G = ±250 dps )
Angular rate values
0 dps
100 dps 2Ch A4h
200 dps 59h 49h
-100 dps D3h 5Ch
-200 dps A6h B7h
OUTX_H_G (23h) OUTX_L_G (22h)
00h 00h
Register address
AN5398 - Rev 3
page 27/132

4.6 Accelerometer offset registers

The device provides accelerometer offset registers (X_OFS_USR, Y_OFS_USR, Z_OFS_USR) which can be used for zero-g offset correction or, in general, to apply an offset to the accelerometer output data.
The accelerometer offset block can be enabled by setting the USR_OFF_ON_OUT bit of the CTRL7_G register. The offset value set in the offset registers is internally subtracted from the measured acceleration value for the respective axis; internally processed data are then sent to the accelerometer output register and to the FIFO (if enabled). These register values are expressed as an 8-bit word in two’s complement and must be in the range [-127, 127].
The weight [g/LSB] to be applied to the offset register values is independent of the accelerometer selected full scale and can be configured using the USR_OFF_W bit of the CTRL6_C register:
-10
• 2
•
g/LSB if the USR_OFF_W bit is set to 0;
2-6 g/LSB if the USR_OFF_W bit is set to 1.

4.7 Rounding functions

The rounding function can be used to auto address the device registers for a circular burst-mode read. Basically, with a multiple read operation the address of the register that is being read goes automatically from the first register to the last register of the pattern and then goes back to the first one.

4.7.1 Rounding of FIFO output registers

The rounding function is automatically enabled when performing a multiple read operation of the FIFO output registers: after reading FIFO_DATA_OUT_Z_H (7Eh), the address of the next register that will be read goes automatically back to FIFO_DATA_OUT_TAG (78h), allowing the user to read many data with a unique multiple read.
AN5398
Accelerometer offset registers

4.7.2 Rounding of sensor output registers

It is possible to apply the rounding function to the other output registers.
The rounding function can also be enabled for the following groups of output registers:
• Accelerometer output registers, from OUTX_L_A (28h) to OUTZ_H_A (2Dh);
• Gyroscope output registers, from OUTX_L_G (22h) to OUTZ_H_G (27h);
• Gyroscope and accelerometer output registers, from OUTX_L_G (22h) to OUTZ_H_A (2Dh).
The output register rounding pattern can be configured using the bits ROUNDING[1:0] of the CTRL5_C register, as indicated in the following table.
Table 21. Output register rounding pattern
ROUNDING[1:0] Rounding pattern
00 No rounding
01 Accelerometer only
10 Gyroscope only
11 Gyroscope + Accelerometer
AN5398 - Rev 3
page 28/132

4.8 DEN (data enable)

The device allows an external trigger level recognition by enabling the TRIG_EN, LVL1_EN, LVL2_EN bits in CTRL6_C register.
Four different modes can be selected (see Table 22. DEN configurations):
• Edge-sensitive trigger mode;
• Level-sensitive trigger mode;
• Level-sensitive latched mode;
• Level-sensitive FIFO enable mode.
The Data Enable (DEN) input signal must be driven on the INT2 pin, which is configured as an input pin when one of these modes is enabled.
The DEN functionality is active by default on the gyroscope data only. To extend this feature to the accelerometer data, the bit DEN_XL_EN in CTRL4_C register must be set to 1.
The DEN active level is low by default. It can be changed to active-high by setting the bit DEN_LH in CTRL5_C register to 1.
TRIG_EN LVL1_EN LVL2_EN Function Trigger type Action
0 0 0 Data enable off - -
1 0 0 Edge-sensitive trigger mode Edge Data generation
0 1 0 Level-sensitive trigger mode Level Data stamping
0 1 1 Level-sensitive latched mode Edge Data stamping
1 1 0 Level-sensitive FIFO enable mode Level Data generation in FIFO and stamping
AN5398
DEN (data enable)
Table 22. DEN configurations
AN5398 - Rev 3
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4.8.1 Edge-sensitive trigger mode

Edge-sensitive trigger mode can be enabled by setting the TRIG_EN bit in CTRL6_C to 1, and LVL1_EN, LVL2_EN bits in CTRL6_C register to 0.
Once the edge-sensitive trigger mode is enabled, the FIFO buffer and output registers are filled with the first sample acquired after every rising edge (if DEN_LH bit is equal to 1) or falling edge (if DEN_LH bit is equal to 0) of the DEN input signal.
The following figure shows, with red circles, the samples acquired after the falling edges (DEN active-low).
Figure 7. Edge-sensitive trigger mode, DEN active-low
AN5398
DEN (data enable)
Edge-sensitive trigger mode, when enabled, acts only on the gyroscope output registers. GDA is related only to downsampled data, while the accelerometer output registers and XLDA are updated according to ODR_XL. If the DEN_XL_EN bit is set to 1, the accelerometer sensor is downsampled too. In this case, the gyroscope and accelerometer have to be set in combo mode at the same ODR. The accelerometer standalone mode can be used by setting the gyroscope in Power-Down.
Please note that the DEN level is internally read just before the update of the data registers: if a level change occurs after the read, DEN will be acknowledged in the next ODR.
AN5398 - Rev 3
page 30/132
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