IIS2DLPC: high-performance ultra-low-power 3-axis accelerometer for industrial
applications
Introduction
This document is intended to provide usage information and application hints related to ST’s IIS2DLPC motion sensor.
The IIS2DLPC is a 3D digital accelerometer system-in-package with a digital I²C/SPI serial interface standard output and a
dynamic user-selectable full-scale acceleration range of ±2/±4/±8/±16 g. The device is capable of measuring accelerations with
output data rates from 1.6 Hz to 1600 Hz.
The IIS2DLPC has multiple operating modes which are reconfigurable on the fly and range from ultra-low-power mode (less
than 0.4 µA at 1.6 Hz ODR or single-shot) to high-performance, high-resolution mode (90 µg/√(Hz) at 1.6 kHz ODR at 120 µA).
Ideal applications are industrial IoT and connected devices, anti-tampering devices for smart meters and portable healthcare
devices.
The IIS2DLPC has an integrated 32-level first-in, first-out (FIFO) buffer allowing the user to store data in order to limit
intervention by the host processor and can be configured to generate interrupt signals by using hardware recognition of free-fall
events, 6D orientation, tap and double-tap sensing, activity or inactivity, and wake-up events.
The IIS2DLPC is available in a small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended
temperature range from -40 °C to +85 °C.
AN5201 - Rev 4 - January 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1Pin description
AN5201
Pin description
Figure 1. Pin connections
Table 1. Internal pin status
NameFunctionPin status
Pin #
SCL
1
2CS
3
4
5NCInternally not connected. Can be tied to VDD, VDDIO, or GND.
6GND0 V supply
7RESConnect to GND
8GND0 V supply
9VDDPower supply
10VDD_IO Power supply for I/O pins
11INT2
12INT1Interrupt pin 1Default: push-pull output forced to ground
1. In order to disable the internal pull-up on the CS pin, write '1' to the CS_PU_DISC bit in CTRL2 (21h).
2. Internal pull-up on SDO/SA0 pin cannot be disabled: do not connect this pin to GND in low-power applications.
I²C serial clock (SCL)
SPC
SPI serial port clock (SPC)
SPI enable
I²C/SPI mode selection
1: SPI idle mode / I²C communication enabled
0: SPI communication mode / I²C disabled
SDO
Serial data output (SDO)
SA0
I²C less significant bit of the device address (SA0)
SDA
I²C serial data (SDA)
SDI
SPI serial data input (SDI)
SDO
3-wire interface serial data output (SDO)
Interrupt pin 2
Clock input when selected in single data conversion on demand.
These operating modes are selected by writing the MODE[1:0] and LP_MODE[1:0] bits in CTRL1 (20h) shown in
the table below.
AN5201
Operating modes
Table 3. Accelerometer resolution
Table 4. CTRL1 register
b7b6b5b4b3b2b1b0
ODR3ODR2ODR1ODR0MODE1MODE0LP_MODE1LP_MODE0
Table 5. Mode selection
MODE[1:0]
00Low-Power Mode (12/14-bit resolution)
01High-Performance Mode (14-bit resolution)
10Single data conversion on-demand mode (12/14-bit resolution)
11Not allowed
Mode and resolution
Table 6. Low-power mode selection
LP_MODE[1:0]
00Low-Power Mode 1 (12-bit resolution)
01Low-Power Mode 2 (14-bit resolution)
10Low-Power Mode 3 (14-bit resolution)
11Low-Power Mode 4 (14-bit resolution)
Mode and resolution
AN5201 - Rev 4
From each of these five sets, two configurations have been designed:
•Very low-power(low-noise off)
•Low-noise
Writing the LOW_NOISE bit in CTRL6 (25h) selects the desired configuration. The LOW_NOISE bit in CTRL6
(25h) impacts front-end noise and current consumption. Bandwidths and settling time are not impacted.
page 5/55
AN5201
Power mode
Table 7 shows the typical values of power consumption for the different operating modes.
Note: In Low-Power Mode the RMS noise is the same for all ODRs.
AN5201
Power mode
AN5201 - Rev 4
page 7/55
3.2Continuous conversion
When bits MODE[1:0] in CTRL1 (20h) are set to Low-Power mode (00b) or High-Performance mode (01b), the
device is in continuous conversion and the output data rate can be selected through the ODR[3:0] bits in CTRL1
(20h).
This mode is available only for low-power modes and it is enabled by writing the MODE[1:0] bits to ‘10' in CTRL1
(20h).
In this configuration the device waits for a trigger signal in order to generate new data according to the selected
power mode LP_MODE[1:0] bits in CTRL1 (20h), after that the device immediately enters power-down.
The trigger can be:
•A rising edge on the INT2 pin (if SLP_MODE_SEL = ‘0' in register CTRL3 (22h)). In this case the
user can detect the end of the conversion using the DRDY bit of the STATUS register (27h) that can also
be routed to the INT1 pin by setting the INT1_DRDY bit to 1 in register CTRL4_INT1_PAD_CTRL (23h).
Minimum duration of trigger signal high level is 20 ns.
•A write of SLP_MODE_1 to ‘1' in register CTRL3 (22h) (if SLP_MODE_SEL ='1' in register CTRL3(22h)). In this case, the user can detect the end of the conversion using the DRDY bit/signal as in the
previous case, or by checking when the SLP_MODE_1 bit in register CTRL3 (22h) is automatically cleared.
Figure 2. Single data conversion using INT2 as external trigger (SLP_MODE_SEL = 0)
AN5201
Single data conversion (on-demand mode)
The maximum data rate using single data conversion mode is 200 Hz and the time of conversion depends on the
low-power mode selected (refer to the following table).
Table 11. Low-power mode selection
Low-power
Mode 11.20 ms
Mode 21.70 ms
Mode 32.30 ms
Mode 43.55 ms
Typical time of conversion
(T_on)
Note: If the ODR[3:0] bits of the CTRL1 register are set to 0000b, the accelerometer is permanently configured in
Power-down mode and no conversion can be triggered. When the single data conversion mode has to be used,
the ODR[3:0] bits of the CTRL1 register must be different than 0000b.
Interrupts, embedded features and FIFO are still supported when using single data conversion mode. Also the
embedded filters LPF1, LPF2 and HP are available in single data conversion (on-demand mode) with the same
bandwidth and settling time of the selected low-power mode (see Section 3.4 Accelerometer bandwidth for
details).
AN5201 - Rev 4
page 9/55
3.4Accelerometer bandwidth
The accelerometer sampling chain (Figure 3. Accelerometer filtering chain diagram) is represented by a cascade
of a few blocks:
•ADC: Analog-to-digital converter
•Anti-Aliasing Filter: available only in High-Performance Mode (MODE[1:0] = 01) with a cutoff frequency of
400 Hz
•LPF1(2): low-pass filter 1(2)
•HP: high-pass filter
•User offset: configurable values that are subtracted from the sampled data (one for each axis)
Figure 3. Accelerometer filtering chain diagram
AN5201
Accelerometer bandwidth
As shown in the figure above, data can be generated using three different filter paths:
•only LPF1 (green path) : in order to select this path set BW_FILT[1:0] = 00 and FDS = 0. Additional details in
Table 12. Low-pass filter 1 bandwidth.
•LPF1 + LPF2 (purple path) : in order to select this path set BW_FILT[1:0] to a value different from 00 and
FDS = 0. Additional details in Table 13. Bandwidth: low-pass path.
•LPF1 + HP (blue path): these outputs are available by setting FDS = 1. Additional details in
Table 14. Bandwidth: high-pass path.
AN5201 - Rev 4
page 10/55
AN5201
Accelerometer bandwidth
Table 12. Low-pass filter 1 bandwidth
BW_FILT[1:0] = 00
ModeODR selection
Samples to discard
Settling @95%
Low-Power Mode 4@ each ODR
0180
Low-Power Mode 3@ each ODR0360
Low-Power Mode 2@ each ODR0720
Low-Power Mode 1@ each ODR03200
High-Performance@12.5 Hz0ODR/2
High-Performance@25 Hz0ODR/2
High-Performance@50 Hz0ODR/2
High-Performance@100 Hz1ODR/2
High-Performance@200 Hz1ODR/2
High-Performance@400 Hz1ODR/2
High-Performance@800 Hz1ODR/2
High-Performance@1600 Hz2400
1. The starting condition of ODR[3:0], MODE[1:0], LP_MODE[1:0] and BW_FILT[1:0] do not impact these values. The turn-on
time (first sample available starting from power-down condition) is 1 / ODR.
1. The starting condition of ODR[3:0], MODE[1:0], LP_MODE[1:0] and BW_FILT[1:0] do not impact these values.
(1)
Cutoff
Samples to discard
[Hz]
Settling @95%
(1)
Cutoff
[Hz]
Setting USR_OFF_ON_OUT = 1 in CTRL7 does not change the bandwidth of the system. In this configuration,
the values written in registers X_OFS_USR, Y_OFS_USR, Z_OFS_USR are subtracted from the respective axis.
The offset values are signed values (two's complement).
The weight of the bits in registers X_OFS_USR, Y_OFS_USR, Z_OFS_USR is defined through the USR_OFF_W
bit in CTRL7.
AN5201 - Rev 4
page 12/55
3.5High-pass filter configuration
The IIS2DLPC provides an embedded high-pass filtering capability to easily delete the DC component of the
measured acceleration. As shown in Figure 3. Accelerometer filtering chain diagram, through the FDS bit in
register CTRL6 the user can route the filter outputs to the output registers.
It is also possible to independently apply the filter to the embedded function data (Figure 9. Embedded functions
in Section 5 Interrupt generation and embedded functions). This means that it is possible to get filtered data
while the interrupt generation works on unfiltered data.
The high-pass filter can be configured in reference mode by setting the HP_REF_MODE bit in the CTRL7 register
to 1. In this configuration the output data is calculated as the difference between the measured acceleration and
the output values captured when reference mode was enabled. In this way only the difference is applied without
any filtering.
As an example, this feature can be combined with the wake-up functionality described in Section 5.4 in order
to detect when the device is displaced with respect to a specific orientation, i.e. the orientation of the device
when the HP_REF_MODE bit was set to 1. When the output acceleration exceeds the wake-up threshold defined
by the WK_THS[5:0] bits in the WAKE_UP_THS register for a duration longer than the one defined by the
WAKE_DUR[1:0] bits in the WAKE_UP_DUR register, an interrupt is generated. If the device is moved back to the
original reference orientation, the interrupt is deactivated.
Figure 4. High-pass filter in normal and reference mode
AN5201
High-pass filter configuration
AN5201 - Rev 4
page 13/55
3.6Frequency response
The following figures indicate the frequency response of the sensor in various configurations.
CTRL1.MODE = 11; CTRL6.BW_FILT = 01)
Note: The frequency response is determined by CAD simulation.
AN5201 - Rev 4
page 16/55
4Reading output data
4.1Startup sequence
Once the device is powered up, it automatically downloads the calibration coefficients from the embedded
non-volatile memory to the internal registers. When the boot procedure is completed, i.e. after approximately
20 milliseconds, the accelerometer automatically enters power-down. The default status of the pins with both VDD
and VDDIO "on" is indicated in Table 1. Internal pin status.
Note: VDD cannot be lower than VDDIO. VDD = 0 V and VDDIO "on" is allowed: when this power supply
configuration is applied, an internal pull-up is applied also to the SDA and SCL pins (the other pins maintain the
default status indicated in Table 1).
To turn on the accelerometer and gather acceleration data, it is necessary to select one of the operating modes
through the CTRL1 register.
Refer to Section 3 Operating modes for a detailed description of data generation.
4.2Using the status register
The device is provided with a STATUS register which can be polled to check when a new set of data is available.
The DRDY bit is set to 1 when a new set of data is available from the accelerometer output.
The read operations should be performed as follows:
1.Read STATUS
2.If DRDY = 0, then go to 1
3.Read OUT_X_L
4.Read OUT_X_H
5.Read OUT_Y_L
6.Read OUT_Y_H
7.Read OUT_Z_L
8.Read OUT_Z_H
9.Data processing
10. Go to 1
AN5201
Reading output data
4.3Using the data-ready signal
The device can be configured to have one hardware signal to determine when a new set of measurement data is
available to be read.
The data-ready signal is derived from the DRDY bit of the STATUS register. The signal can be driven to the INT1
pin by setting the INT1_DRDY bit of the CTRL4_INT1_PAD_CTRL register to 1 and to the INT2 pin by setting the
INT2_DRDY bit of the CTRL5_INT2_PAD_CTRL register to 1.
The data-ready signal rises to 1 when a new set of data has been measured and is available to be read. In
DRDY latched mode (DRDY_PULSED bit = 0 in CTRL7 register), which is the default condition, the signal gets
reset when the higher part of one of the channels has been read (29h, 2Bh, 2Dh). In DRDY pulsed mode
(DRDY_PULSED = 1) the pulse duration is 75 μs (typical) if the accelerometer is configured in High-Performance
mode, otherwise it can vary between 105 μs and 175 μs. Pulsed mode is not applied to the DRDY bit which is
always latched.
AN5201 - Rev 4
page 17/55
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