Datasheet W.A.R.P. 1.1 Datasheet (ST)

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WEIGHT ASSOCIATIVE RULE PROCESSOR

HighSpeed Rules Processing
AntecedentMembership Functions with any

Shape
Up to 256Rules (4Antecedents,1

Consequent)
Up to 16 Input ConfigurableVariables
Up to 16 MembershipFunctionsforan Input

Variable
Up to 16 OutputVariables
Up to 128 MembershipFunctionsforall

Consequents
MAX-DOT Inference Method
Defuzzification on chip
SoftwareTools and EmulatorsAvailability
100-pinCPGA100Ceramic Package
84-leadPlastic LeadedChip Carrierpackage

GENERAL DESCRIPTION

W.A.R.P. is a VLSI Fuzzy Logic controller whose
architecture arises from the need of realizing an
integratedstructurewith high inferencingperform­ancesandflexibility. Toget those resultsa modular
architecture based on a set of parallel memory
blockshas beenimplemented.

Inordertoobtainhigh performancesW.A.R.P.uses
different data representations during the various
phases of the computational cycle, so that it is
always operating on the o ptimal data repre­sentation. A vectorial characterization has been
adopted for the Antecedent Membership Func­tions. W.A.R.P. exploits a SGS-THOMSON pat­entedstrategytostoretheAntecedentMembership

W.A.R.P. 1.1

CPGA100 PLCC84

Figure1. Logic Diagram

MCLK VS S VDD

FIN

SYNC

8

I0-I7

EPA0-EPA2

A0-A9

3

10

CHM OFL

W.A.R.P.

1.1

ADVANCED DATA

10

O0-O9

4

OCNT0-OCNT3

STB
NP

EP

PRST

Table 1. W.A.R.P. Configuration Settings

Number of Inputs Configurable [1..8]
Standard Rule Format 4 Antecedents, 1 Consequent [or subsets]
Rules Number Max 256 Rulesin the 4Antecedent, 1 Consequent format
Antecedent’sMFs Number Configurable [up to 16 for an input variable]
Consequent’sMFs Number Max 256 for all outputs variables
Input Data Resolution 8 bit
Output Data Resolution 8 bit

May 1996

This is advance information on a new productnow in development or undergoing evaluation. Details are subject to change without notice.

1/19

W.A.R.P.1.1

Figure2. CPGA100 PinConfiguration

Table 2. AbsoluteMaximumRatings

Symbol Parameter Value Unit

V

DD

V

I

V

O

I

OL

I

OH

T

OPT

T

STG

Notes: Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device.

These arestress ratingsonly and operation of the device at these or any other conditions above those indicated in the Operating
sections of thisspecification is not implied. Exposure toAbsolute Maximum Rating conditions for extended periods may affect
device reliability.Refer also to the SGS-THOMSON SURE Programand other relevant quality documents.

2/19

Supply Voltage -0.5 to 7 V
Input Voltage -0.5to VDD+0.5 V
Ouput Voltage -0.5to VDD+0.5 V
Output Sink Peak Current +24 mA
Output Source Peak Current -12 mA
Operating Temperature 0 to +70 °C
StorageTemperature (Ceramic) -65 to +150 °C
StorageTemperature (Plastic) -45 to +125 °C

Figure3. PLCC84Pin Configuration

VDD

VSSA0A1A2A3A4VDD

11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

12

VSS

13

VDD

MCLK

CHM

PRST

MTE

VDD

FIN

OFL

TE

VSS

14
15
16

I0
I1

17

I2

18

I3

19
20

I4

21

I5
I6

22

I7

23
24
25
26
27
28
29
30
31
32

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

VSS

EPA0

EPA1

EPA2A5A6A7A8A9VDD

W.A.R.P. 1.1

VSS

W.A.R.P.1.1

74
73

VDD
72
71

VSS
70

SYNC

69
68

OTST

OMTS

67

STB

66

EP

65

VSS

64

NP

63

OCNT3

62

OCNT2

61

OCNT1

60

OCNT0

59
58

VSS

57
56

VDD

55
54

VSS

O0O1O2O3O4

VDD

O5O6O7O8O9

VSS

VDD

VSS

Table 3. RecomendedOperationConditions (Ta=0to +70 °Cunless otherwisespecified)

Symbol Parameter Min Typ Max Unit

V

DD

V

IL

V

IH

V

OL

V

OH

FCLK Clock Frequency 40 MHz

CL Output Load Capacitance 10 85 pF

Supply Voltage 4.75 5.0 5.25 V
Input Voltage 0.8 V
Input Voltage 2 V
Ouput Voltage 0.5 V
Ouput Voltage 2.4 V

3/19

W.A.R.P.1.1

Table4. Pin Description

Name Pins Type Function

V

DD

V

SS

A0-A9 I/O Memory Address Bus

I0-I7 I Data Input Bus

PRST I Preset

FIN I FirstInput Signal

OFL I Off-Line/On-Line Switch

CHM I ChargeMode Switch

TE I Testing(it must be connected to V

MTE I Testing (it must be connected to V

MCLK I Clock (up to 40 MHz)

EPA0-EPA2

O0-O9 O Defuzzified Output

OCNT0-OCNT3 O Output Counter

STB O Strobe(Output Ready Signal)

OTST O Testing(it mustbe connected toV

OMTS O Testing (it must be connected to V

SYNC O External Synchronization

*

Pins not usedin W.A.R.P. 1.0

*

EP O End Process

NP O New Process

Functionsindedicatedmemoriesinorderto reduce
the computationaltime. Thereforea great amount
of W.A.R.P. processing isbased on a look-uptable
approachrather than on on-linecalculation.

Those Membership Functions (MFs), each one
portrayed by a configurable resolution of 2
elements,arestored in fourinternalRAMs(1Kbyte
each). The consequentMFs, due to the different
modelling, are loaded in a single RAM by storing
for each MFitsareaandits barycentre.Thisis due
to theadoptionof theCenterofGravitydefuzzifica­tion method.

The downloading phase allows the setting of the
device, in terms of I/O number, universes of dis­courseandMF shapes.DuringthisphaseW.A.R.P.
prepares its internal memories for the on-line
elaboration phase and loads the microcode in its
programmemory. Thismicrocode,whichdrivesthe
on-line phase, is generated by the Compiler (see
W.A.R.P.-SDT User Manual) according to the
adoptedconfiguration.Thepossibleconfigurations
areshown in table 1.

During the on-line phase (up to 40MHz working
frequency),W.A.R.P.processes theinputdataand
producesitsoutputsaccordingtotheconfiguration
loadedin the downloadingphase.

W.A.R.P. is conceivedto work together with tradi-

- Power Supply

- Ground

O EPROM Address Bus

6

or 2

)

SS

)

SS

)

SS

)

SS

tional microcontrollers which shall perform normal
control tasks while W.A.R.P. will be indipendently
responsiblefor all the fuzzyrelated computing.

W.A.R.P. is manufacturedusing the high perform­ance, reliable HCMOS4T (O.7µm) SGS-THOM-

7

SON Microelectronicsprocess.

PIN DESCRIPTION
V

DD,VSS

these pins.V

: Power is supplied to W.A.R.P. using

isthe powerconnectionandVSSis

DD

the ground connection;multi-connectionsare nec­essary.

A0-A9: When the CHM pin is low theyaccept as
input theaddressesfortheinternalmemory bus. In
the off-linemodetheyareusedtoaddressW.A.R.P.
memories where the microprogram and data of
antecedentandconsequentmembershipfunctions
must be loaded.
Each A0-A9 word is composed by assemblingthe
datacontainedinthe memorysupportrelatedto.cs
and .addfiles (seeW.A.R.P.-SDT User Manual).In
particular,couplesofdatarespectivelycomingfrom
.cs and .addfiles are joined to forma single A0-A9
word in the followingway:

4/19

W.A.R.P.1.1

add7 add6 add5 add4 add3 add2 add1 add0

cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0

cs2 cs1 cs0 add6 add5 add4 add3 add2 add1 add0

A9

A0

This resultingword allows to identifythe appropri­ate memory [cs2-cs0] and its respective address
[add6-add0] where the relative I0-I7 are to be
stored.

When the CHM pin is high, during the off-line
phase, W.A.R.P. generates the addresses for its
internalmemoriesandsendthoseaddressestothe
single external memory support where data (.dat
file)are located.These addresses,whichare sent
by means of the EPA0-EPA2 and A0-A9 (EPA0
MSB, A9 LSB) output pins, allow to identify the
data (on the EPROM) that have be loaded in
W.A.R.P. internalmemories.
In on-linemode A0-A9 are not used.

I0-I7: During the off-line phase these 8 data input
pins accept the microcode configuration and data
to be written into the internalmemories. The ante­cedentmemoryword size is 64 bits, so it is neces­sary to giveeachword8 bitsat a time. Inthe same
way are written the words of consequentmemory
and of program memory.
In on-linemode this bus carries the inputvariables
to W.A.R.P..Input values havea resolution of6 or
7 bits in accordancewith the configurationsetting.

PRST: This is the restart pin of W.A.R.P.. It is
possibletorestartthework during thecomputation
(on-line phase) or before the writing of internal
memories(off-linephase).In both casesit mustbe
put low at leastfora clock period.

FIN: During the on-line phase it will start the run­time acquisition cycle. This pin is activated by
providinga positivepulse fora time no lower than
an entire clock period. When all expected inputs
have been processed, a new FIN pulse must be
sent to activate a new process.

OFL: When this pin is high, the chip is enabled to
load data in the internal RAMs (off-line phase). It
mustbelowwhenthe fuzzycontrolleris waitingfor
input valuesand during the processingphase(on­line phase).

CHM:Thispin,whichisusedonlyduringtheoff-line
phase, determines the charge mode. CHM is not
presentin W.A.R.P.1.0 release.
When CHM is low the addresses of the internal
memory locations where data have to be stored

must be sent to W.A.R.P. from the outside by
means of the input pins A0-A9.
WhenCHM is high W.A.R.P. automaticallygener­ates the addresses of its internal memories and
manages the EPROMs reading by means of the
addresses contained in EPA0-EPA2 and A0-A9
output pins(13 bits).

TE: Fortesting purpose only. It mustbeconnected

.

to V

SS

MTE: For testing purpose only. It must be con­nected to V

SS

.

MCLK: This is the input master clock whose fre­quencycan reach up to 40MHz (MAX).
During the off-line phase with CHM high, the
DCLKsignalwith a frequencyofMCLK/32 is gen­erated in order to drive the downloading phase
timing.

EPA0-EPA2: During the off-linephase and in cor­respondencewithCHM high,theseoutputpins are
joined (as MSB) to A0-A9 to obtainethe complete
address ofthe memory supportwhere to read the
data to be loadedin W.A.R.P.internal memories.
EPA0-EPA2 are not used when CHM is low or in
W.A.R.P. 1.0 release.

O0-O9: These pins carry out the output values.
When the STB (strobe pin) is high, one output
variablecan bereadbyexternaldevices(in on-line
mode). The resolution ofoutput variables is 1024
points(10 bits). Ifthere are more than oneoutput,
the outputvariables are calculatedone by one and
theyare providedin the sequencestabilizedduring
the editing phase (see W.A.R.P.-SDTUser Man­ual).

OCNT0-OCNT3:This4 bit outputbus provides the
output variableswith a progressive number during
the on-line phase. As a consequenceit ispossible
to know towhichvariablecorrespondthedatathat
areonthe outputdatabus(O0-O9).Thedimension
of OCNT bus is connected with the maximum
number ofoutput variables (16).

STB:The strobepin enables the user to utilize the
output.When thispinishigh itindicatesthat a new
output variablehasbeen calculated andit is ready
on the output bus (O0-O9). This signal synchro­nizes the external devices and in particular the
interfaces with the controlled processes (on-line
mode).

EP: This signal low indicates that the processing
of all the rules has been completed.

NP: This output pin indicates that a new process
can start. NP is automatically set low before the
lastoutputhasbeencalculated,sothatitispossible
to start a new data acquisitionbefore(with a new
FIN) the computation is terminated.

5/19

W.A.R.P.1.1

Figure4. Block Diagram

OTST: For testing purpose only. It must be con-

nectedto V

SS

.

OMTS: For testing purpose only. It must be con­nectedto V

SS

.

SYNC:W.A.R.P. uses this pin to synchronizeinput
data from an external database in off-line mode.
The database contains informationabout antece­dent and consequent membership functions and
aboutfuzzy rules. Tomemorize this database it is
possibleto use an host processor or a non volatile
memory.

FUNCTIONAL DESCRIPTION

W.A.R.P.worksintwomodedependingontheOFL
controlsignal level:

Off-line MODE (OFL High)
On-line MODE (OFLLow)
OFF-LINE MODE

All W.A.R.P. memories are loaded during the off­line phase. The membershipfunctions arewritten
insidetheirrelatedmemoriesandtheprocess con­trol rules are loaded inside the program memory.
If the CHM switch has been set low then the
addressesof the words to be written in the memo­ries are providedby an externalbus (A0-A9), while
data must be loaded 8 bita time in the data bus.
If the CHM switch has been set high then the
addressesof the words to be written in the memo­ries are internally generated while the addresses
of the EPROM’s locations to be read are directly

Table 5. AvailableConfigurations on a Single Antecedent Memory.

Numbers ofInput Data Resolution

1 128 (7bit) 16

*

2

264(6bit)16
3 64 (6 bit) 2x8 + 1x16

*

Thisconfiguration is not available in W.A.R.P.1.0.

464(6bit)8

128 (7bit) 8

Number ofMembership Functions

for TermSet

6/19

W.A.R.P.1.1

provided by W.A.R.P. by means of A0-A9 and
EPA0-EPA2output pins.
Data must be loaded 8 bit a time in the data bus
and can be read from an external non volatile
memoryor loaded by an hostprocessor.

ON-LINEMODE

In On-line mode W.A.R.P. is enabled to elaborate
input valuesandcalculateoutputsaccordingto the
fuzzyrulesstoredinto themicroprogram.W.A.R.P.
reads the input values one a time in the input data
bus when all the inputs are given, a NP signal is
pulledhighto indicatethatthe computationis start­ing.Thecomputationalphaseisdividedintwomain
parts.During the first one the inputvaluesareread
and the corresponding ALPHA values (activation
levels)are extractedfrom theinternalmemories. In
the second part the computation of the fuzzy rules
and the defuzzificationare implemented.

The block diagramshown in figure 3 describesthe
structureof W.A.R.P..

Antecedent Memory. It is formed by 4 benchs
eachonecontainingonetofour fuzzy setsbonded
to the input variables.

Consequent Memory. It is formed by one bench
wherethefuzzysetsbondedto theoutputvariables
arestored .

ProgramMemory. It is formedby a single bench.
Each line contains an operating code to execute
the computation of a rule. This code selects the
antecedentweights(ALPHA)involvedinarule,and
connectsthem by the programmedconnective op­erators(AND,OR).

Input Router. This internal block performs the
input data routing. Data are read one byte a time
fromtheinputdata bus, storedin 4differentbuffers
and, thanksto a pipeline process, sent togetherto
4 indipendentmodulesto be processed inparallel
accordingtothe chosenset-upconfiguration.Input
data resolution is decided by the user (MAX 128
points) according to the available configurations,
as shown intable 5.

The cycle starts when a positivepulseis appliedat
FIN for a time no lower than an entireclock period
and continues until a new FIN (after NP low) or a
PRST signal is given.

Fuzzifier. This block generates the addresses of
the antecedentmemorieswheretheALPHAvalues
for each sampled input value are stored. It reads
the first four input values and calculatesthecorre­sponding antecedent memories addresses. After­wards it reads other four inputs values and
simultaneously sends, thanks to a pipeline proc­ess, the previous four ALPHAvalues into internal
registers.TheseALPHAvaluesarethensenttothe
Inference Unit. W.A.R.P.stores all ALPHA values
comprisinga term set, which is formed by the MFs
connected to the IF-part of a rule, in successive
memory locations of the same memory word (see
figure 4). The vectors characterizingthe MFs of a
term set are stored so that theALPHAsofdifferent
MFs corresponding to the same universe of dis­course point (for the same input) are stored se­quentially. So W.A.R.P. retrieves all the alpha
values of a termset using the crisp input value to
calculate the memory word address in the used
fuzzy memory device.The Fuzzifier Unit is driven

Figure5.Antecedent Memory Organization

7/19

W.A.R.P.1.1

Figure6. InferenceUnit Structure

bytheconfigurationinaccordancewith theantece­dent part of the fuzzy rules. The duration of the
fuzzification process depends from the chosen
configurationand the input number.

InferenceUnit. Thanksto the ThetaOperator, the
InferenceUnitgeneratestheTHETAweightswhich
areused to manipulatethe consequentMFs.

This is a calculation of the maximumand/or mini­mumperformedon ALPHAvaluesaccordingto the
logical connectives of fuzzy rules. It is possible to
utilize the AND/OR connectivesandto directlyex­ploit ALPHA weights or the negated values. The
numberof THETAweightsdepends onthe number
of rules.

The rules can have at maximum four ALPHA
weights (however they are connected). Two or
more rules canbe only joinedwith theOR connec­tive.

InferenceUnitstructure is shown in figure5.
Defuzzifier. It generates the output crisp values

implementing the consequent part ofthe rules ac­cording to MAX-DOTmethod.

In this method consequentMFs are multipliedby a
weight value Ω (OMEGA), which is calculated on
the basisofantecedentMFsand logical operators.

Allthetermsneededtoevaluatesumsinnumerator
and denominatorof center of gravityequation(see
formula)are stored during the off-linephase.

The processing of fuzzy rules produces, for each
output variable, a resulting membership function.
Each MF related to the processed output variable

is firstlymodified by a rule weight in accordanceto
MAX-DOTmethod.

Output value(X) is deduced fromthe centroids (x
and themodifiedMFs (Ω

n

∑

1

X

=

)by usingthe formula:

i*Ai

Ωi∗

∑

n

1

Ωi∗

A

∗

i

A

i

x

i

n = number of MFsdefined for the OutputVariable
A

=MFiArea

i

x

=abscissof the MFicentroid

i

Ω

=membershipdegree of the output MFi.

i

To represent a membership function related with
the THEN-part of a rule W.A.R.P. uses a single
memory bench. For each consequent MF each
memorywordcontainsboththeareamultipliedwith
the barycentre and the area itself. This area is
related to the first truth level (there are 16 truth
levels (4bit), so amultiplication with the calculated
THETAmust be performedon-line.

Two parallel blocks calculate the numerator and
denominator values to implement the centroids
formula. Afinaldivision block calculates the output
values (see figure 6).

)

i

8/19

Figure7. DefuzzifierStructure

W.A.R.P.1.1

ELECTRICAL SPECIFICATIONS
DC PARAMETRICS AcrossTemperature Range (T=0to +70 °C unless otherwisespecified) -

TTL INTERFACE

2.4V

0.4V

2V

0.8V

2.4V

0.4V

Input Output

Table 6. DC Characteristics

Symbol Parameter Min Typ Max Unit

V

IL

V

IH

V

OL

V

OH

I

IL

I

IH

Low Level InputVoltage 0.8 V

High Level Input Voltage 2.0 V

Low Level OutputVoltage 0.2 0.4 V

High Level Output Voltage 2.4 3.4 V

Low Level InputCurrent VI=V

High Level Input Current VI=V

SS

DD

+1 µA

-1 µΑ

9/19

W.A.R.P.1.1

DC PARAMETRICS

DC PARAMETRICSAcrossTemperature Range (T=0 to +70 °Cunless otherwisespecified
TTLINTERFACE

Data

Clock

Table7. AC Characteristics

Symbol Parameters Test Conditions

t

t

CLH

t

t
t

t

SET

t

HLD

CP

CLL

CR
CF

Clock Period 50 25 ns

Clock High 20 30 10 15 ns

Clock Low 20 30 10 15 ns

Clock Rise 0.8V to 2V 4 4 ns

Clock Fall 2V to 0V 4 4 ns

Setup 12 12 ns

Hold 15 15 ns

t

CLL

t

50%

50%

tSET tHLD

50%

CLH

t

CP

CK=20MHz

Min Max

CK=40MHz

Min Max

Unit

10/19

W.A.R.P. TIMING TABLES

Off-line Phase Timing (Internal RAMs Loading withCharge Mode ”0”)

OFL

F IN d e te c t ion DATA0 a c q u is ition DATA1 a c q u is ition D ATAn a c q uis itio n

MCLK

FIN

T

ACQ

I0- I6

NP

EP

T

AC Q =

200 ns for a configuration with 16 inputs, 8 outputs,28 rules

DATA0 DATAnDATA1

W.A.R.P.1.1

TimingTableDescription: OFF-LINEphase (CHM ”0”)

- CHM [INPUT] low will enablethe ’manualdownloading’by specifyingthe address anddata to be loaded
into W.A.R.P..

- MCLK [INPUT] must be connected with the external synchronization signal.

- PRST[INPUT]must be set highto enable the device.

-OFL[INPUT]mustbe sethightoenabletheconfigurationloadingphaseintotheinternalRAMsofW.A.R.P..

- Theinputto be written into the internal memoriesat the addressspecifiedin A0-A9 must be put into I0-I7
bus .

- SYNC [OUTPUT] will be provided to synchronize input data (I0-I7,A0-A9) coming from an external
database.SYNC frequencyis MCLK/32 with a phase delay of t
on input buses at the rising edge ofMCLK,returns a SYNC pulse after t

ns . W.A.R.P. stores the data present

CSP

ns indicatingthat is waiting for

CSP

new data andaddressthatmustbe given within next 31MCLKpulses. Afterwards W.A.R.P. stores thedata
on input buses and restoresa new SYNC pulse.

W.A.R.P. stores the data situated in I0-I7 andthe addressesA0-A9into its internal registers.

Figure8. Block Diagram for W.A.R.P. downloading (CHM ”0”)

11/19

W.A.R.P.1.1

Off-line Phase Timing (Internal RAMs Loading withCharge Mode ”1”)

CHM

PRST

MC LK

W.A .R .P. store s DATA0 W.A .R.P. store s DATA1 W.A .R .P. st ore s DATAn

DC LK

OFL

EPA0-EPA2+
A0-A9

I0 -I7

SYNC

ADD RE S S 0 ADDR ES S 1 ADD RES S n

DATA0 DATAnDATA1

Timing Table Description: OFF-LINEphase (CHM ”1”)

- CHM [INPUT] high will enable the ’automatic downloading’, specifying the address of the non-volatile
memory where are data to be loaded into W.A.R.P.. Internal memory addresses are automatically
generated.

- MCLK [INPUT] must be connectedwiththe externalsynchronizationsignal.

- PRST [INPUT] must be set high to enablethe device.

- OFL[INPUT] must be set high to enable the loadingphase of data into the internalRAMs of W.A.R.P..

- SYNC [OUTPUT] will be provided to synchronizeinput data (I0-I7) coming from the external database.
SYNC frequencyis MCLK/32.

-DCLK[INTERNAL] setstheworkingfrequencyaccordingto theOFLcontrolsignal.Itdrivestheaddressing
ofdatacoming fromtheexternalmemorysupportbythe I0-I7 inputbus. Theexternalmemorysupport must
return the data (addressedby EPA0-EPA2+A0-A9[OUTPUT]) into I0-I7 in a periodof time no longerthan
halfa periodofDCLK. DCLK frequencyis MCLK/32.

Figure 9.

12/19

Block Diagram for W.A.R.P. downloading(CHM”1”)

W.A.R.P.1.1

On-line Phase Timing(Acquisition and Elaboration)Working Frequency40MHz

OFL

FIN detection DATA0 acquisition

MCLK

FIN

T

ACQ

I0-I6

DATA0

NP

EP

T

ACQ = 200 ns for a configuration with 16 input s, 8 outputs , 28 rules

Timing TableDescription:ON-LINE phase

st

step:Acquisition

1

- MCLK [INPUT] must be connectedwith the external synchronizationsignal.

- OFL [INPUT] must be set low to enable the acquisition/elaborationphase of W.A.R.P..

- FIN [INPUT] must be set high for at least 1clock period to start the acquisitionphase. OFLmust already
be low since at least 4 clock periods before providing a FIN pulse. FIN duration must be in the range
[1clock,2clockperiods]. FIN pulse mustn’t coincide with NP transitions.

- NP [OUTPUT] will remain low during the acquisition phase.

- Theinput data must be sent toI0-I6 after OFL hasbeen set low andFIN has beensethigh. Datasituated
in I0-I6 are stored into its internal registers at each next rising edge of the MCLK.

- Afterthe current inputs havebeen acquired,the NP [OUTPUT] high signal informs that the elaboration
phase can start. Thisinformationis providedthanks to the configurationstored in the programmemory.

DATA1 acquisition

DATA1

DATAn acquisition

DATAn

Figure 10. Input/Output Connection Block Diagram

13/19

W.A.R.P.1.1

On-linePhase Timing(Output Generation)Working Frequency 40MHz

MCLK

STB

start of
computation

d ata output
storag e

data output
storag e

data output
storag e

NEW DATA
ACQUISITION

NP

COMP

T

EP

O0-O9

last output data

OCNT0-3

T

comp= 600 ns(first proce ss, pipeline empty), 310 ns (next processes) for a configuration with 16 inputs, 8 outputs, 28 rules

Elapsed time from the first data acquisition to the first output: 810 nsfor the first cycle , 525ns forthe other ones

end of
computation

DATAOUT 1

OUT NUM1

T

COMP

OUT NUM 2

T

COMP

COMP

T

DATAOUT n-1DATAOUT 2

OUT NUM n-1last output number

.

TimingTable Description: ON-LINE phase

nd

2

step:Elaboration

- MCLK [INPUT] must be connectedwith the external synchronizationsignal.

- OFL [INPUT] must remain low during this phase.

-NP [OUTPUT] remains high during this phase.

- EP [OUTPUT] is set high during this phase.

- STB [OUTPUT] is set high for a clock period every time an output value has been calculated. It informs
that it is possible to utilizethe outputwhich is situatedin the output bus (O0-O9).The STB pulse starts at
the rising edge ofthe MCLKand stopsat the next risingedgeof the MCLK. At thefalling edge of the STB

the data situated on the O0-O9 bus can be stored.

- The current output on the O0-O9 [OUTPUT] bus is provided exactly when the STB signal rises and it
doesnot change until a new STBsignal occurs.

-Theoutput identifieron theOCNT0-OCNT3 [OUTPUT]bus is providedexactlywhenthe STBsignalrises
and it doesnot change until a new STBsignaloccurs.

- NP [OUTPUT]isset low when the penultimate STROBEis disabledallowinga new acquisition phase to
start while W.A.R.P.is still elaborating the last output.

- Whenthe last output has been provided,EP will be automaticallyset low.

14/19

PROGRAMMING TOOL
FUZZYSTUDIO 1.0 - W.A.R.P. Software Development Tool

Figure11. W.A.R.P. Software Development Tools

W.A.R.P.1.1

BASIC TOOLS

EDITOR

COMPILER

SU PPORT TOOLS

EXPORTER

INTEL HX

FILE

DEBUGGER

RS232

SGS-THOMSON has developed some software
tools(seefigure11)tosupporttheuseofW.A.R.P.1
allowing easy configurating and loading of the
memoriesandfunctionalsimulations.It isfullycom­patiblewith the W.A.R.P.board.

It has been designed in order to be used with the
followinghardware/softwarerequirements:

80386 (or higher) processor
VGA/ SVGAscreen

WindowsVersion3.0 or Higher

The constituting blocks are:
W.A.R.P.-SDT Editor:

it is a tool to define the fuzzy controller with a
User-Friendly Interface.

It is composed by:

– VariableEditor (to define the I/O variable)
– MembershipEditor (todefine the member-

ship functionshape)

– Rule Editor (to define the base ofknowledge)

W.A.R.P-SDT Compiler:

it generates the code to be loaded in W.A.R.P.
memories according to the data defined through
the editor. It also generates the data base for
Debugger,Exporterand Simulator.

W.A.R.P-SDT Debugger:

it allowsthe userto examinestep-by-stepthe fuzzy
computationforadefined application.Italsoallows

EMULATOR

Cmodel

MATLAB

FUZZYSTUDIO
APPLICATION

DEVELOPMENT



BOARD

FUZZYSTUDIO

W.A.R.P.-SDT

FUZZYSTUDIO

MODELER

RULE

EXTRACTOR

OPTIMIZER

FUZZYSTUDIO

SIMULATOR

Proprietary



ANCILLARY,

HIGH LEVEL

SUPPORT TOO LS



&



to checkthe results of the entire control process
by using a list of patterns stored into a file.

It allowsto show:

– Alpha values
– Theta values
– Defuzzificationpartial values
– Outputvalues

W.A.R.P.-SDTExporter:

itgeneratesfilestobeimported indifferentenviron­ments in order to develop W.A.R.P. based simula­tions exploitinguser-developedmodels.

It addressesthefollowing environments:
Standard C: the exporter generates a C function

that can be recalled by an user program
Matlab: the exporter generates a ’.M’ file that can

be used to performsimulations in Matlab environ­ments

W.A.R.P.-SDT Simulator:

it allows to:

– define modelsof the controlled system in

terms of differentialequations
– define the external inputs and set points
– resolve the differential equationsby using

Runge-Kuttaalgorithm
– functionallysimulate W.A.R.P.
– show the simulation results in graphic

charts.

15/19

W.A.R.P.1.1

W.A.R.P. ApplicationDevelopmentBoard

The boardhas been designedto be connected to
the RS232 port ofan IBMPC 386 (or higher), but
it canalsoworkstandalone.Inputsandoutputsare
providedatTTLcompatiblelevel.Theboard allows
the user to charge the rules and the membership
functions(seeW.A.R.P.-SDTUserManual)intothe
W.A.R.P. memories.

It can manageup to 16inputs and 16 outputs.
The clockgeneratorfrequencyon boardis24MHz.

Figure12. Board Block Diagram

An automatic trigger is used to synchronize
W.A.R.P. with the external environment (working
connectedwith a PC).

Whenthe boardisusedas a standalonedeviceall
the fuzzy data (membership functions and rules)
arestoredinEPROMs.Theboardallowsthestand­alone/PCworkingtobeselectedby settingaswitch
(seeW.A.R.P.-SDTUserManual). A blockdiagram
of the board is described in figure12.

16/1516/19

PACKAGE DIMENSIONS

W.A.R.P.1.1

Dim.

A 4.20 5.08 0.16 0.19
A1 0.56 0.02
A3 2.54 0.10

B 0.38 0.01
B1 1.14 0.003

D 30.10 30.35 1.18 1.19

D1 29.20 29.41 1.14 1.15
D3 27.69 28.70 1.11 1.13

E 30.10 30.35 1.18 1.19
E1 29.20 29.41 1.14 1.15
E3 27.69 28.70 1.11 1.13

e 1.27 0.05

D 30.10 30.35 1.18 1.19

D1 29.20 29.41 1.14 1.15
D3 27.69 28.70 1.11 1.13

F 0.50 0.020

G 1.78 0.070

Min. Typ. Max. Min. Typ. Max.

mm inch

Figure13. W.A.R.P. 84 Pin PLCC84 PlasticPackage

NE

Number of Pins

Pin 1

K1

ND

Number of Pins

E3
E1

E

D3 D1 D

B1

A1

A3

h

B

e

L

A

VR01534

h

17/19

W.A.R.P.1.1

PACKAGE DIMENSIONS

Dim.

A 33.58 1.332
B 17.78 0.700

C 2.24 0.088

c1 2.54 0.100

D 4.70 0.185
d1 1.40 0.055
d2 1.68 0.065

E 30.78 1.212
e 2.54 0.100
F 0.50 0.020

G 1.78 0.070

Min. Typ. Max. Min. Typ. Max.

mm inch

Figure14. W.A.R.P. 100 Pin CPGA100 Ceramic Package

18/19

W.A.R.P.1.1

Functionsindedicatedmemories inorderto reduce
the computationaltime. Therefore a great amount
of W.A.R.P.processing is based on a look-up table
approach rather than on on-line calculation.

Those Membership Functions (MFs), each one
portrayed by a configurableresolution of 2

6

or 2
elements,arestoredin fourinternalRAMs(1Kbyte
each). The consequentMFs, due to the different
modelling, are loaded in a single RAM by storing
for each MF its area andits barycentre.This is due
to theadoptionof the CenterofGravitydefuzzifica­tion method.

The downloading phase allows the setting of the
device, in terms of I/O number, universes of dis­courseandMF shapes.DuringthisphaseW.A.R.P.
prepares its internal memories for the on-line

programmemory. Thismicrocode,which drivesthe
on-line phase, is generated by the Compiler (see
W.A.R.P.-SDT User Manual) according to the
adoptedconfiguration.Thepossibleconfigurations
areshown in table 1.

7

During the on-line phase (up to 40MHz working
frequency),W.A.R.P.processes theinputdataand
producesitsoutputsaccordingtotheconfiguration
loadedin the downloadingphase.

W.A.R.P. is conceivedto work together with tradi­tional microcontrollerswhich shall perform normal
control tasks while W.A.R.P. will be indipendently
responsiblefor all the fuzzyrelatedcomputing.

W.A.R.P. is manufactured using the high perform­ance,reliableHCMOS4T (O.7µm)SGS-THOMSON
Microelectronicsprocess.

elaboration phase and loads the microcode in its

Table8. OrderingInformation

Part Number Maximum Frequency Supply Voltage Temperature Range Package

STFLWARP11/PG 40MHz 5±5% 0 °Cto 70 °C CPGA100

STFLWARP11/PL 40 MHz 5±5% 0 °Cto 70 °C PLCC84

Type Device

STFLSTUDIO10/KIT

STFLWARP11/PG

STFLWARP11/PL

FUZZYSTUDIO ADB FUZZYSTUDIO SDT

W.A.R.P.1.X
W.A.R.P.1.X programmer
EPROM programmer
RS-232 communication handler
Internal Clock

Development Tools

Variables and Rules Editor
W.A.R.P.Compiler/Debugger
Exporter forANSIC and MATLAB



Order Code Description Supported Target Functionalities System Requirement

STFLWARP11/PG

STFLAFM10/SW

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of thirdparties which mayresult from its use. No
license is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products arenot authorized for use ascritical components inlife support devices orsystems withoutexpress
written approval of SGS-THOMSON Microelectronics.

Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -

WTA-FAMforBuilding Rules
BACK-FAMforBuilding MFs

 1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved

FUZZYSTUDIO is a trademark of SGS-THOMSON Microelectronics



MS-DOS

,Microsoftand Microsoft Windowsare registered trademarks of Microsoft Corporation.

MATLAB

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Singapore - Spain - Sweden - Switzerland - Taiwan- Thailand - United Kingdom - U.S.A.

STFLWARP11/PL
STFLWARP20/PL
ANSI C
MATLAB



is a registered trademark ofMathworks Inc.



Rules Minimizer
Step-by-Step Simulation
Simulation from File
Local Tuning

MS-DOS 3.1or higher
Windows 3.0 or later
486, PENTIUMcompatible
8 MBRAM

19/19