ST VS6552 User Manual
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VS6552
VGA Color CMOS Image Sensor Module
FEATURES
■ Small physical size
■ Ultra low power standby mode
■ SmOP (Small Optical Package) technology
featuring integrated lens
■ Class leading low light performance
■ VGA resolution sensor
■ Compatible with STV0974 companion mobile
processor
■ High frame rate to minimize image distortion
■ Low EMI link (VisionLink) to STV0974
■ On-chip 10-bit ADC
■ Automatic dark calibr ati on
2
■ I
C communications
■ On-chip PLL
DESCRIPTION
The VS6552 is a VGA resolution SmOP sensor
module. SmOP technology combines the image
sensor and fixed focus lens system in a single
module. This approa ch provides a nu mber of advantages:
– SmOP technology is suitable for high volume
manufacturing
– S mOP can be plugged into a PCB mounted
flow soldered socket
– SmOP can be mounted close to noisy RF
source as differential signalling used to
transmit data has good immunity from radio
interference.
The sensor outputs raw Bayer colorized data to
the STV0974 companion mobile processor.
STV0974 then perf orms all color processi ng and
exposure control functions before outputting the
data in an appropriate interface format like YCbCr,
RGB or JPEG.
VS6552 offers an ul tra low power standby mode
that consumes less than 15 µW.
The SmOP lens has been designed to combine
class leading low light performance with good
depth of field to ensure excellent overall optical
performance. The lens is a 2 element moulded
plastic design.
The output data an d qualificatio n clock are transmitted over low noi se, low v oltag e and fu lly d ifferential links. VS6552 configuration registers are
controlled via a private I
2
C interface to STV0974.
APPLICATIONS
■ Mobile phone embedded camera system
■ PDA embedded camera or accessory camera
■ Wireless security camera
Table 1. Technical Specifications
Pixel resolution 644 x 484 (VGA)
Pixel size 5.6µm x 5.6µm
Exposure control +81 dB
Analog gain +24 dB (max)
Dynamic range 60 dB (Typical)
Signal to noise at
2
50cd.m
Supply voltage
Power consumption
Package size
Lens
Package type 14 pad SmOP
37 dB (Typical)
2.8 V (analog supply)
1.8 V (digital supply)
<75 mW (@30 frame/s)
<15 µW (standby mode)
10.7mm x 8.7mm x
6mm:SmOP1.5
9.5mm x 8.5mm x 6.1mm
:SmOP2
o
HFOV, f# 2.8
45
System attach Socket or flexible circuit
Rev. 2
1/26October 2004
VS6552
Table 2. Order Codes
Part Number
VS6552V015/T 2 [ -25; +55 ] °C SmOP1.5
VS6552V02C/T 2 [ -25; +55 ] °C SmOP2M
VS6552V02D/T 2 [ -25; +55 ] °C SmOP2ME
Operating
Temperature
Package
2/26
VS6552
TABLE OF CONTENT
Overview ........................................................................................................................................... 4
Sensor Overview 4
Signal Description ........................................................................................................................... 5
Functional Description .................................................................................................................... 6
Analog Video Block 6
Digital Video Block 6
Device Operating Modes 7
Power Management 7
Clock and Frame Rate Timing 8
Control and Video Interface Formats 9
Electrical Characteristics ................................................................................................................ 9
DC Electrical Characteristics 10
AC Electrical Characteristics 10
ESD Handling Characteristics 13
Optical specification...................................................................................................................... 13
Defect Categorization .................................................................................................................... 13
Pixel Defects 13
Package Mechanical Data ............................................................................................................. 13
SmOP1.5 Module Outline 13
SmOP2 M Module Outline 13
SmOP2 ME Module Outline 13
Application Information................................................................................................................. 23
Socket 23
EMC and Shielding 23
Revision History............................................................................................................................. 25
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VS6552
1 OVERVIEW
1.1 Sensor Overview
The VS6552 VGA image sensor produces raw
VGA digital video data at up to 30 frames per second. The image data is digit ized using an internal
10-bit column ADC. The resulting 10-bit output
data includes embe dded codes for synchronization. The data is formatted and transmi tted over a
fully differential link. The data is accompanied by a
qualifying clock th at is transmitted ov er an identical fully differential link .
The sensor is ful ly config urab le us ing an I
2
C inter-
face.
The sensor is optimized for high volume mobile
applications
1.1.1 Typical Application - Mobile Application
Figure 1. Camera System Using STV0974
The VS6552 is an image sensor, it should be used
in conjunction with the STMicroelectronics
STV0974 companion processor. The coprocessor
and the sensor together form a complete im aging
system.
The sensors main function is to convert the viewed
scene into a data stream. The companion processor function is to manage the sensor so that it can
produce the best possible data and to process the
data stream into a form which is easily handled by
up stream mobile baseband or MMP chipsets.
The sensor supplies high speed clock signal to the
processor and provides the embedded control sequences which allow the co processor to synchronize with the frame and line level timings. The
processor then performs the color processing on
the raw image data from the sensor before supplying the final image data to the host.
STV0974
VS6552
Pixel
Array
ADC
Microprocessor
MSCL
MSDA
PCLKP
PCLKN
Digital Logic
PDATAP
PDATAN
VP
VC
Interface Logic
SCL
SDA
DIO[0:13]
CLK
PDN
4/26
2 SIGNAL DESCRIPTION
Table 3. Signal Description
Pad Number Pad Name I/O Type Description
Power supplies
VS6552
System
Control
Data
1CEXT PWR
Connection to capacitor
a
2 AGND PWR Analog ground
3 AVDD PWR Analog power
8 GND PWR Digital ground
11 VDD PWR Digital power
4PDN I
Power down control
b
5 CLK I System clock input
6 MSCL I Serial communication clock
7 MSDA I/O Serial communication data
9 PCLKN vLVDS output Output qualifying clock
10 PCLKP vLVDS output Output qualifying clock
12 PDATAN vLVDS output Serial output data
13 PDATAP vLVDS output Serial output data
Not connected
14 Not connected
NC Not connected
a.Internally generated v oltage that needs to be externally decoupled with a 100 nF, 5 V capacitor
b.Signal is active low
Note: The physical position of t he sign als on the pa ckag e can be found by referi ng t o th e pino ut inf ormat ion in Chapter7: Package Mechan-
ical Data.
5/26
VS6552
3 FUNCTIONAL DESCRIPTION
The first sections of this chapter detail the main
blocks in the device:
■ Analog video block
■ Digital video block
The later sections of th is chapter describe other
functional aspects of the de vice. Devic e level op erating modes, including suspend, are detailed
Figure 2. Analog Video Block
SRAM readout
X-Address
Column ADC
raw sensor data
Power
management
3.1 Analog Video Block
3.1.1 Features
■ ADC: 10-bit A/D converter - SRAM readout
■ Dynamic range 60 dB (typical)
■ SNR 37 dB @ 50 cd.m
2
(typical)
Timing signals
Digital
logic
VGA
pixel
array
3.1.2 Analogue Block Diagram
The analog video block f rom Figure 4, consis ts of
a VGA resolution pi xel a rray, p ower m anagem ent
circuitry. The digi tal block provides all timing signals to drive the analog block.
Pixel voltage values are read out and digitized using the address decoders and column ADC
3.2 Digital Video Block
3.2.1 Features
■ Frame rate: 30 frame/s max. (VGA) can be
reduced down to less than 3 frame/s (VGA)
■ Automatic dark calibration to ensure consistent
video level over varying scenes
Y address
Timing signals
■ Fixed pattern noise (FPN) data gathering
■ Line and frame statistics gathering
■ On-chip Power-On-Reset cell
■ Single video output format: VGA 640 x 480
■ H - Scaler function to aid software only
viewfinder implementations
3.2.2 Dark Calibration Algorithm
VS6552 runs a dark calibrati on algorithm on the
raw image data to control the video offsets caused
by dark current. This en sures that a high quality
image is output over a rang e of operating conditions. First frame dark level is corre ctl y cal ibrat ed,
for subsequent frames the a djust ment o f the d ark
level is damped by a leaky integrator function to
avoid possible frame to frame flicker.
6/26
VS6552
3.2.3 Image Statistics
VS6552 generates image s tatistics which can be
used by STV0974 as an input to an auto exposure
controller (AEC), a utomatic gain controller (AGC )
and automatic white balance (AWB). .
3.3 Device Operating Modes
3.3.1 Standby
This is the lowest power consumption mode. I
2
communications to STV 097 4 a re not supported in
this mode. The clock input pad, PLL and the video
blocks are powered down.
3.3.2 Sleep Mode
2
Sleep mode preserves the contents of the I
ister map. I
2
C communications to STV0974 are
C reg-
supported in this mode. The sleep mode is selected via a serial interface command sent by
STV0974. The data pads go high at the end of the
current frame. At this point the video block and
Table 4. VS6552 Power-up Sequence
Design block powered down
Mode
I2C Digital
PLL & CLK
pins
PLL power down. The internal video timing is reset
to the start of a video frame in prepara tion for the
enabling of active vide o. The values of the serial
interface registers like exposure and gain are preserved. The system clock must remain active to allow communication with the sensor.
3.3.3 Clock Active Mode
This mode is sim ilar to ‘sleep mode’ except t hat
the PLL is now powered up to permit a PCLKP/
PCLKN signal to be delivered to STV0974. The
C
PDATAP/PDATAN pads remain in ac tive. The vid eo block is powered down.
3.3.4 Idle Mode
VCAP is generated. The analog video block is now
powered up but the array is he ld in rese t and the
output PDATAP/PDATAN pads remain high.
3.3.5 Video
The VS6552 streams live video to the STV0974.
Video data
a b
Output pins Analog
inhibit
Standby
(PDN low)
Sleep No Yes Yes Yes Yes Yes
Clock
active
Idle No No No No No Yes
Video
a.PLL (Phase Locked Loop) generates fast system clock for STV0974
b.PLL, PCLKP and PCLKN pins
3.4 Power Management
VS6552 requires a dual power supply. The analog
circuits are powered by a nominal 2.8 V supply
Yes Yes Yes Yes Yes Yes
No No No Yes Yes Yes
No No No No No No
3.4.1 Power-up, Power-down Procedures
The power up and power down procedures are de-
tailed in the following Figure 3.
while the digital logic and digi tal I/O are powered
by a nominal 1.8 V supply.
7/26
VS6552
Figure 3. VS6552 Power-up Sequence
VDD (1.8V)
AVDD (2.8V)
PDN
CLK
PCLKP/N
PDATAP/N
MSDA
MSCL
Mode Change: Sleep -> Clock active Mode Command: Idle -> Streaming
and enable data qualification clock and
Standby Idle
general configuration
Sleep Streaming
Clock active
Mode Change: Clock active -> Idle
also enable data output
3.4.2 Active Signals with Unpowered VS6552
All signals going into the VS6552 must be either at
a low state or high impe dance when powe r is removed from the device. The exceptions to this rule
are the I
2
C lines which may be at a low or high
state and the clock which can be active.
3.5 Clock and Frame Rate Timing
3.5.1 Video Frame Rate Control
The output frame rate of VS6552 c an be reduced
by extending the frame length. The extension is
achieved by adding 'blank' video lines to act as
timing padding. This is advantageous as it does
not reduce the pixel readout rate and therefore
does not introduce unwanted motion distribution
effects to the image. The frame rate can be reduced from the default 3 0 fram e/s at VG A res olution to less than 3 frame/s at VGA resolution.
3.5.2 PLL and Clock Input
A PLL IP block is embedded. This block generates
all necessary int ernal clocks from an inp ut range
defined in Table 5. The input clock pad accepts up
to 26 MHz signals.
Table 5. System Input Clock Frequency Range
System clock frequency
Min. (MHz) Max. (MHz)
6.5 26
a.The standard su ppor ted i nput fre quenci es (i n MHz) are as
follows: 6.5, 8.4, 9, 9.6, 9.72, 12,13, 16.8, 18, 19.2,
19.44, 26.
a
3.5.3 Clock Input Type
VS6552 can receive the following clock types:
■ Single ended CMOS
■ Single ended Sine wave
■ Clock can be AC or DC coupled
The clock is fail-safe.
8/26
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