ST VNP20N07FI, VNB20N07, VNV20N07 User Manual

VNP20N07FI

®

FULLY AUTOPROTECTED POWER MOSFET

TYPE V

VNP20N07FI VNB20N07 VNV20N07

■ LINEAR CURRENT LIMITATION ■ THERMAL SHUT DOWN ■ SHORT CIRCUIT PROTECTION ■ INTEGRATED CLAM P ■ LOW CURRENT DRAWN FROM INPUT PIN ■ DIAGNOST IC FEE DBA CK THRO UG H INP UT

clamp

70 V 70 V 70 V

■ ESD PROTECTION ■ DIRECT ACCESS TO THE GATE OF THE

POWER MOSFET (ANALOG DRIVING)

■ COMPATIBLE WITH STANDARD POWER

MOSFET

DESCRIPT ION

The VNP20N07FI, VNB20N07 and VNV20N07 are monolithic devices made using STMicroelectronics VlPower M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Built-in thermal shut-down, linear current limitation and overvoltage clamp protect the chip in harsh

R

DS(on)

0.05 Ω

I

lim

20 A 20 A 20 A

VNB20N07/VNV20N07

"OMNIFET":

ISOWATT220

3

1

D2PAK TO-263

enviroments. Fault feedback can be detected by monitoring the

voltage at the input pin.

3

2

1

10

1

PowerSO-10

BLOCK DIAG RAM (∗)

(∗) PowerSO-10 Pin Configuration : INPUT = 6,7,8,9,10; SOURCE = 1,2,4,5; DRAIN = TAB

June 1998

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VNP20N07FI-VNB20N07-VNV20N07

ABSOLUTE MAXIMUM RATING

Symbol Parameter Value Unit

V

P

T

Drain-source Voltage (Vin = 0) Internally Clamped V

DS

Input Voltage 18 V

in

I

Drain Current Internally Limited A

D

I

Reverse DC Output Current -28 A

R

Electrostatic Discharge (C= 100 pF, R=1.5 KΩ) 2000 V

esd

Total Dissipation at Tc = 25 oC8334W

tot

T

Operating Junction Temperature Internally Limited

j

Case Operating Temperature Internally Limited

c

Storage Temperature -55 to 150

stg

THERMAL DATA

R

thj-case

R

thj-amb

Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max

PowerSO-10

D2PAK

ISOWATT220 PowerSO-10 D2PAK

3.75

62.5

ISOWATT220

1.5 50

1.5

62.5

o o

o

C

o

C

o

C

C/W C/W

ELECTRICAL CHARACTERISTICS (T

= 25 oC unless otherwise specified)

case

OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

CLAMP

Drain-source Clamp

ID = 200 mA V

= 0 607080 V

in

Voltage

V

CLTH

Drain-source Clamp

ID = 2 mA V

= 0 55 V

in

Threshold Voltage

V

INCL

Input-Source Reverse

I

= -1 mA -1 -0.3 V

in

Clamp Voltage

I

DSS

ISS

Zero Input Voltage Drain Current (V

in

Supply Current from

= 0)

= 13 V V

V

DS

V

= 25 V V

DS

= 0

in

= 0

in

VDS = 0 V Vin = 10 V 250 500 µA

50

200

Input Pin

ON (∗)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

IN(th)

Input Threshold

V

= Vin ID + Iin = 1 mA 0.8 3 V

DS

Voltage

R

DS(on)

Static Drain-source On Resistance

Vin = 10 V ID = 10 A V

= 5 V ID = 10 A

in

0.05

0.07

DYNAMIC

µA µA

Ω Ω

Symbol Parameter Test Conditions Min. Typ. Max. Unit

gfs (∗) Forward

V

= 13 V ID = 10 A 13 17 S

DS

Transconductance

C

Output Capacitance V

oss

= 13 V f = 1 MHz V

DS

= 0 500 800 pF

in

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VNP20N07FI-VNB 20N07-VN V20N07

ELECTRICAL CHARACTERISTICS (continued) SWITCHING (∗∗)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

t

d(on)

t

d(off)

t

d(on)

t

d(off)

t

(di/dt)

Q

Turn-on Delay Time Rise Time

r

Turn-off Delay Time Fall Time

f

Turn-on Delay Time Rise Time

r

Turn-off Delay Time Fall Time

f

Turn-on Current Slope V

on

Total Input Charge VDD = 12 V ID = 10 A V

i

V

= 15 V Id = 10 A

DD

V

= 10 V R

gen

(see figure 3)

V

= 15 V Id = 10 A

DD

V

= 10 V R

gen

(see figure 3)

= 15 V ID = 10 A

DD

V

= 10 V R

in

gen

= 10 Ω

= 1000 Ω

= 10 Ω

= 10 V 60 nC

in

90 240 430 150

800

1.5

3.5 60 A/µs

SOURCE DRAIN DIO DE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

(∗) Forward On Voltage ISD = 10 A Vin = 0 1.6 V

SD

trr(∗∗)

Q

rr

I

RRM

Reverse Recovery Time Reverse Recovery

(∗∗)

Charge Reverse Recovery

(∗∗)

Current

I

= 10 A di/dt = 100 A/µs

SD

V

= 30 V Tj = 25 oC

DD

(see test circuit, figure 5)

165

0.55

6.5

180 400 800 300

1200

2.2

6

10

5.5

ns ns ns ns

ns

µs µs µs

ns

µC

A

PROTECTION

Symbol Parameter Test Conditions Min. Typ. Max. Unit

I

t

dlim

T

jsh

T

jrs

I

(∗∗) Fault Sink Current Vin = 10 V

gf

E

as

(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (∗∗) Parameters guaranteed by design/characterizat i on

Drain Current Limit Vin = 10 V VDS = 13 V

lim

(∗∗) Step Response

Current Limit

(∗∗) Overtemperature

V

= 5 V VDS = 13 V

in

Vin = 10 V V

= 5 V

in

14 14

150

Shutdown

(∗∗) Overtemperature Reset 135

V

= 5 V

in

(∗∗) Single Pulse

Avalanche Energy

starting Tj = 25 oC VDD = 20 V V

= 10 V R

in

= 1 KΩ L = 10 mH

gen

0.95 J

20 20

29 70

50 20

28 28

60

140

A A

µs µs

o

C

o

C

mA mA

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VNP20N07FI-VNB20N07-VNV20N07

PROTECTION FEATURES

During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50 KHz. The only difference from the user’s standpoint is that a small DC current (I

) flows into the Input pin in order to

iss

supply the internal circuitry. The device integrates:

- OVERVOLTAGE CLAMP PROTECTION:

internally set at 70V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads.

- LINEAR CURRENT LIMITER CIRCUIT: limits

the drain current Id to Ilim whatever the Input pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold T

jsh

.

- OVERTEMPERATURE AND SHORT CIRCUIT

PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs at minimum 150 restarted when the chip temperature falls below 135

o

C. The device is automatically

o

C.

- STATUS FEEDBACK: In the case of an

overtemperature fault condition, a Status Feedback is provided through the Input pin. The internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100 Ω. The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential.

Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit (with a small increase in R

DS(on)

).

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