ST VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 User Manual

VNN7NV04, VNS7NV04 VND7NV04, VND7NV04-1

OMNIFET II fully autoprotected Power MOSFET

Features

	Type	RDS(on)	Ilim	Vclamp
	VNN7NV04
	VNS7NV04	60 mΩ	6 A	40 V
	VND7NV04
	VND7NV04-1

■Linear current limitation

■Thermal shutdown

■Short circuit protection

■Integrated clamp

■Low current drawn from input pin

■Diagnostic feedback through input pin

■ESD protection

■Direct access to the gate of the Power MOSFET (analog driving)

■Compatible with standard Power MOSFET in compliance with the 2002/95/EC European Directive

2

		3
	1	2
		SO-8
	SOT-223

	3	3
		2
	1	1
	TO252 (DPAK)	TO251 (IPAK)

Description

The VNN7NV04, VNS7NV04, VND7NV04 VND7NV04-1, are monolithic devices designed in STMicroelectronics VIPower M0-3 Technology, intended for replacement of standard Power MOSFETs from DC up to 50 kHz applications. Built in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh environments.

Fault feedback can be detected by monitoring the voltage at the input pin.

Table 1.	Device summary
Package			Order codes
		Tube	Tube (lead-free)	Tape and reel	Tape and reel (lead-free)
SOT-223		VNN7NV04	-	VNN7NV0413TR	-
SO-8		VNS7NV04	-	VNS7NV0413TR	-
TO-252		VND7NV04	VND7NV04-E	VND7NV0413TR	VND7NV04TR-E
TO-251		VND7NV04-1	VND7NV04-1-E	-	-
September 2010			Doc ID 7383 Rev 3		1/37

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Contents	VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1

Contents

1	Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
2	Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 7
	2.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	2.3	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
3	Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	3.1	Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	3.2	SO-8 maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . .	17
	3.3	DPAK maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . .	18
	3.4	SOT-223 maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . .	19
4	Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
	4.1	SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	4.2	SOT-223 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	4.3	DPAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
5	Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
	5.1	TO-251 (IPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	5.2	TO-252 (DPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
	5.3	SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
	5.4	SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	5.5	SOT-223 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	5.6	SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
	5.7	DPAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	5.8	IPAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
6	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		36

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List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5. SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 6. SOT-223 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7. DPAK thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 8. TO-251 (IPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 9. TO-252 (DPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10. SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 11. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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List of figures	VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Test circuit for diode recovery times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 8. Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 9. Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 10. Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11. Static drain-source on resistance vs input voltage (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 12. Static drain-source on resistance vs input voltage (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 13. Source-drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 14. Static drain source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 15. Turn-on current slope (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 16. Turn-on current slope (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 17. Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 18. Static drain-source on resistance vs Id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 19. Input voltage vs input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 20. Turn-off drain source voltage slope (part 1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 21. Turn-off drain source voltage slope (part 2/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 22. Capacitance variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 23. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 24. Normalized on resistance vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 25. Switching time resistive load (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 26. Switching time resistive load (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 27. Normalized input threshold voltage vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 28. Normalized current limit vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 29. Step response current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 30. SO-8 maximum turn-off current versus load inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 31. SO-8 demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 32. DPAK maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 33. DPAK demagnetization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 34. SOT-223 maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 35. SOT-223 demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 36. SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 37. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 38. SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 39. Thermal fitting model of an OMNIFET II in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 40. SOT-223 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 41. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 42. SOT-223 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 43. Thermal fitting model of an OMNIFET II in SOT-223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 44. DPAK PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 45. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 46. DPAK thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 47. Thermal fitting model of an OMNIFET II in DPAK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 48. TO-251 (IPAK) package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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Figure 49. TO-252 (DPAK) package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 50. SOT-223 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 51. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 52. SOT-223 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 53. SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 54. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 55. DPAK footprint and tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 56. DPAK tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 57. IPAK tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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Block diagram and pin description	VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1

1 Block diagram and pin description

Figure 1.		Block diagram
			DRAIN
			2
			Overvoltage
			Clamp
INPUT		Gate
	1
		Control
			Linear
		Over	Current
			Limiter
		Temperature
			3
			SOURCE	FC01000

Figure 2. Configuration diagram (top view)

SO-8 Package(1)

SOURCE			1	8	DRAIN
SOURCE					DRAIN
SOURCE			4	5	DRAIN
INPUT					DRAIN

1. For the pins configuration related to SOT-223, DPAK, IPAK see outlines at page 1.

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2 Electrical specifications

Figure 3. Current and voltage conventions

ID

VDS

DRAIN

IIN RIN

INPUT

SOURCE

VIN

2.1Absolute maximum ratings

Table 2.	Absolute maximum ratings
Symbol	Parameter			Value		Unit
		SOT-223		SO-8	DPAK/IPAK
VDS	Drain-source voltage (VIN=0 V)		Internally clamped			V
VIN	Input voltage		Internally clamped			V
IIN	Input current		+/-20			mA
RIN MIN	Minimum input series impedance		150			Ω
ID	Drain current		Internally limited			A
IR	Reverse DC output current		-10.5			A
VESD1	Electrostatic discharge (R=1.5 KΩ,		4000			V
	C=100 pF)
VESD2	Electrostatic discharge on output pin		16500			V
	only (R=330 Ω, C=150 pF)
Ptot	Total dissipation at Tc=25 °C	7		4.6	60	W
	Maximum switching energy
EMAX	(L=0.7 mH; RL=0 Ω; Vbat=13.5 V;	40			40	mJ
	Tjstart=150 ºC; IL=9 A)
	Maximum switching energy
EMAX	(L=0.6 mH; RL=0 Ω; Vbat=13.5 V;			37		mJ
	Tjstart=150 ºC; IL=9 A)
Tj	Operating junction temperature		Internally limited			°C
Tc	Case operating temperature		Internally limited			°C
Tstg	Storage temperature			-55 to 150		°C

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Electrical specifications	VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1

2.2Thermal data

Table 3.	Thermal data
Symbol	Parameter		Value				Unit
		SOT-223	SO-8		DPAK	IPAK
Rthj-case	Thermal resistance junction-case max	18			2.1	2.1	°C/W
Rthj-lead	Thermal resistance junction-lead max		27				°C/W
Rthj-amb	Thermal resistance junction-ambient max	96(1)	90(1)		65(1)	102	°C/W

1.When mounted on a standard single-sided FR4 board with 0.5 mm2 of Cu (at least 35 µm thick) connected to all DRAIN pins.

2.3Electrical characteristics

-40 °C < Tj < 150 °C, unless otherwise specified.

Table 4.			Electrical characteristics
Symbol			Parameter				Test conditions	Min	Typ	Max	Unit
Off
VCLAMP			Drain-source clamp	VIN=0 V; ID=3.5 A				40	45	55	V
			voltage
VCLTH			Drain-source clamp	VIN=0 V; ID=2 mA				36			V
			threshold voltage
VINTH			Input threshold voltage	VDS=VIN; ID=1 mA				0.5		2.5	V
I		ISS	Supply current from input	V	DS	=0 V; V	=5 V		100	150	µA
			pin				IN
VINCL			Input-source clamp	IIN=1 mA				6	6.8	8	V
			voltage	IIN=-1 mA				-1.0		-0.3
IDSS			Zero input voltage drain	VDS=13 V; VIN=0 V; Tj=25 °C						30	µA
			current (VIN=0 V)	V	DS	=25 V; V =0 V				75
							IN
On
RDS(on)			Static drain-source on	VIN=5 V; ID=3.5 A; Tj=25 °C						60	mΩ
			resistance	VIN=5 V; ID=3.5 A						120
Dynamic (Tj=25 °C, unless otherwise specified)
g		(1)	Forward	V		=13 V; I =3.5 A			9		S
	fs		transconductance		DD		D
COSS			Output capacitance	VDS=13 V; f=1 MHz; VIN=0 V					220		pF

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VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1			Electrical specifications
Table 4.	Electrical characteristics (continued)
Symbol	Parameter	Test conditions	Min	Typ	Max	Unit
Switching (Tj=25 °C, unless otherwise specified)
td(on)	Turn-on delay time			100	300	ns
		VDD=15 V; ID=3.5 A
tr	Rise time			470	1500	ns
		Vgen=5 V; Rgen=RIN MIN=150 Ω
td(off)	Turn-off delay time			500	1500	ns
		(see figure Figure 4.)
tf	Fall time			350	1000	ns
td(on)	Turn-on delay time			0.75	2.3	µs
		VDD=15 V; ID=3.5 A
tr	Rise time			4.6	14.0	µs
		Vgen=5 V; Rgen=2.2 KΩ
td(off)	Turn-off delay time			5.4	16.0	µs
		(see figure Figure 4.)
tf	Fall time			3.6	11.0	µs
(dI/dt)on	Turn-on current slope	VDD=15 V; ID=3.5 A		6.5		A/µs
		Vgen=5 V; Rgen=RIN MIN=150 Ω
Qi	Total input charge	VDD=12 V; ID=3.5 A; VIN=5 V		18		nC
		Igen=2.13 mA (see figure Figure 7.)
Source drain diode (Tj=25 °C, unless otherwise specified)
(1)	Forward on voltage	ISD=3.5 A; VIN=0 V		0.8		V
VSD
trr	Reverse recovery time	ISD=3.5 A; dI/dt=20 A/µs		220		ns
Qrr	Reverse recovery charge	VDD=30 V; L=200 µH		0.28		µC
		(see test circuit, figure Figure 5.)
IRRM	Reverse recovery current			2.5		A
Protections (-40 °C < Tj < 150 °C, unless otherwise specified)
Ilim	Drain current limit	VIN=5 V; VDS=13 V	6	9	12	A
tdlim	Step response current	VIN=5 V; VDS=13 V		4.0		µs
	limit
Tjsh	Over temperature		150	175	200	°C
	shutdown
Tjrs	Over temperature reset		135			°C
Igf	Fault sink current	VIN=5 V; VDS=13 V; Tj=Tjsh		15		mA
	Single pulse avalanche	starting Tj=25 °C; VDD=24 V
Eas		VIN=5 V Rgen=RIN MIN=150 Ω; L=24 mH	200			mJ
	energy
		(see figures Figure 6. & Figure 8.)
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %

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Protection features	VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1

3 Protection features

During normal operation, the input pin is electrically connected to the gate of the internal Power MOSFET through a low impedance path.

The device then behaves like a standard Power MOSFET and can be used as a switch from DC up to 50 kHz. The only difference from the user’s standpoint is that a small DC current IISS (typ. 100µA) flows into the input pin in order to supply the internal circuitry.

The device integrates:

●Overvoltage clamp protection: internally set at 45 V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads.

●Linear current limiter circuit: limits the drain current ID to Ilim whatever the input pin voltages. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the over temperature threshold Tjsh.

●Over temperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Over temperature cutout occurs in the range 150 to 190 °C, a typical value being 170 °C. The device is automatically restarted when the chip temperature falls of about 15 °C below shutdown temperature.

●Status feedback: in the case of an over temperature fault condition (Tj > Tjsh), the device tries to sink a diagnostic current Igf through the input pin in order to indicate fault condition. If driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so

that the input pin driver is not able to supply the current Igf, the input pin will fall to 0 V. This will not however affect the device operation: no requirement is put on the current capability of the input pin driver except to be able to supply the normal operation drive current IISS.

Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL logic circuit.

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Doc ID 7383 Rev 3

VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1	Protection features
Figure 4. Switching time test circuit for resistive load

ID
	90%
tr	10%	tf
td(on)		t
		t
Vgen		d(off)
		t

Figure 5. Test circuit for diode recovery times

A

A

D

I

OMNIFET

FAST

L=100uH

DIODE

B

S

B

150Ω

D

Rgen

VDD

Vgen

I

OMNIFET

S

8.5 Ω

Doc ID 7383 Rev 3

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Protection features	VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
Figure 6. Unclamped inductive load test	Figure 7. Input charge test circuit
circuits

VIN

PW

VIN

RGEN

Figure 8. Unclamped inductive waveforms

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Doc ID 7383 Rev 3