VNQ830P-E
Quad channel high-side driver
Features
Typ e R
VNQ830P-E 65 mΩ
1. Per each channel.
■ ECOPACK
■ Automotive Grade: compliance with AEC
DS(on)
(1)
®
: lead free and RoHS compliant
guidelines
■ Very low standby current
■ CMOS compatible input
■ On-state open-load detection
■ Off-state open-load detection
■ Thermal shutdown protection and diagnosis
■ Undervoltage shutdown
■ Overvoltage clamp
■ Output stuck to V
■ Load current limitation
■ Reverse battery protection
■ Electrostatic discharge protection
CC
I
OUT
6A 36V
detection
V
CC
SO-28 (double island)
Description
The VNQ830P-E is a quad HSD formed by
assembling two VND830P-E chips in the same
SO-28 package. The VND830P-E is a monolithic
device made using| STMicroelectronics™
VIPower™ M0-3 technology. The VNQ830P-E is
intended for driving any type of multiple load with
one side connected to ground.
The active V
device against low energy spikes (see ISO7637
transient compatibility table). Active current
limitation combined with thermal shutdown and
automatic restart protects the device against overload. The device detects the open-load condition
in both the on and off-state.
pin voltage clamp protects the
CC
In the off-state the device detects if the output is
shorted to V
. The device automatically turns off
CC
in the case where the ground pin becomes
disconnected.
Table 1. Device summary
Package
SO-28 VNQ830P-E VNQ830PTR-E
February 2011 Doc ID 10861 Rev 4 1/27
Tube Tape and reel
www.st.com
1
VNQ830P-E Contents
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17
3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 17
3.1.2 Solution 2: a diode (D
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
) in the ground line . . . . . . . . . . . . . . . . . . . . 18
GND
3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Maximum demagnetization energy (V
= 13.5 V) . . . . . . . . . . . . . . . . . 20
CC
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 10861 Rev 4 2/27
VNQ830P-E List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. V
Table 8. Switching (V
Table 9. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 13. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 14. Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
- output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
= 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
Doc ID 10861 Rev 4 3/27
VNQ830P-E List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 17. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 21. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 23. Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 25. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 26. Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 27. SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 28. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 22
Figure 29. SO-28 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 30. Thermal fitting model of a quad channel HSD in SO-28. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. SO-28 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 33. SO-28 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Doc ID 10861 Rev 4 4/27
VNQ830P-E Block diagram and pin description
1 Block diagram and pin description
Figure 1. Block diagram
V
CC1,2
V
cc
CLAMP
OVERVOLTAGE
UNDERVOLTAGE
GND1,2
INPUT1
STAT US1
INPUT2
STAT US2
GND3,4
INPUT3
STAT US3
INPUT4
STAT US4
OVERTEMP. 1
OVERTEMP. 2
V
cc
CLAMP
OVERTEMP. 3
OVERTEMP. 4
LOGIC
LOGIC
CLAMP 1
DRIVER 1
CURRENT LIMITER 1
OPEN-LOAD ON 1
OPEN-LOAD OFF 1
OVERVOLTAGE
UNDERVOLTAGE
CLAMP 3
DRIVER 3
CURRENT LIMITER 3
OPEN-LOAD ON 3
OPEN-LOAD OFF 3
CLAMP 2
DRIVER 2
CURRENT LIMITER 2
OPEN-LOAD ON 2
OPEN-LOAD OFF 2
CLAMP 4
DRIVER 4
CURRENT LIMITER 4
OPEN-LOAD ON 4
OPEN-LOAD OFF 4
OUTPUT1
OUTPUT2
V
CC3,4
OUTPUT3
OUTPUT4
Doc ID 10861 Rev 4 5/27
VNQ830P-E Block diagram and pin description
Figure 2. Configuration diagram (top view)
VCC1,2
1
GND 1,2
INPUT1
STATUS1
STATUS2
INPUT2
1,2
V
CC
3,4
V
CC
GND 3,4
INPUT3
STATUS3
STATUS4
INPUT4
V
3,4
CC
Table 2. Suggested connections for unused and not connected pins
14
28
15
V
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT3
OUTPUT3
OUTPUT3
OUTPUT4
OUTPUT4
OUTPUT4
V
CC
CC
1,2
3,4
Connection / pin Status N.C. Output Input
Floating X X X X
To ground X
Through 10 KΩ
resistor
Doc ID 10861 Rev 4 6/27
VNQ830P-E Electrical specifications
2 Electrical specifications
2.1 Absolute maximum ratings
Stressing the device above the rating listed in Ta ble 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality
document.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
- V
- I
I
- I
I
V
E
T
CC
CC
GND
OUT
OUT
I
IN
STAT
ESD
MAX
P
tot
T
stg
DC supply voltage 41 V
Reverse DC supply voltage - 0.3 V
DC reverse ground pin current - 200 mA
DC output current Internally limited A
Reverse DC output current - 6 A
DC input current +/- 10 mA
DC status current +/- 10 mA
Electrostatic discharge (Human Body Model: R=1.5 KΩ;
C = 100 pF)
–INPUT
–STATUS
–OUTPUT
–V
CC
Maximum switching energy
(L = 1.5 mH; R
= 0 Ω; V
L
Power dissipation (per island) at T
Junction operating temperature Internally limited °C
j
= 13.5 V; T
bat
= 150 °C; IL = 9 A)
jstart
= 25 °C 6.25 W
lead
4000
4000
5000
5000
140 mJ
Storage temperature - 55 to 150 °C
V
V
V
V
Doc ID 10861 Rev 4 7/27
VNQ830P-E Electrical specifications
2.2 Thermal data
Table 4. Thermal data (per island)
Symbol Parameter Value Unit
R
thj-lead
R
thj-amb
R
thj-amb
Thermal resistance junction-lead 15 °C/W
Thermal resistance junction-ambient
(one chip ON)
Thermal resistance junction-ambient
(two chips ON)
1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35 µm thick) connected
to all V
2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35 µm thick) connected to
all V
pins. Horizontal mounting and no artificial air flow.
CC
pins. Horizontal mounting and no artificial air flow.
CC
2.3 Electrical characteristics
Values specified in this section are for 8 V < V
otherwise stated.
Figure 3. Current and voltage conventions
I
S3,4
V
CC3,4 V
I
IN1
V
STAT3
V
IN4
V
I
STAT1
I
IN2
I
STAT2
I
IN3
I
STAT3
I
IN4
I
STAT4
STAT4
V
IN1
V
STAT1
V
IN2
V
STAT2
V
IN3
INPUT1
STATUS1
INPUT2
STATUS2
INPUT3
STATUS3
INPUT4
STATUS4
GND
(1)
60
(1)
46
< 36 V; -40°C < Tj < 150°C, unless
CC
V
CC3,4
3,4
I
GND3,4
V
CC1,2
OUTPUT1
OUTPUT2
OUTPUT3
OUTPUT4
GND
1,2
I
GND1,2
I
OUT1
I
OUT2
I
OUT3
I
OUT4
V
OUT4
V
F1(1)
OUT3
I
V
S1,2
OUT2
44
31
V
(2)
(2)
OUT1
V
°C/W
°C/W
CC1,2
1. VFn = V
Table 5 . Power
CCn
- V
during reverse battery condition.
OUTn
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
Operating supply
CC
voltage
Undervoltage shutdown 3 4 5.5 V
USD
Overvoltage shutdown 36 V
OV
5.5 13 36 V
Doc ID 10861 Rev 4 8/27
VNQ830P-E Electrical specifications
Table 5. Power (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
R
I
L(off1)
I
L(off2)
I
L(off3)
I
L(off4)
Table 6. Protections
Symbo
T
TSD
T
T
hyst
t
SDL
I
lim
V
demag
On-state resistance
ON
Supply current
I
S
Off-state output current V
Off-state output current V
Off-state output current
Off-state output current
l
Parameter Test conditions Min. Typ. Max. Unit
Shutdown temperature 150 175 200 °C
Reset temperature 135 °C
R
Thermal hysteresis 7 15 °C
Status delay in overload
conditions
Current limitation
Turn-off output clamp
voltage
I
= 2 A; Tj = 25°C
OUT
= 2 A; V
I
OUT
Off-state; V
= V
V
IN
OUT
Off-state; V
= V
V
IN
OUT
On-state; V
= 0 A
I
OUT
= V
IN
OUT
= 0V; V
IN
V
= V
IN
OUT
= 125°C
T
j
V
= V
IN
OUT
=25°C
T
j
> T
T
j
TSD
V
= 13 V 6 9 15 A
CC
5.5 V < V
I
= 2 A;
OUT
L = 6 mH
65
> 8 V
CC
= 13 V;
CC
= 0 V
= 13 V;
CC
= 0 V; Tj = 25°C
= 13 V; V
CC
IN
= 5 V;
130mΩmΩ
12 40 µA
12 25 µA
57mA
= 0 V 0 50 µA
= 3.5 V -75 0 µA
OUT
= 0V; V
= 0 V; V
CC
CC
= 13 V;
= 13 V;
5µA
3µA
20 µs
< 36 V 15 A
CC
V
CC
-41 V
CC
-48 V
-55 V
CC
Note: To ensure long term reliability under heavy overload or short circuit conditions, protection
and related diagnostic signals must be used together with a proper software strategy. If the
device is subjected to abnormal conditions, this software must limit the duration and number
of activation cycles.
Table 7 . VCC - output diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
F
Forward on voltage - I
Doc ID 10861 Rev 4 9/27
= 1.2 A; Tj = 150°C — — 0.6 V
OUT
VNQ830P-E Electrical specifications
Table 8. Switching (V
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
Turn-on delay time
Turn-off delay time
= 13V; Tj = 25°C)
CC
RL = 6.5Ω from VIN rising
edge to V
(see Figure 5)
RL = 6.5 Ω from VIN falling
edge to V
(see Figure 5)
OUT
OUT
= 1.3 V
= 11.7 V
—30—µs
—30—µs
dV
/dt
OUT
dV
OUT
Table 9. Logic inputs
Turn-on voltage slope
(on)
/dt
Turn-off voltage slope
(off)
RL = 6.5 Ω from V
to V
OUT
= 10.4 V
(see Figure 5)
RL = 6.5 Ω from V
11.7 V to V
OUT
(see Figure 5)
OUT
OUT
= 1.3 V
= 1.3 V
=
—
—
See
Figure 10
See
Figure 12
—V/µs
—V/µs
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
I
IL
V
IH
I
IH
V
I(hyst)
V
ICL
Table 10. Status pin
Input low level 1.25 V
Low level input current V
= 1.25 V 1 µA
IN
Input high level 3.25 V
High level input current V
= 3.25 V 10 µA
IN
Input hysteresis voltage 0.5 V
I
= 1 mA 6 6.8 8 V
Input clamp voltage
IN
I
= -1 mA -0.7 V
IN
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
STAT
I
LSTAT
C
STAT
V
SCL
Status low output voltage I
Status leakage current
Status pin input capacitance
Status clamp voltage
Doc ID 10861 Rev 4 10/27
= 1.6 mA 0.5 V
STAT
Normal operation;
= 5 V
V
STAT
Normal operation;
= 5 V
V
STAT
I
= 1 mA 6 6.8 8 V
STAT
= - 1 mA -0.7 V
I
STAT
10 µA
100 pF
VNQ830P-E Electrical specifications
Table 11. Open-load detection
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
t
DOL(on)
V
t
DOL(off)
Open-load on-state detection
OL
threshold
Open-load on-state detection
delay
Open-load off-state voltage
OL
detection threshold
Open-load detection delay at
turn-off
Figure 4. Status timings
OPEN-LOAD STATUS TIMING (with external pull-up)
V
> V
OUT
OL
V
INn
V
STATn
t
DOL(off)
= 5 V 50 100 200 mA
V
IN
= 0 A 200 µs
I
OUT
V
= 0 V 1.5 2.5 3.5 V
IN
I
OUT
t
DOL(on)
< I
OL
V
V
OVERTEMP STATUS TIMING
Tj > T
INn
STATn
t
SDL
TSD
1000 µs
t
SDL
Figure 5. Switching characteristics
V
OUTn
80%
dV
/dt
OUT
(on)
V
INn
t
d(on)
10%
t
d(off)
90%
dV
OUT
/dt
(off)
t
t
Doc ID 10861 Rev 4 11/27
VNQ830P-E Electrical specifications
Table 12. Truth table
Conditions Input Output Status
Normal operation
L
H
L
Current limitation
H
H
Overtemperature
Undervoltage
Overvoltage
Output voltage > V
Output current < I
Table 13. Electrical transient requirements
OL
OL
L
H
L
H
L
H
L
H
L
H
ISO T/R
Test level
L
H
L
X
X
(T
(T
< T
j
> T
j
L
L
L
L
L
L
H
H
L
H
TSD
TSD
H
H
H
) H
) L
H
L
X
X
H
H
L
H
H
L
7637/1
test pulse
1- 25V
2+ 25V
3a - 25 V
3b + 25 V
4- 4V
5 + 26.5 V
1. All functions of the device are performed as designed after exposure to disturbance.
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to
proper operation without replacing the device.
I II III IV Delays and impedance
(1)
(1)
(1)
(1)
(1)
(1)
- 50 V
+ 50 V
- 50 V
+ 50 V
- 5 V
+ 46.5 V
(1)
(1)
(1)
(1)
(1)
(2)
- 75 V
+ 75 V
- 100 V
+ 75 V
- 6 V
+ 66.5 V
(1)
(1)
(1)
(1)
(1)
(2)
- 100 V
+ 100 V
- 150 V
+ 100 V
- 7 V
+ 86.5 V
(1)
(1)
(1)
(1)
(1)
(2)
2ms, 10Ω
0.2 ms, 10 Ω
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
Doc ID 10861 Rev 4 12/27
VNQ830P-E Electrical specifications
Figure 6. Waveforms
NORMAL OPERATION
INPUT
n
LOAD VOLTAGE
STATUS
V
INPUT
n
CC
n
LOAD VOLTAGE
STATUS
V
CC
INPUT
n
LOAD VOLTAGE
STATUS
n
n
UNDERVOLTAGE
V
USDhyst
V
USD
n
undefined
OVERVOLTAGE
n
VCC<V
OV
V
> V
CC
OV
INPUT
n
LOAD VOLTAGE
STATUS
INPUT
n
n
LOAD VOLTAGE
STATUS
T
INPUT
n
j
n
LOAD CURRENT
STATUS
n
OPEN-LOAD with external pull-up
V
> V
n
V
OL
OUT
OL
OPEN-LOAD without external pull-up
n
T
TSD
T
R
n
OVERTEMPERATURE
Doc ID 10861 Rev 4 13/27
VNQ830P-E Electrical specifications
2.4 Electrical characteristics curves
Figure 7. Off-state output current Figure 8. High level input current
IL(off1) (uA)
2.5
2.25
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
-50 -25 0 25 50 75 100 125 150 175
Off state
Vcc=36V
Vin=Vout=0V
Tc (°C)
Iih (uA)
5
4.5
Vin=3.25V
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Figure 9. Input clamp voltage Figure 10. Turn-on voltage slope
Vicl (V)
8
7.8
Iin=1mA
7.6
7.4
7.2
7
6.8
6.6
6.4
6.2
6
-50 -25 0 25 50 75 1 00 125 150 175
Tc (°C)
dVout/dt(on) (V/ms)
800
700
600
500
400
300
200
100
Vcc=13V
Rl=6.5Ohm
0
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
Figure 11. Overvoltage shutdown Figure 12. Turn-off voltage slope
Vov (V)
50
48
46
44
42
40
38
36
34
32
30
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Doc ID 10861 Rev 4 14/27
dVout/dt(off) (V/ms)
600
550
500
450
400
350
300
250
200
Vcc=13V
Rl=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
VNQ830P-E Electrical specifications
Figure 13. I
vs T
LIM
Ilim (A)
20
18
16
14
12
10
8
6
4
2
0
-50 -25 0 25 50 75 100 125 150 175
case
Vcc=13V
Tc (°C)
Figure 14. On-state resistance vs V
Ron (mOhm)
120
110
100
90
80
70
60
50
40
30
20
10
0
5 10152025303540
Tc=150°C
Tc=25°C
Tc= - 40°C
Iout=2A
Vcc (V)
Figure 15. Input high level Figure 16. Input hysteresis voltage
Vih (V)
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
-50 -25 0 25 50 75 100 125 15 0 175
Tc (°C)
Vhyst (V)
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50 -25 0 25 50 75 100 125 15 0 175
Tc (°C)
CC
Figure 17. On-state resistance vs Tcase Figure 18. Input low level
Ron (mOhm)
160
140
120
100
80
60
40
20
0
-50 -25 0 2 5 50 75 100 125 150 175
Iout=2A
Vcc=8V; 13V & 36V
Tc (°C)
Doc ID 10861 Rev 4 15/27
Vil (V)
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
-50 -25 0 25 50 75 100 125 15 0 175
Tc (°C)
VNQ830P-E Electrical specifications
Figure 19. Status leakage current Figure 20. Status low output voltage
Ilstat (uA)
0.05
0.04
Vstat=5V
0.03
0.02
0.01
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Vstat (V)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Istat=1.6mA
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Figure 21. Status clamp voltage Figure 22. Open-load on-state detection
threshold
Vscl (V)
8
7.8
Istat=1mA
7.6
7.4
7.2
7
6.8
6.6
6.4
6.2
6
-50 -25 0 25 50 75 100 125 15 0 175
Tc (°C)
Iol (mA)
150
140
130
120
110
100
90
80
70
60
50
Vcc=13V
Vin=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Figure 23. Open-load off-state voltage
detection threshold
Vol (V)
5
4.5
3.5
2.5
1.5
0.5
Vin=0V
4
3
2
1
0
-50 -25 0 25 50 75 100 125 15 0 175
Tc (°C)
Doc ID 10861 Rev 4 16/27
VNQ830P-E Application information
3 Application information
Figure 24. Application schematic
+5V
+5V
μ
R
C
+5V
V
R
prot
R
prot
prot
R
prot
STATUS1
INPUT1
STATUS2
INPUT2
CC1,2
V
CC3,4
OUTPUT1
D
ld
GND3,4
D
OUTPUT2
OUTPUT3
OUTPUT4
GND
R
prot
R
prot
R
prot
R
prot
+5V
+5V
STATUS3
INPUT3
STATUS4
INPUT4
GND1,2
V
GND
R
GND
Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2.
3.1 GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1 Solution 1: a resistor in the ground line (R
This can be used with any type of load.
The following show how to dimension the R
1. R
2. R
≤ 600 mV / 2 (I
GND
≥ ( - VCC) / ( - I
GND
S(on)max
GND
)
)
Doc ID 10861 Rev 4 17/27
GND
resistor:
GND
only)
VNQ830P-E Application information
where - I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power dissipation in R
P
= ( - VCC)2/ R
D
GND
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
Please note that, if the microprocessor ground is not shared by the device ground, then the
R
produces a shift (I
GND
S(on)max
values. This shift varies depending on how many devices are ON in the case of several highside drivers sharing the same R
If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.
3.1.2 Solution 2: a diode (D
A resistor (R
inductive load. This small signal diode can be safely shared amongst several different HSD.
Also in this case, the presence of the ground network produces a shift (~600mV) in the input
threshold and the status output values if the microprocessor ground is not common with the
device ground. This shift not varies if more than one HSD shares the same diode/resistor
network. Series resistor in INPUT and STATUS lines are also required to prevent that,
during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest
configuration for unused INPUT and STATUS pin is to leave them unconnected.
= 1 kΩ) should be inserted in parallel to D
GND
(when V
GND
< 0 during reverse battery situations) is:
CC
* R
GND
) in the input thresholds and the status output
GND
.
) in the ground line
S(on)max
becomes the sum of the
if the device is driving an
GND
3.2 Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V
maximum DC rating. The same applies if the device is subject to transients on the VCC
CC
line that are greater than those shown in Ta bl e 1 3 .
3.3 MCU I/O protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (R
the microcontroller I/O pins from latching up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:
- V
CCpeak
/ I
latchup
≤ R
prot
≤ (V
OHμC
- V
IH
- V
GND
) / I
IHmax
) in line to prevent
prot
Doc ID 10861 Rev 4 18/27
VNQ830P-E Application information
Example
For the following conditions:
V
CCpeak
I
latchup
V
OHμC
5kΩ ≤ R
= - 100 V
≥ 20 mA
≥ 4.5 V
≤ 65 kΩ.
prot
Recommended values are:
R
= 10 kΩ
prot
3.4 Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (V
microprocessor.
The external resistor has to be selected according to the following requirements:
1. No false open load indication when load is connected: in this case we have to avoid
V
V
OUT
to be higher than V
OUT
= (V
/ (RL + RPU))RL < V
PU
; this results in the following condition:
Olmin
Olmin.
2. No misdetection when load is disconnected: in this case the V
V
R
< (V
PU
Because I
up resistor R
; this results in the following condition:
OLmax
PU
s(OFF)
- V
PU
OLmax
) / I
L(off2)
.
may significantly increase if V
should be connected to a supply that is switched OFF when the module is in
standby.
) like the +5V line used to supply the
PU
has to be higher than
OUT
is pulled high (up to several mA), the pull-
out
Figure 25. Open-load detection in off-state
V
CC
INPUT
STATUS
DRIVER
+
LOGIC
+
-
VOL
GROUND
Doc ID 10861 Rev 4 19/27
V batt. VPU
I
L(off2)
OUT
R
PU
R
R
L
VNQ830P-E Application information
3.5 Maximum demagnetization energy (V
Figure 26. Maximum turn-off current versus load inductance
LMAX (A)
I
100
10
1
0.1 1 10 100
L(mH)
= 13.5 V)
CC
A
B
C
A = single pulse at T
Jstart
B= repetitive pulse at T
C= repetitive pulse at T
VIN, I
L
Demagnetization
Note: Values are generated with R
In case of repetitive pulses, T
must not exceed the temperature specified above for curves B and C.
= 150ºC
= 100ºC
Jstart
= 125ºC
Jstart
Demagnetization
= 0 Ω.
L
(at beginning of each demagnetization) of every pulse
jstart
Demagnetization
t
Doc ID 10861 Rev 4 20/27
VNQ830P-E Package and PCB thermal data
4 Package and PCB thermal data
4.1 SO-28 thermal data
Figure 27. SO-28 PC board
Note: Layout condition of R
thickness = 2 mm, Cu thickness = 35 µm, Copper areas: 0.5 cm
Table 14. Thermal calculation according to the PCB heatsink area
Chip 1 Chip 2 T
ON OFF R
OFF ON R
ON ON
ON ON
R
= thermal resistance junction to ambient with one chip ON
thA
R
= thermal resistance junction to ambient with both chips ON and P
thB
R
= mutual thermal resistance
thC
thA
thC
R
thB
T
amb
(R
P
dchip2
and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB
thA
th
x P
x P
x (P
x P
+ T
dchip1
dchip2
dchip1
dchip1
amb
jchip1
+ T
+ T
+ P
) + R
amb
amb
dchip2
thC
x
) +
R
thC
R
thA
R
thB
T
amb
(R
P
dchip1
thA
x P
x P
x (P
x P
dchip1
dchip2
dchip1
dchip2
+ T
amb
T
jchip2
+ T
+ T
2
, 3 cm2, 6 cm2).
amb
amb
+ P
dchip2
) + R
thC
x
) +
dchip1
P
dchip1
P
dchip1
= P
Note
= P
≠ P
dchip2
dchip2
dchip2
Doc ID 10861 Rev 4 21/27
VNQ830P-E Package and PCB thermal data
Figure 28. R
RTHj_am b
(°C/W)
70
60
50
40
30
20
10
01234567
vs PCB copper area in open box free air condition
thj-amb
PCB Cu heatsink area (cm ^2)/island
R
thA
R
thB
R
thC
Figure 29. SO-28 thermal impedance junction ambient single pulse
ZTH (°C/W)
1000
100
10
1
0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
Footprint
6 cm
2
Doc ID 10861 Rev 4 22/27
VNQ830P-E Package and PCB thermal data
Equation 1: pulse calculation formula
Z
where
THδ
RTHδ Z
δ tpT⁄=
THtp
1 δ–()+⋅=
Figure 30. Thermal fitting model of a quad channel HSD in SO-28
Tj_1
Pd1
Tj_2
Pd2
Tj_3
Pd3
Tj_4
Pd4
C1
C13 C14
R13
C7
C15 C16
R15
R14
R16
C3 C4
R3R1 R6R5R2
R17
C8
R8
C9
R9R7
R4
R18
C10
R10
C5 C6C2
C11 C12
R12R11
Table 15. Thermal parameters
Area / island (cm2) Footprint 6
R1 = R7 = R13 = R15 (°C/W) 0.15
R2 = R8 = R14 = R16 (°C/W) 0.7
R3 = R9 (°C/W) 1.8
R4 = R10 (°C/W) 10
R5 = R11 (°C/W) 15
R6 = R12 (°C/W) 30 13
C1 = C7 = C13 = C15 (W.s/°C) 0.0005
C2 = C8 = C14 = C16 (W.s/°C) 3E-03
C3 = C9 (W.s/°C) 1.50E-02
C4 = C10 (W.s/°C) 0.15
C5 = C11 (W.s/°C) 1.5
C6 = C12 (W.s/°C) 5 8
R17 = R18 (°C/W) 150
T_amb
Doc ID 10861 Rev 4 23/27
VNQ830P-E Package and packing information
5 Package and packing information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 31. SO-28 package dimensions
Table 16. SO-28 mechanical data
Symbol
Min. Typ. Max.
A 2.65
a1 0.10 0.30
b 0.35 0.49
b1 0.23 0.32
C0.50
c1 45° (typ.)
D 17.7 18.1
E 10.00 10.65
e1.27
e3 16.51
F 7.40 7.60
L 0.40 1.27
S 8° (max.)
Millimeters
Doc ID 10861 Rev 4 24/27
VNQ830P-E Package and packing information
5.2 SO-28 packing information
Figure 32. SO-28 tube shipment (no suffix)
Base Q.ty 28
Bulk Q.ty 700
Tube length (± 0.5) 532
A 3.5
C
B
A
Figure 33. SO-28 tape and reel shipment (suffix “TR”)
B 13.8
C (± 0.1) 0.6
All dimensions are in mm.
Reel dimensions
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2
All dimensions are in mm.
Top
cover
tape
End
500mm min
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4
Empty components pockets
saled with cover tape.
User direction of feed
Start
No componentsNo components Components
500mm min
Doc ID 10861 Rev 4 25/27
VNQ830P-E Revision history
6 Revision history
Replaced
Table 17. Document revision history
Date Revision Changes
03-May-2006 1 Initial release.
Document reformatted and restructured.
18-Dec-2008 2
03-May-2010 3
07-Feb-2011 4
Added contents, list of tables and figures.
Added ECOPACK® packages information.
Changed Features list.
Replaced VND830P-E to VND830-E.
Table 3: Absolute maximum ratings
–E
Updated Figure 5: Switching characteristics
Updated Table 15: Thermal parameters
: updated value
MAX
Doc ID 10861 Rev 4 26/27
VNQ830P-E
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Doc ID 10861 Rev 4 27/27
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