ST VNQ830M-E User Manual

VNQ830M-E

QUAD CHANNEL HIGH SIDE DRIVER

Table 1. General Features

Type R

VNQ830M-E 60m

(*) Per each channel

CMOS COMPATIBLE INPUTS

■

■ OPEN DRAIN STATUS OUTPUTS

■ ON STATE OP EN L OAD DET ECTIO N

■ OFF STATE OPEN LOAD DETECTION

■ SHOR T E D L O A D PROTE C TION

■ UNDERVOLTAGE AND OVERVOLTAGE

DS(on)

Ω (*) 6A (*) 36V

I

out

V

CC

SHUTDOWN

■ LOSS OF GROUND PROTECTION

■ VERY LOW STAND-BY CURRENT

■ REVERSE BATTERY PROTECTION (**)

■ IN COMPLIANCE WITH THE 2002/95/EC

EUROPEAN DIRECT IVE

DESCRIPTION

The VNQ830M-E is a quad HSD formed by assembling two VND830M-E chips in the same SO-28 package. The VND830M-E is a monolithic device made by using| STMicroelectronics VIPower M0-3 Technology. The VNQ830M-E is intended for driving any type of multiple loads with one side connected to ground.

Activ e V

pin voltage clamp pro tects the device

CC

against low energy spikes (see ISO7637 transient compatibility table).

Figure 1. Package

SO-28 (DOUBLE ISLAND)

Active current limitation combined with thermal shutdown and automatic restart protects the device against overload.

The device detects open load condition both in on and off state. The openload t hreshold is aim ed at detecting the 5W/12V standard bulb as an openload fault in the on state. Outp ut shorted to

is detected in the off state. Device

V

CC

automatically turns off in case of ground pin disconnection

Table 2. Order Codes

Package Tube Tape and Reel

SO-28

Note: (**) See appli c a t i on sche m atic at pa ge 10

VNQ830M-E VNQ830MTR-E

Rev. 1

1/21October 2004

VNQ830M-E

Figure 2. Block Diagram

V

cc

CLAMP

OVERVOLTAGE

UNDERVOLTAGE

V

CC1,2

GND1,2

INPUT1

STATUS1

INPUT2

STATUS2

GND3,4

INPUT3

STATUS3

INPUT4

STATUS4

OVERTEMP. 1

OVERTEMP. 2

V

cc

CLAMP

OVERTEMP. 3

LOGIC

CLAM P 1

DRIVER 1

CURRENT LIMITER 1

OPENLOAD ON 1

OPENLOAD OFF 1

OVERVOLTAGE

UNDERVOLTAGE

CLAMP 3

DRIVER 3

CURRENT LIMITE R 3

OPENLOAD ON 3

OPENLOAD OFF 3

CLAMP 2

DRIVER 2

CURRENT LIMITER 2

OPENLOAD ON 2

OPENLOAD OFF 2

CLAMP 4

DRIVER 4

CURRENT LIMITER 4

OPENLOAD ON 4

OUTPUT1

OUTPUT2

V

CC3,4

OUTPUT3

OUTPUT4

2/21

OVERTEMP. 4

OPENLOAD OFF 4

VNQ830M-E

Table 3. Absolute Maximum Ratings

Symbol Parameter Value Unit

V

- V

- I I

OUT

- I

I

STAT

V

P

E

T

CC

GND

OUT

I

IN

ESD

tot

MAX

T

j

stg

DC Supply Voltage 41 V Reverse DC Supply Voltage - 0.3 V DC Reverse Ground Pin Current - 200 mA DC Output Current Internally Limited A Reverse DC Output Current - 6 A DC Input Current +/- 10 mA DC Status Current +/- 10 mA Electrostatic Discharge (Human Body Model:

R=1.5KΩ; C=100pF)

- INPUT

- STATUS

- OUTPUT

- V

CC

Power Dissipation T

=25°C 6.25 W

pins

4000 4000 5000 5000

Maximum Switching Energy (L=1mH; R

I

=10.5A)

L

=0Ω; V

L

=13.5V; T

bat

jstart

=150ºC;

77 mJ

Junction Operating Temperature Internally Limited °C Storage Temperature - 55 to 150 °C

V V V V

Figure 3. Con fig urat i on Dia g ra m (Top View) & Sugg est ed C o nnections for Unu sed and N.C. Pins

VCC1,2 GND 1,2 INPUT1 STA TUS1 STA TUS2

INPUT2

1,2

V

CC

VCC3,4 GND 3,4 INPUT3

STATUS3 STA TUS4 INPUT4

3,4

V

CC

1

14

Connection / Pin Status N.C. Output Input

Floating X X X X To Ground X Through 10KΩ resistor

28

VCC1,2 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT2 OUTPUT2

OUTPUT2

OUTPUT3 OUTPUT3 OUTPUT3

OUTPUT4

V

15

3,4

CC

3/21

VNQ830M-E

Figure 4. Current and Voltage Conventions

V

CC3,4

V

IN1

(*) VFn = V

V

STAT1

CCn

V

- V

I

S3,4

I

IN1

I

STAT1

I

IN2

I

IN2

V

STAT2

V

IN3

V

STAT3

during reverse battery condition

OUTn

STAT2

I

IN3

I

STAT3

I

IN4

I

STAT4

V

IN4

V

STAT4

INPUT1 STATUS1

INPUT2 STATUS2

INPUT3

STATUS3

INPUT4 STATUS4

GND

V

CC3,4

3,4

I

GND3,4

V

CC1,2

OUTPUT1

OUTPUT2

OUTPUT3

OUTPUT4

GND

1,2

I

GND1,2

I

OUT1

I

OUT2

I

OUT3

I

OUT4

V

OUT4

V

F1

OUT3

I

S1,2

V

OUT1

V

CC1,2

(*)

V

OUT2

Table 4. Thermal Data (Per islan d )

Symbol Parameter Value Unit

R

thj-lead

R

thj-amb

R

thj-amb

Thermal Resistance Junction-lead per chip 20 °C/W

Thermal Resistance Junction-ambient 60 Thermal Resistance Junction-ambient (two chips ON) 46

(1) (1)

44 31

(2) (2)

°C/W °C/W

Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick) connected to all VCC pins. Horizontal

mounting an d no arti ficial ai r flow

Note: 2. When mounted on a standard single-sided FR-4 board with 6cm

2

of Cu (at least 3 5µm thick) connected to all VCC pins. Hori zontal

mounting an d no arti fi cial ai r flow

4/21

VNQ830M-E

ELECTRICAL CHARACTERISTICS

(8V<V

(Per each channel)

Table 5. Po we r Ou t put

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

Note: (**) Per island

<36V; -40°C< Tj <150°C, unless otherwise specified)

CC

(**) Operating Supply Voltage 5.5 13 36 V

CC

(**) Undervoltage Shut-down 3 4 5.5 V

USD

(**) Overvoltage Shut- down 36 V

OV

I

R

on

(**) Supply Current

I

S

I

L(off1)

I

L(off2)

I

L(off3)

I

L(off4)

On State Resistance

Off State Output Current VIN=V Off State Output Current VIN=0V; V Off State Output Current VIN=V Off State Output Current VIN=V

=2A; Tj=25°C

OUT

I

=2A; VCC>8V

OUT

Off State; V Off State; V

=13V; VIN=V

CC

=13V; VIN=V

CC

OUT OUT

=25°C On State; VCC=13V; VIN=5V; I

=0V 0 50 µA

OUT

=3.5V -75 0 µA

OUT

=0V; VCC=13V; Tj =125°C 5 µA

OUT

=0V; VCC=13V; Tj =25°C 3 µA

OUT

=0V =0V; Tj

=0A

OUT

12

5

60

120

40

25

7

mΩ mΩ

µA

mA

Table 6. Protection (Per each channel) (See note 1)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

T

TSD

T

hyst

t

SDL

I

lim

V

demag

Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be

Table 7. V

Symbol Parameter Test Conditions Min Typ Max Unit

V

Shut-down Temperature 150 175 200 °C Reset Temperature 135 °C

R

Thermal Hysteresis 7 15 °C Status Delay in Overload

Conditions

Current limitation

Turn-off Output Clamp Voltage

used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the durat i on and number of activation cycl es

- Output Diode (Per each channel)

CC

Forward on Voltage -I

F

T

j>TTSD

20 µs

6 10.5 15

5.5V<V

I

OUT

<36V

CC

=2A; L=6mH VCC-41 VCC-48 VCC-55 V

=1.3A; Tj=150°C 0.6 V

15

A A

5/21

VNQ830M-E

ELECTRICAL CHARACTERISTICS (continued) Table 8. Status Pin (Per each channel)

Symbol Parameter Test Conditions Min Typ Max Unit

V

I

LSTAT

C

V

STAT

SCL

Status Low Output Voltage I

=1.6mA 0.5 V

STAT

Status Leakage Current Normal Operation; V Status Pin Input

Capacitance Status Clamp Voltage

Normal Operation; V I

=1mA

STAT

=-1mA

I

STAT

=5V 10 µA

STAT

=5V 100 pF

STAT

6 6.8

-0.7

8V

V

Table 9. Switching (Per each channel) (V

CC

=13V)

Symbol Parameter Test Conditions Min Typ Max Unit

=6.5Ω from VIN rising edge to

R

L

V

=1.3V

OUT

=6.5Ω from VIN falling edge to

R

L

V

=11.7V

OUT

=6.5Ω from V

R

L

V

=10.4V

OUT

=6.5Ω from V

R

L

V

=1.3V

OUT

(Per each channel)

=1.3V to

=11.7V to

30 µs

See

relative

diagram

See

relative

diagram

dV

t

OUT

d(on)

d(off)

Turn-on Delay Time

Turn-off Delay Time

/dt

Turn-on Voltage Slope

(on)

/dt

Turn-off Voltage Slope

(off)

Table 10. Openload Detection

Symbol Parameter Test Conditions Min Typ Max Unit

I

OL

t

DOL(on)

Openload ON State Detection Threshold Openload ON State Detection Delay

=5V 0.6 0.9 1.2 A

V

IN

I

=0A 200 µs

OUT

Openload OFF State

V

OL

Voltage Detection

V

=0V 1.5 2.5 3.5 V

IN

Threshold Openload Detection Delay

t

DOL(off)

at Turn Off

1000 µs

V/µs

Table 11. Logic Input

(Per each channel)

Symbol Parameter Test Conditions Min Typ Max Unit

V

IL

I

IL

V

IH

I

IH

I(hyst)

ICL

Input Low Level 1.25 V Low Level Input Current VIN=1.25V 1 µA Input High Level 3.25 V High Level Input Current VIN=3.25V 10 µA Input Hysteresis Voltage 0.5 V

Input Clamp Voltage

I

IN

I

IN

=1mA =-1mA

6 6.8

-0.7

8V

6/21

V

Tabl e 12. Truth Tabl e

CONDITIONS INPUT OUTPUT SENSE

VNQ830M-E

Normal Operation

L

H

L

Current Limitation

H H

Overtemperature

Undervoltage

Overvoltage

Output Voltage > V

Output Current < I

OL

L

H

L

H

L

H

L

H

L

H

Figure 5.

OPEN LOAD STATUS TIMING (with external pull-up)

V

> V

OUT

OL

V

INn

I

OUT

< I

L

H

L X X

(T

< T

j

> T

j

L

L H

H

L H

TSD

H H

H

) H

) L

H

L

X X

H H

L

H H

L

OVER TEMP STATUS TIMING

OL

V

INn

Tj > T

TSD

V

STA Tn

t

DOL(off)

t

DOL(on)

V

STATn

t

SDL

t

SDL

7/21

VNQ830M-E

Figure 6. Switching time Waveforms

V

OUTn

80%

/dt

dV

OUT

(on)

V

INn

t

d(on)

10%

t

d(off)

90%

dV

OUT

/dt

(off)

t

Table 13. Electrical Transient Requirements On V

ISO T/R 7637/1

Test Pulse

1 -25 V -50 V -75 V -100 V 2 ms 10 Ω

2 +25 V +50 V +75 V +100 V 0.2 ms 10 Ω 3a -25 V -50 V -100 V -150 V 0.1 µs 50 Ω 3b +25 V +50 V +75 V +100 V 0.1 µs 50 Ω

4 -4 V -5 V -6 V -7 V 100 ms, 0.01

5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2

ISO T/R 7637/1

Test Pulse

1CCCC

2CCCC 3aCCCC 3bCCCC

4CCCC

5C E E E

I II III IV Delays and

TEST LEVELS RESULTS

I II III IV

CC

TEST LEVELS

t

Impedance

Ω

CLASS CONTENTS

C All functions of the device are performed as designed after exposure to disturbance.

E One or more functions of the device is not performed as designed after exposure and cannot be

returned to proper operation without replacing the device.

8/21

Figure 7. Waveforms

INPUT

n

LOAD VOLTAGE STATUS

V

CC

INPUT

n

LOAD VOLTAGE STATUS

V

CC

INPUT

n

LOAD VOLTAGE STATUS

VNQ830M-E

NORMAL OPERATION

n

UNDERVOLT AGE

V

USDhyst

V

USD

n

undefined

OVERVOLTAGE

VCC<V

OV

n

VCC>V

OV

INPUT

n

LOAD VOLTAGE STATUS

INPUT

n

LOAD VOLTAGE STATUS

T

INPUT

n

j

n

LOAD CURRENT

STATUS

n

OPEN LOAD with external pull-up

n

OPEN LOAD without external pull-up

V

n

T

TSD

T

R

n

V

OL

OVERTEMPERATURE

OUT>VOL

9/21

VNQ830M-E

Figure 8. Application Schematic

+5V

µ

R

prot

R

C

+5V

prot

STATUS1

INP UT1

STA TU S2

INPUT2

V

CC1,2

V

CC3,4

OUTPUT1

D

ld

R

prot

R

prot

R

prot

R

prot

+5V

STATUS 3

INP UT3

STATUS4

INP UT4

GND1,2

V

GND

Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2.

GND PROTECTION NETWORK AGAINST REVERSE BATTERY

Solution 1: Re sistor in th e ground line (R can be used with any type of load.

The following is an indication on how to d imension the

resistor.

R

GND

1) R

2) R

where -I be found in the absolute maxim um rating section of the

≤ 600mV / 2(I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can

GND

S(on)max

)

).

device’s datasheet. Power Dissipation in R

battery situations) is:

(when VCC<0: during rever se

GND

only). This

GND

P

D

This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) wh ere I sum of the maximum on-stat e currents of the differe nt devices.

Please note that if the microprocessor ground is not common with the device ground then the R produce a shift (I and the status output values. This shift will vary depending on how many dev ices are ON in the case of several high side drivers sharing the same R

If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2.

GND3,4

R

GND

= (-VCC)2/R

OUTPUT2

OUTPUT3

OUTPUT4

D

GND

S(on)max

* R

S(on)max

) in the input thresho lds

GND

becomes t he

GND

.

will

10/21

VNQ830M-E

Solution 2: A diode (D A resistor (R

if the device will be driving an inductive load.

D

GND

=1kΩ) should be inserted in parallel to

GND

) in the ground line.

GND

This small signal diode can be safely shared amongst several different HS D. Also in this cas e, the presenc e of the ground netwo rk will produce a shif t (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.

Series resistor in INPUT and STATUS lines are also required to p reven t tha t, d uring batt ery voltag e tr ansie nt, the current exceeds the Absolute Maximum Rating.

Safest configu ration for unu sed INPU T and S TAT US p in is to leave them unconnected.

LOAD DUMP PROTECTIO N

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the V shown in the ISO T/R 7637/1 table.

.

µC I/Os PROTECTION:

If a ground protection network is used and negative transients are present on the V be pulled negative. ST suggests to insert a resistor (R in line to prevent the µC I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os.

-V

CCpeak/Ilatchup

Calculation example:

line that are greater than the ones

CC

line, the control pins will

CC

≤ R

prot

≤ (V

OHµC-VIH-VGND

) / I

prot

IHmax

CCpeak

prot

= - 100V and I

≤ 65kΩ.

For V 5kΩ ≤ R Recommended R

value is 10kΩ.

prot

latchup

≥ 20mA; V

OPEN LOAD DETECTION IN OFF STATE

Off state open load detection requires an external pull-up resistor (R positive supply voltage (V supply the microprocessor. The external res istor has to be s electe d ac cordin g to t he following requirements:

1) no false o pen load indic ation when lo ad is con necte d: in this case we have to avoid V

V

Olmin

V

OUT

2) no misdetection when load is disconnected: in this case the V results in the fol lowing condition R I

L(off2)

Because I

)

pulled high (up to several mA), the pull-u p resistor R should be connected to a supply that is switched OFF

when the module is in standby. The values of V

the Electrical Characteristics section.

) connected between OUTPUT pin and a

PU

) like the +5V line used to

PU

to be high er than

OUT

; this results in the following condition

=(VPU/(RL+RPU))RL<V

has to be higher than V

OUT

Olmin.

PU

<(V

.

may significantly increase if V

s(OFF)

OLmin

, V

OLmax

and I

are available in

L(off2)

≥ 4.5V

OHµC

OLmax

PU–VOLmax

; this

is

out

)/

PU

Figure 9. Open Load detection in off state

INPUT

STATUS

DRIVER

+

LOGIC

V batt. VPU

V

CC

OUT

+

R

VOL

GROUND

IL(off2)

R

PU

RL

11/21

VNQ830M-E

Figure 10. Off State Output Current

IL(o ff 1 ) (uA)

2.5

2.25

2

1.75

1.5

1.25

1

0.75

0.5

0.25 0

-50 -25 0 25 50 75 100 125 150 175

Off state Vcc=36V

Vin=Vout=0V

Tc (°C)

Figure 11. Input Clamp Voltage

Vicl (V)

8

7.8

7.6

7.4

7.2

7

6.8

6.6

6.4

6.2

6

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 13. High Level Input Current

Iih (uA)

5

4.5

3.5

2.5

1.5

0.5

Vin=3.25V

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 14. Status Leakage Current

Ilstat (uA)

0.05

0.04

Vstat= 5 V

0.03

0.02

0.01

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 12. S t at us Low Output Volta ge

Vstat (V)

0.8

0.7

Istat=1.6mA

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

12/21

Figure 15. Status Clamp Voltage

Vscl (V)

8

7.8

7.6

7.4

7.2

6.8

6.6

6.4

6.2

Istat=1mA

7

6

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

VNQ830M-E

Figure 16. Overvoltage Shutdown

Vov (V)

50

48

46

44

42

40

38

36

34

32 30

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 17. Turn-on Voltage Slope

dVout/dt( on ) (V /ms )

800

700

600

Vcc=13V

Rl=6.5Ohm

Figure 19. I

LIM

Vs T

case

Ilim (A)

20

18

16

14

12

10

8

6

4

2 0

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 20. Turn-off Voltage Slope

dVout/dt(off) (V/ms)

600

550

500

Ri=6.5Ohm

500

400

300

200

100

0

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Figure 18. On State Resistance Vs T

Ron (mOhm)

160

140

120

100

80

60

40

20

0

-50 -25 0 25 50 75 100 125 150 175

Iout=2A

Vcc=8V; 13V & 36V

Tc (°C)

case

450

400

350

300

250

200

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 21. On State Resistance Vs V

Ron (mOhm)

120 110 100

90 80 70 60 50 40 30 20 10

0

5 10152025303540

Vcc (V)

Tc=150°C

Tc=25°C

Tc= - 40°C

Iout=5A

CC

13/21

VNQ830M-E

)

Figure 22. Input High Level

Vih (V )

3.6

3.4

3.2

3

2.8

2.6

2.4

2.2

2

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 23. Openload On State Detection

Threshol d

Iol (mA)

1250

1200

1150

1100

1050

1000

950

900

850

800 750

Vcc=13V

Vin=5V

-50 - 25 0 25 50 75 100 125 15 0 175

Tc (°C

Figure 25. Input Low Level

Vil (V)

2.6

2.4

2.2

2

1.8

1.6

1.4

1.2

1

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 26. Openload Off State Detection

Threshold

Vol (V )

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5 0

Vin=0V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C

Figure 24. Input Hysteresis Voltage

Vhyst (V)

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

14/21

Figure 27. Maximum turn off curren t vers us load indu ctan ce

LMAX (A)

I

100

10

VNQ830M-E

A

B

C

1

0.1 1 10 100

A = Single Pulse at T

B= Repetitive pulse at T C= Repetitive Pulse at T

Conditions: VCC=13.5V

VIN, I

L

Jstart

=150ºC

=100ºC

Jstart

=125ºC

Jstart

Demagnetization

L(mH)

Values are generated with R In case of repetitive pulses, T

each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C.

Demagnetization

=0Ω

L

(at beginning of

jstart

Demagnetization

t

15/21

VNQ830M-E

SO-28 Double Island Thermal Data

Figure 28. Double Island PC Board

Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: 0.5cm

2

, 3cm2, 6cm2).

Table 14. Thermal Calculation According To The Pcb Heatsink Area

Chip 1 Chip 2 T

ON OFF R

OFF ON R

ON ON R ON ON (R

R

= Thermal resistance Junctio n to Am bient wit h one

thA

chip ON

= Thermal resistance Jun ction to Ambient with both

R

thB

chips ON and P R

= Mutual thermal resistance

thC

dchip1=Pdchip2

thA thC thB

thA

x P

x (P

x P

dchip1 dchip2

dchip1 dchip1

+ T + T

+ P ) + R

jchip1

amb amb

dchip2

thC

) + T

x P

amb

dchip2

+ T

amb(RthA

R

x P

thC

R

x P

thA

R

x (P

thB

x P

Figure 29. R Open Box Free Air Condition

dchip1 dchip2

dchip1

dchip2

T

jchip2

+ T

amb

+ T

amb

+ P

) + R

thj-amb

RTHj_amb

(°C/W)

70 60 50

dchip2

thC

x P

) + T

dchip1

amb

+ T

P

dchip1=Pdchip2

ambPdchip1≠Pdchip2

Vs. PCB Copper Area In

R

thA

R

thB

Note

16/21

40

R

thC

30 20 10

01234567

PCB Cu heatsink area (cm^2)/island

Figure 30. SO-28 Thermal Impedance Jun ction Ambient Single Pu lse

Zth(°C/W )

100

10

1

0.1

VNQ830M-E

0,5 cm^2/island

3 cm^2/island

6 cm^2/island

One channel ON Two channels ON

on same chip

0.01 1E-04 0.001 0.01 0.1 1 10 100 1000

tim e(s )

Figure 31. Th e rm al fit t in g m od e l of a double channel HSD in SO-28

Tj_1

Pd1

Tj_2

Pd2

Tj_3

Pd3

Tj_4

Pd4

C1

C13 C14

R13

C7

C15 C16

R15

R14

R16

C3 C4

R3R1 R6R5R2

R17

C8

R8

R18

C9

C10

R9R7

T_amb

R4

R10

C5 C6C2

C11 C12

R12R11

Pulse calculation formula

Z

TH

where

R

δ Z

TH

δ

THtp

1 δ–()+⋅=

δ tpT⁄=

Table 15. Thermal Parameter

Area/island (cm2) 0.5 6

R1=R7=R13= R15 (°C/W) 0.05 R2=R8=R14= R16 (°C/W) 0.3 R3=R9 (°C/W) 3.4 R4=R10 (°C/W) 11 R5=R11 (°C/W) 15 R6=R12 (°C/W) 30 13 C1=C7=C13= C15 (W.s/ °C) 0.001 C2=C8=C14= C16 (W.s/ °C) 5.00E-03 C3=C9 (W.s/°C) 1.00E-02 C4=C10 (W.s/°C) 0.2 C5=C11 (W.s/°C) 1.5 C6=C12 (W.s/°C) 5 8 R17=R18 (°C/W) 150

17/21

VNQ830M-E

PACKAGE MECHANICAL

Table 16. SO-28 Mechanical Data

Symbol

A 2.65

a1 0.10 0.30

b 0.35 0.49

b1 0.23 0.32

C 0.50

c1 45° (typ.)

D 17.7 18.1

E 10.00 10.65 e 1.27

e3 16.51

F 7.40 7.60 L 0.40 1.27 S 8° (max.)

Figure 32. SO-28 Package Dimensions

Min Typ Max

millimeters

18/21

Figure 33. SO-28 Tube Shipment (No Suffix)

Base Q.ty 28 Bulk Q.ty 700

C

B

Tube length (± 0.5) 532 A 3.5 B 13.8 C (± 0.1) 0.6

All dimensions are in mm.

A

Figure 34. Tape And Reel Shipment (Suffix “TR”)

VNQ830M-E

REEL DIMENSIONS

Base Q.ty 1000 Bulk Q.ty 1000 A (max) 330 B (min) 1.5 C (± 0.2) 13

F 20.2 G (+ 2 / -0) 16.4 N (min) 60 T (max) 22.4

TAPE DIMENSIONS

According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986

Tape width W 16 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 12 Hole Diameter D (± 0.1/-0) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.05) 7.5 Compartment Depth K (max) 6.5 Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Top

cover

tape

End

500mm m in

Empty compon ents poc ke ts saled with co ve r tape.

User direction of feed

Start

No compon entsNo components Com pon ents

500mm m in

19/21

VNQ830M-E

REVISION HIST ORY

Date Rev ision Description of Change s

Oct. 2004 1 - First Issue

20/21

VNQ830M-E

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implic ation or otherwise und er any patent or patent rights of STMic roelectroni cs. Specifications menti oned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authori zed for use as criti cal components in life suppor t devices or systems without ex press written a pproval of STMi croelectroni cs.

The ST logo i s a registered tr ademark of STMic roelectroni cs .

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21/21

ST VNQ830M-E User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual