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VNQ5027AK-E
Datasheet (ST)
31 pgs459.61 Kb0
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Datasheet VNQ5027AK-E Datasheet (ST)

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Features
VNQ5027AK-E
Quad channel high side driver with analog current sense
for automotive applications
Max supply voltage V
Operating voltage range V
Max on-state resistance (per ch.) R
Current limitation (typ) I
Off-state supply current I
1. Typical value with all loads connected.
■ Output current: 42A
■ Current sense disable
■ Proportional load current sense
■ Undervoltage shut-down
■ Overvoltage clamp
■ Thermal shutdown
■ Current and power limitation
■ Very low standby current
■ Protection against loss of ground and loss of
V
CC
■
Very low electromagnetic susceptibility
■ Optimized electromagnetic emission
■ Reverse battery protection (see Application
CC
CC
ON
LIMH
S
schematic on page 20)
■ In compliance with the 2002/95/EC European
directive
■ Package: ECOPACK
®

Table 1. Device summary

Package
41V
4.5 to 36 V
27 mΩ
42 A
(1)
2 µA
PowerSSO-24
Applications
■ All types of resistive, inductive and capacitive
loads
■ Suitable as LED driver
Description
The VNQ5027AK-E is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table).
This device integrates an analog Current Sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears.
Order codes
Tube Tape and reel
CC pin
PowerSSO-24 VNQ5027AK-E VNQ5027AKTR-E
July 2009 Doc ID 12730 Rev 6 1/31
www.st.com
1
Contents VNQ5027AK-E
Contents
1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20
3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31 Doc ID 12730 Rev 6
VNQ5027AK-E List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Switching (VCC=13V; Tj= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Current Sense (8V<V
Table 9. Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13. Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 14. Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
Doc ID 12730 Rev 6 3/31
List of figures VNQ5027AK-E
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Delay response time between rising edge of output current and rising edge of Current Sense
(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. I
OUT/ISENSE
Figure 8. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. On-state resistance vs T Figure 17. On-state resistance vs V
Figure 18. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 19. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 20. I
LIMH
vs T
Figure 21. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 24. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 25. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
Figure 28. PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 24
Figure 30. PowerSSO-24™ thermal impedance junction ambient single pulse (one channel on). . . . 25
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24™ . . . . . . . . . . . . . . . . . 25
Figure 32. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 33. PowerSSO-24™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 34. PowerSSO-24™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
vs I
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4/31 Doc ID 12730 Rev 6
VNQ5027AK-E Block diagram and pin configuration

1 Block diagram and pin configuration

Figure 1. Block diagram

V
CC
Pwr
LIM
UNDERVOLTAGE
DRIVER 1
OVERTEMP. 1
I
OUT1
K 1
1
PwCLAMP 1
I
1
LIM
V
DSLIM
INPUT2
Control & Protection Equivalent to
1
CURRENT
SENSE2
INPUT3
CURRENT
SENSE3
INPUT4
CURRENT
SENSE4
channel1
Control & Protection Equivalent to channel1
Control & Protection Equivalent to channel1
V
CC
CLAMP
GND
INPUT1
INPUT2
INPUT3
INPUT4
CS_DIS

Table 2. Pin functions

LOGIC
Name Function
V
CC
OUTPUT
GND
INPUT
n
CURRENT
SENSE
n
Battery connection.
Power output.
n
Ground connection. Must be reverse battery protected by an external diode / resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.
Analog current sense pin, delivers a current proportional to the load current.
CS_DIS Active high CMOS compatible pin to disable the current sense pin.
V
V
V
CC
CC
CC
OUTPUT1
CURRENT SENSE1
OUTPUT2
CURRENT SENSE2
OUTPUT3
CURRENT SENSE3
OUTPUT4
CURRENT SENSE4
Doc ID 12730 Rev 6 5/31
Block diagram and pin configuration VNQ5027AK-E

Figure 2. Configuration diagram (top view)

V
GND
INPUT1
CURRENT SENSE1
INPUT2
CURRENT SENSE2
INPUT3
CURRENT SENSE3
INPUT4
CURRENT SENSE4
CS_DIS.
V
CC
CC
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT3
OUTPUT3
OUTPUT3
OUTPUT4
OUTPUT4
OUTPUT4
TA B = V

Table 3. Suggested connections for unused and not connected pins

CC
Connection / pin Current Sense N.C. Output Input CS_DIS
Floating N.R.
To ground
1. Not recommended.
(1)
Through 1 kΩ
resistor
XX X X
XN.R.
Through 10 kΩ
resistor
Through 10 kΩ
resistor
6/31 Doc ID 12730 Rev 6
VNQ5027AK-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I
S
V
CC
I
CSD
V
CSD
I
INn
V
INn
CS_DIS
INPUTn
GND
OUTPUTn
CURRENT S
ENSEn
I
GND
I
SENSEn
V
SENSEn
V
Fn
I
OUTn
V
OUTn
V
CC
Note: V
Fn
= V
- VCC during reverse battery condition.
OUTn

2.1 Absolute maximum ratings

Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in this section for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit
- I
- I
V
-V
I
OUT
DC supply voltage 41 V
CC
Reverse DC supply voltage 0.3 V
CC
DC reverse ground pin current 200 mA
GND
DC output current Internally limited A
Reverse DC output current 24 A
OUT
DC Input current -1 to 10 mA
I
IN
I
CSD
-I
CSENSE
V
CSENSE
E
DC Current Sense disable Input current -1 to 10 mA
DC Reverse CS pin current 200 mA
Current Sense maximum voltage
Maximum switching energy (single pulse)
MAX
(L=0.8 mH; R
=0Ω; V
L
=13.5V; T
bat
jstart
=150ºC; I
OUT
= I
limL
(Typ.))
V
-41
CC
+V
CC
140 mJ
V V
Doc ID 12730 Rev 6 7/31
Electrical specifications VNQ5027AK-E
Table 4. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Electrostatic discharge (human body model: R=1.5KΩ; C=100pF)
4000 2000 4000 5000 5000
V V V V V
V
V
ESD
ESD
T
– Input – Current sense –CS_DIS – Output –V
CC
Charge device model (CDM-AEC-Q100-011) 750 V
Junction operating temperature - 40 to 150 °C
T
j
Storage temperature - 55 to 150 °C
stg

2.2 Thermal data

Table 5. Thermal data

Symbol Parameter Max value Unit
R
thj-case
R
thj-amb
Thermal resistance junction-case (with one channel ON) 1.35 °C/W
Thermal resistance junction-ambient See Figure 29. °C/W
8/31 Doc ID 12730 Rev 6
VNQ5027AK-E Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for 8 V<VCC<36 V, -40 °C< Tj <150 °C, unless otherwise stated.

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
USDhyst
R
V
clamp
I
L(off)
1. PowerMOS leakage included.
2. For each channel.
Operating supply voltage 4.5 13 36 V
CC
Undervoltage shutdown 3.5 4.5 V
USD
Undervoltage shut-down hysteresis
On-state resistance
ON
Clamp voltage IS= 20 mA 41 46 52 V
I
Supply current
S
Off-state output current
Output - VCC diode
V
F
voltage
(2)
I
= 3A; Tj= 25°C
OUT
= 3A; Tj= 150°C
I
OUT
I
= 3A; VCC=5V; Tj= 25°C
OUT
Off-state; V V
IN=VOUT=VSENSE=VCSD
On-state; V I
OUT
VIN=V Tj=25°C
(2)
V
IN=VOUT
CC
CC
=0A
=0V; VCC=13V;
OUT
=0V; VCC=13V;
Tj=125°C
-I
=3A; Tj=150°C 0.7 V
OUT
=13V; Tj=25°C;
=0V
=13V; VIN=5V;
0.5 V
(1)
2
5
8
000.01 3
27 54 37
(1)
14
5
mΩ mΩ mΩ
µA
mA
µA
Table 7. Switching (VCC=13V; Tj= 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
(dV
OUT
(dV
OUT
W
ON
W
OFF
Turn-on delay time RL= 4.3Ω (see Figure 6.)40 µs
Turn-off delay time RL= 4.3Ω (see Figure 6.)40 µs
/dt)onTurn-on voltage slope RL= 4.3Ω
/dt)
Turn-off voltage slope RL= 4.3Ω
off
Switching energy losses during t
won
Switching energy losses during
t
woff
RL= 4.3Ω (see Figure 6.)0.2 mJ
RL= 4.3Ω (see Figure 6.)0.3 mJ
See
Figure 19.
See
Figure 21.
V/µs
V/µs
Doc ID 12730 Rev 6 9/31
Electrical specifications VNQ5027AK-E

Table 8. Current Sense (8V<VCC<16V)

Symbol Parameter Test conditions Min. Typ. Max. Unit
I
= 0.5A;
OUT
dK
dK
dK
K
0
0/K0
K
1
1/K1
K
2
2/K2
K
3
I
OUT/ISENSE
(1)
Current sense ratio drift
I
OUT/ISENSE
(1)
Current sense ratio drift
I
OUT/ISENSE
(1)
Current sense ratio drift
I
/ I
OUT
SENSE
V
= 0.5 V; V
SENSE
= -40°C...150°C
T
j
I
= 0.5A; V
OUT
= 0V;
V
CSD
= -40 °C to 150 °C
T
J
I
= 2A;
OUT
V
SENSE
= 4 V; V
SENSE
CSD
Tj= -40°C...150°C
= 25°C...150°C
T
j
I
= 2A; V
OUT
V
CSD
= -40 °C to 150 °C
T
J
I
OUT
V
SENSE
= -40°C...150°C
T
j
= 0V;
= 3A;
= 4 V; V
SENSE
CSD
Tj= 25°C...150°C
I
= 3A; V
OUT
V
CSD
= -40 °C to 150 °C
T
J
I
OUT
V
SENSE
= -40°C...150°C
T
j
= 0V;
= 10A;
= 4 V; V
SENSE
CSD
Tj= 25°C...150°C
CSD
= 0.5V;
=0 V;
= 4V;
=0 V;
= 4V;
= 0 V;
=0 V;
1680 2910 4120
-12 12 %
2050 2190
2700 2700
3410 3210
-10 10 %
2260 2350
2690 2690
3160 3030
-7 7 %
2490 2590
2700 2700
2870 2800
I
= 10A; V
OUT
V
= 0V;
CSD
= -40 °C to 150 °C
T
J
I
= 0A; V
OUT
= 5V; VIN= 0V;
V
CSD
= -40°C...150°C
T
j
= 0V; VIN= 5V;
V
CSD
= -40°C...150°C
T
j
= 2A; V
I
OUT
= 5V; VIN= 5V;
V
CSD
dK
3/K3
I
SENSE0
(1)
Current sense ratio drift
Analog sense leakage current
Tj= -40°C...150°C
I
V
SENSE
OL
open load on-state current detection threshold
Max analog sense output voltage
V
I
OUT
IN
= 5V, I
= 3A; V
10/31 Doc ID 12730 Rev 6
= 4 V;
SENSE
-4 4 %
= 0V;
SENSE
0
0
= 0V;
SENSE
0
= 5 µA 5 30 mA
SENSE
= 0V 5 V
CSD
µA
1
µA
2
µA
1
VNQ5027AK-E Electrical specifications
Table 8. Current Sense (8V<VCC<16V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
SENSEH
I
SENSEH
t
DSENSE1H
t
DSENSE1L
t
DSENSE2H
Analog sense output voltage in over temperature condition
Analog sense output current in over temperature condition
Delay response time from falling edge of CS_DIS pin
Delay response time from rising edge of CS_DIS pin
Delay response time from rising edge of INPUT pin
Delay response time between
Δ
t
DSENSE2H
rising edge of output current and rising edge of current sense
t
DSENSE2L
1. Parameter guaranteed by design; it is not tested.
Delay response time from falling edge of input pin
= 13V; R
V
CC
V
CC
V
SENSE
I
SENSE
= 13V; V
SENSE
SENSE
<4V, 0.5A<Iout<10A
= 90% of I
(see Figure 4.)
<4V, 0.5A<Iout<10A
V
SENSE
=10% of I
I
SENSE
(see Figure 4.)
<4V, 0.5A<Iout<10A
V
SENSE
=90% of I
I
SENSE
(see Figure 4.)
V I
SENSE
I
OUT
I
OUTMAX
V I
<4V,
SENSE
= 90% of I
= 90% of I
=2A (see Figure 5)
<4V, 0.5A<Iout<10A
SENSE
=10% of I
SENSE
(see Figure 4.)
= 3.9KΩ 9V
= 5V 8 mA
SENSE max
SENSE max
SENSE max
SENSEMAX,
OUTMAX
SENSE max
50 100 µs
520µs
70 300 µs
200 µs
100 250 µs

Table 9. Protection

(1)
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
I
T
T
T
HYST
V
DEMAG
V
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
DC short circuit current
limH
Short circuit current
limL
during thermal cycling
Shutdown temperature 150 175 200 °C
TSD
T
Reset temperature TRS + 1 TRS + 5 °C
R
Thermal reset of
RS
STATUS
Thermal hysteresis (T
TSD-TR
)
Turn-off output voltage clamp
Output voltage drop
ON
limitation
VCC=13V 5V<VCC<36V
=13V; TR<Tj<T
V
CC
= 2A; VIN=0; L=6mH VCC-41 VCC-46 VCC-52 V
I
OUT
=0.2A; Tj=-40°C...150°C
I
OUT
TSD
(see Figure 9.)
29 42 59
59
A A
16 A
135 °C
7°C
25 mV
Doc ID 12730 Rev 6 11/31
Electrical specifications VNQ5027AK-E

Table 10. Logic input

Symbol Parameter Test conditions Min. Typ. Max. Unit
V
I
V
I
V
I(hyst)
V
V
CSDL
I
CSDL
V
CSDH
I
CSDH
V
CSD(hyst)
V
CSCL
Input low level voltage 0.9 V
IL
Low level input current VIN= 0.9V 1 µA
IL
Input high level voltage 2.1 V
IH
High level input current VIN= 2.1V 10 µA
IH
Input hysteresis voltage 0.25 V
I
Input clamp voltage
ICL
IN
I
IN
CS_DIS low level voltage 0.9 V
Low level CS_DIS current V
CSD
CS_DIS high level voltage 2.1 V
High level CS_DIS current V
CSD
CS_DIS hysteresis voltage 0.25 V
I
CS_DIS clamp voltage
CSD
I
CSD

Figure 4. Current sense delay characteristics

INPUT
CS_DIS
= 1mA
= -1mA
5.5
-0.7
7V
=0.9V 1 µA
=2.1V 10 µA
= 1mA
= -1mA
5.5
-0.7
7V
V
V
LOAD CURRENT
SENSE CURRENT
t
DSENSE2H
t
DSENSE1L
t
DSENSE1H
t
DSENSE2L
12/31 Doc ID 12730 Rev 6
VNQ5027AK-E Electrical specifications
Figure 5. Delay response time between rising edge of output current and rising
edge of Current Sense (CS enabled)
V
IN
Δ
t
DSENSE2H
t
I
OUT
90% I
OUTMAX
I
OUTMAX
t
I
SENSE

Figure 6. Switching characteristics

V
OUT
t
Won
80%
dV
/dt
OUT
(on)
t
r
INPUT
t
d(on)
90% I
10%
I
SENSEMAX
SENSEMAX
t
d(off)
t
Woff
90%
t
f
dV
OUT
/dt
t
(off)
t
t
Doc ID 12730 Rev 6 13/31
Electrical specifications VNQ5027AK-E
Figure 7. I
I
/ I
out
sense
OUT/ISENSE
vs I
OUT
4500
4000
3500
3000
2500
2000
max Tj = -40 °C to 150 °C
max Tj = 25 °C to 150 °C
min Tj = 25 °C to 150 °C
min Tj = -40 °C to 150 °C
typical value
1500
1000
246810
I
(A)
OUT

Figure 8. Maximum current sense ratio drift vs load current

dk/k(%)
15
10
5
0
-5
-10
-15
2345678910
Note: Parameter guaranteed by design; it is not tested.
I
OUT
(A)
14/31 Doc ID 12730 Rev 6
VNQ5027AK-E Electrical specifications

Table 11. Truth table

Conditions Input Output Sense (V
Normal operation
L
H
L H
CSD
0
Nominal
=0V)
(1)
Overtemperature
Undervoltage
Short circuit to GND (Rsc ≤ 10 mΩ)
Short circuit to V
CC
Negative output voltage clamp
1. If the V and external circuit.
is high, the SENSE output is at a high impedance, its potential depends on leakage currents
CSD
L
H
L
H
L H H
L H
LL 0

Figure 9. Output voltage drop limitation

Vcc-Vout
Tj=150oC
Tj=25
Tj=-40
L L
L L
L L L
V
SENSEH
H H
o
C
o
C
0
V
SENSEH
0 0
0
0 if T
< T
j
if Tj > T
0
< Nominal
TSD
TSD
Von
Iout
Von/R on(T)

Table 12. Electrical transient requirements (part 1/3)

ISO 7637-2:
2004(E)
test pulse
Test levels
III IV
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
Impedance
1 -75 V -100 V 5000 pulses 0.5 s 5 s 2 ms, 10 Ω
2a +37 V +50 V 5000 pulses 0.2 s 5 s 50 µs, 2 Ω
3a -100 V -150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b +75 V +100 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
Doc ID 12730 Rev 6 15/31
Electrical specifications VNQ5027AK-E
Table 12. Electrical transient requirements (part 1/3) (continued)
ISO 7637-2:
2004(E)
test pulse
Test levels
III IV
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
Impedance
4 -6 V -7 V 1 pulse 100 ms, 0.01 Ω
5b
(2)
+65 V +87 V 1 pulse 400 ms, 2 Ω

Table 13. Electrical transient requirements (part 2/3)

ISO 7637-2:
Test level results
2004(E)
test pulse
III IV
1C C
2a C C
3a C C
3b C C
4C C
(2)
5b
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
CC
(1)

Table 14. Electrical transient requirements (part 3/3)

Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure
E
to disturbance and cannot be returned to proper operation without replacing the device.
16/31 Doc ID 12730 Rev 6
VNQ5027AK-E Electrical specifications

2.4 Electrical characteristics curves

Figure 10. Off-state output current Figure 11. High level input current

Iloff (nA)
1000
900
800
700
600
500
400
300
200
100
0
-50 -25 0 25 50 75 100 125 150 175
Off State Vcc=13V
Tc (°C)
Iih (µA)
5
4,5
4
3,5
3
2,5
2
1,5
0,5
0
Vin=2.1V
1
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)

Figure 12. Input clamp voltage Figure 13. Input low level

Vicl (V)
8
7,5
7
6,5
6
5,5
5
lin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Vil (V)
2
1,8
1,6
1,4
1,2
1
0,8
0,6
0,4
0,2
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)

Figure 14. Input high level Figure 15. Input hysteresis voltage

Vih (V)
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Doc ID 12730 Rev 6 17/31
Vihyst (V)
1
0,9
0,8
0,7
0,6
0,5
0,4
0,3
0,2
0,1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Electrical specifications VNQ5027AK-E
Figure 16. On-state resistance vs T
Ron (mOhm)
100
80
60
40
20
0
-50 -25 0 25 50 75 100 125 150 175
Iout= 3A
Vcc=13V
Tc (°C)
case
Figure 17. On-state resistance vs V
Ron (mOhm)
60
50
Tc=150°C
40
Tc=125°C
30
Tc=25°C
20
Tc=-40°C
10
0
0 5 10 15 20 25 30 35 40
Vcc (V)

Figure 18. Undervoltage shutdown Figure 19. Turn-on voltage slope

Vusd (V)
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Figure 20. I
LIMH
vs T
case
(dVout/dt )On (V/ms)
1000
900
800
700
600
500
400
300
200
100
0
-50 -25 0 25 50 75 100 125 150 175
Vcc=13V
RI=4.3 Ohm
Tc (°C)

Figure 21. Turn-off voltage slope

CC
Ilimh (A)
60
55
Vcc=13V
50
45
40
35
30
25
20
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
18/31 Doc ID 12730 Rev 6
(dVout/dt )Off (V/ms)
600
550
500
450
400
350
300
250
200
150
100
50
0
-50 -25 0 25 50 75 100 125 150 175
Vcc=13V
RI= 4.3 Ohm
Tc (°C)
VNQ5027AK-E Electrical specifications

Figure 22. CS_DIS high level voltage Figure 23. CS_DIS clamp voltage

Vcsdh (V)
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)

Figure 24. CS_DIS low level voltage

Vcsdl (V)
3
2,5
2
Vcsdcl(V)
10
9
8
Icsd = 1 mA
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
1,5
1
0,5
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Doc ID 12730 Rev 6 19/31
Application information VNQ5027AK-E

3 Application information

Figure 25. Application schematic

+5V
V
CC
R
prot
μ
C
R
prot
CS_DIS
IINPUT
OUTPUT
D
ld
R
prot
C
ext
CURRENT SENSE
R
SENSE
V
GND
GND
R
GND
D
GND
Note: Channel 2, 3, 4 have the same internal circuit as channel 1.

3.1 GND protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (R
This can be used with any type of load.
The following is an indication on how to dimension the R
1. R
2. R
where -I maximum rating section of the device datasheet.
≤ 600mV / (I
GND
≥ (−VCC) / (-I
GND
is the DC reverse ground pin current and can be found in the absolute
GND
S(on)max
GND
).
)
GND
only)
resistor.
GND
Power Dissipation in R
P
= (-VCC)2/R
D
GND
(when VCC<0: during reverse battery situations) is:
GND
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the R
will produce a shift (I
GND
S(on)max
values. This shift will vary depending on how many devices are ON in the case of several
* R
high side drivers sharing the same R
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
20/31 Doc ID 12730 Rev 6
S(on)max
) in the input thresholds and the status output
GND
.
GND
becomes the sum of the
VNQ5027AK-E Application information
3.1.2 Solution 2: a diode (D
A resistor (R
= 1kΩ) should be inserted in parallel to D
GND
) in the ground line
GND
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (≈600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the V
max DC rating. The same applies if the device is subject to transients on the VCC line
CC
that are greater than the ones shown in the ISO T/R 7637/1 table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (R prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of I/Os.
if the device drives an
GND
prot
) in line to
µC and the
µC
-V
CCpeak/Ilatchup
≤ R
prot
≤ (V
OHµC-VIH-VGND
) / I
IHmax
Calculation example:
For V
5kΩ ≤ R
Recommended values: R
CCpeak
prot
= - 100V and I
≤ 180kΩ.
latchup
= 10kΩ, C
prot
≥ 20mA; V
EXT
≥ 4.5V
OHµC
= 10nF.
Doc ID 12730 Rev 6 21/31
Application information VNQ5027AK-E

Figure 26. Waveforms

NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
V
V
CC
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
V
USD
USDhyst
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
T
j
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
T
R
T
T
TSD
RS
current
limitation
<Nominal
power limitation
SHORT TO V
CC
<Nominal
OVERLOAD OPERATION
thermal cycling
SHORTED LOAD NORMAL LOAD
I
LIMH
I
LIML
V
SENSEH
22/31 Doc ID 12730 Rev 6
VNQ5027AK-E Application information

3.4 Maximum demagnetization energy (VCC=13.5V)

Figure 27. Maximum turn-off current versus inductance (for each channel)

100
A
10
I (A)
1
0,1 1 10 100L (mH)
B
C
A: T
B: T
C: T
VIN, I
= 150°C single pulse
jstart
= 100°C repetitive pulse
jstart
= 125°C repetitive pulse
jstart
L
Note: Values are generated with R
In case of repetitive pulses, T must not exceed the temperature specified above for curves A and B.
Demagnetization Demagnetization Demagnetization
=0Ω.
L
(at beginning of each demagnetization) of every pulse
jstart
t
Doc ID 12730 Rev 6 23/31
Package and PC board thermal data VNQ5027AK-E

4 Package and PC board thermal data

4.1 PowerSSO-24™ thermal data

Figure 28. PowerSSO-24™ PC board

Note: Layout condition of R
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm
Figure 29.
RTHj_amb(°C/ W)
R
thj-amb
55
50
45
40
35
30
0246810
and Zth measurements (PCB: Double layer, Thermal Vias, FR4
th
2
).
vs PCB copper area in open box free air condition (one channel ON)
PCB Cu heatsink area (cm^ 2)
24/31 Doc ID 12730 Rev 6
VNQ5027AK-E Package and PC board thermal data
Figure 30.
PowerSSO-24™ thermal impedance junction ambient single pulse (one channel on)
ZTH (°C/W)
1000
100
10
1
0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
Footprint
2
2 cm
8 cm
2

Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24™

(a)
a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Doc ID 12730 Rev 6 25/31
Package and PC board thermal data VNQ5027AK-E
Equation 1: pulse calculation formula
Z
where

Table 15. Thermal parameters

R1=R7=R9=R11 (°C/W) 0.28
R2=R8=R10=R12 (°C/W) 0.9
R3 (°C/W) 6
R4 (°C/W) 7.7
R5 (°C/W) 9 9 8
R6 (°C/W) 28 17 10
C1=C7=C9=C11 (W.s/°C) 0.001
C2=C8=C10=C12 (W.s/°C) 0.003
C3 (W.s/°C) 0.025
THδ
RTHδ Z
δ tpT⁄=
Area/island (cm2)Footprint28
THtp
1 δ–()+⋅=
C4 (W.s/°C) 0.75
C5 (W.s/°C) 1 4 9
C6 (W.s/°C) 2.2 5 17
26/31 Doc ID 12730 Rev 6
VNQ5027AK-E Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
®
is an ST trademark.

5.2 PowerSSO-24™ mechanical data

Figure 32. PowerSSO-24™ package dimensions

.
Doc ID 12730 Rev 6 27/31
Package and packing information VNQ5027AK-E

Table 16. PowerSSO-24™ mechanical data

Millimeters
Symbol
Min Typ Max
A 2.45
A2 2.15 2.35
a1 0 0.1
b0.33 0.51
c0.23 0.32
D 10.10 10.50
E7.4 7.6
e0.8
e3 8.8
F2.3
G 0.1
H 10.1 10.5
h 0.4
k0° 8°
L0.55 0.85
O1.2
Q0.8
S2.9
T3.65
U1.0
N 10°
X4.1 4.7
Y6.5 7.1
28/31 Doc ID 12730 Rev 6
VNQ5027AK-E Package and packing information

5.3 Packing information

Figure 33. PowerSSO-24™ tube shipment (no suffix)

Base Q.ty 49 Bulk Q.ty 1225
C
B
A

Figure 34. PowerSSO-24™ tape and reel shipment (suffix “TR”)

Tube length (± 0.5) 532 A 3.5 B 13.8 C (± 0.1) 0.6
All dimensions are in mm.
Reel dimensions
Base Q.ty 1000 Bulk Q.ty 1000 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 24.4 N (min) 100 T (max) 30.4
Tape dimensions
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986
Tape width W 24 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 12 Hole Diameter D (± 0.05) 1.55 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.1) 11.5 Compartment Depth K (max) 2.85 Hole Spacing P1 (± 0.1) 2
All dimensions are in mm.
End
Start
Top
cover
tape
500mm min
Empty components pockets saled with cover tape.
User direction of feed
No componentsNo components Components
500mm min
Doc ID 12730 Rev 6 29/31
Revision history VNQ5027AK-E

6 Revision history

Table 17. Document revision history

Date Revision Changes
17-Nov-2006 1 Initial release.
Table 4: Absolute maximum ratings: E
max value changed from
MAX
82 to 140 mJ. Updated Table 8: Current Sense (8V<V
CC
<16V):
– added dK0/K0 parameter – added K – added dK
parameter
1
parameter
1/K1
– added dK2/K2 parameter – added dK – added
3/K3
Δ
t
DSENSE2H
parameter
parameter
– added IOL parameter
18-Dec-2007 2
Added Figure 5: Delay response time between rising edge of output
current and rising edge of Current Sense (CS enabled).
Added Figure 7: I
OUT/ISENSE
vs I
OUT
Added Figure 8: Maximum current sense ratio drift vs load current. Added Section 2.4: Electrical characteristics curves. Added Section 3.4: Maximum demagnetization energy
(VCC = 13.5V). Figure 31: Thermal fitting model of a double channel HSD in
PowerSSO-24™: added note.
Added ECOPACK® packages information. Update Section 5.2: PowerSSO-24™ mechanical data.
12-Feb-2008 3
10-Apr-2008 4
Corrected typing error in Table 8: Current Sense (8V<V changed I
test condition from VIN = 0V to VIN = 5V.
OL
Corrected Figure 27: Maximum turn-off current versus inductance
(for each channel).
CC
<16V):
Table 16: PowerSSO-24™ mechanical data:
– Deleted A (min) value – Changed A (max) value from 2.47 to 2.45
19-Jun-2009 5
– Changed A2 (max) value from 2.40 to 2.35 – Changed a1 (max) value from 0.075 to 0.1 – Added F row – Updated k row
Updated Figure 32: PowerSSO-24™ package dimensions.
22-Jul-2009 6
Updated Table 16: PowerSSO-24™ mechanical data: – Deleted G1 row – Added O, Q, S, T and U rows
30/31 Doc ID 12730 Rev 6
VNQ5027AK-E
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Doc ID 12730 Rev 6 31/31
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